DC-DC CONVERTER FOR REDUCING VOLTAGE RIPPLE OF OUTPUT VOLTAGE AND METHOD OF CONTROLLING THE SAME

Abstract

An auxiliary circuit for reducing an output voltage ripple of a DC-DC converter includes: a capacitor configured to perform charging and discharging, a main buck converter including a first switch and a second switch connected to a voltage source, and a first inductor connected between the capacitor and a contact point of the first switch and the second switch, the first inductor having a first inductor current that flows therethrough, and an auxiliary buck converter including a third switch and a fourth switch respectively connected to the first switch and the second switch in parallel, and a second inductor connected between the capacitor and a contact point of the third switch and the fourth switch, the second inductor having a second inductor current that flows therethrough, and the auxiliary buck converter configured to control the second inductor current by generating two envelopes with different heights to compensate for a difference between the first inductor current and an output current.

Claims

1. A DC-DC converter for reducing an output voltage ripple comprising: a capacitor configured to perform charging and discharging; a main buck converter including: a first switch and a second switch connected to a voltage source, and a first inductor connected between the capacitor and a contact point of the first switch and the second switch, the first inductor having a first inductor current that flows therethrough; and an auxiliary buck converter including: a third switch and a fourth switch respectively connected to the first switch and the second switch in parallel, and a second inductor connected between the capacitor and a contact point of the third switch and the fourth switch, the second inductor having a second inductor current that flows therethrough, and the auxiliary buck converter configured to control the second inductor current by generating two envelopes with different heights to compensate for a difference between the first inductor current and an output current.

2. The DC-DC converter of claim 1, wherein the auxiliary buck converter controls the second inductor current by selectively using the two envelopes.

3. The DC-DC converter of claim 2, wherein the auxiliary buck converter controls the second inductor current in the form of a triangular wave in an envelope which is selected by the auxiliary buck converter.

4. The DC-DC converter of claim 3, wherein the auxiliary buck converter selects and controls a higher envelope of the two envelopes to form a first triangular wave of the second inductor current.

5. The DC-DC converter of claim 4, wherein the auxiliary buck converter selects and controls a lower envelope of the two envelopes to form second and subsequent triangular waves of the second inductor current.

6. The DC-DC converter of claim 1, wherein the auxiliary buck converter further includes: a first envelope generator configured to generate a first envelope by using the first inductor current and the output current; and a second envelope generator configured to generate a second envelope by using the first inductor current and the output current.

7. The DC-DC converter of claim 6, wherein the first envelope generator and the second envelope generator are implemented by either an analog circuit or a digital code instruction.

8. The DC-DC converter of claim 1, wherein the auxiliary buck converter controls an output voltage to be constant even when the output current fluctuates.

9. A method of controlling a DC-DC converter to reduce an output voltage ripple through an auxiliary buck converter connected to a main buck converter in parallel, the method comprising: generating two envelopes with different heights by using a first inductor current and an output current generated from the DC-DC converter; selecting a first envelope, which is higher of the two envelopes, to control a second inductor current; using a triangular wave in the first envelope to form a first triangular wave of the second inductor current; selecting a second envelope, which is lower of the two envelopes, to control the second inductor current; and using a triangular wave in the second envelope to form second and subsequent triangular waves of the second inductor current.

10. The method of claim 9, wherein the generating the two envelopes with different heights is implemented by either an analog circuit or a digital code instruction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0023] FIG. 1 is a circuit diagram of a DC-DC converter including a main buck converter and an auxiliary buck converter;

[0024] FIG. 2 is a view illustrating a mode-specific operation and a main waveform of a DC-DC converter circuit in FIG. 1;

[0025] FIG. 3 is a view illustrating an example of an envelope for describing double envelope control of the present disclosure;

[0026] FIG. 4 is a view for describing the double envelope control according to the present disclosure;

[0027] FIG. 5 illustrates examples of a circuit diagram and a control block diagram to which the present disclosure is applied;

[0028] FIG. 6 is a graph illustrating the relationship between a magnitude (k.sub.1) of an envelope and time delay (Δt.sub.d);

[0029] FIG. 7A illustrates k.sub.1 in the control block diagram in FIG. 5, and FIG. 7B illustrates an example of a circuit for implementing k.sub.1;

[0030] FIG. 8 is a graph illustrating the relationship between a magnitude (k.sub.c) of the envelope and an output voltage (v.sub.o);

[0031] FIG. 9A illustrates k.sub.c in the control block diagram in FIG. 5, and FIG. 9B illustrates an example of a circuit for implementing k.sub.c;

[0032] FIG. 10A illustrates a simulation result of single envelope control, and FIG. 10B illustrates a simulation result of the double envelope control according to the present disclosure; and

[0033] FIG. 11 is a flow chart of a method of controlling a DC-DC converter for reducing an output voltage ripple according to one embodiment of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0034] The following detailed description of the present disclosure refers to the accompanying drawings illustrating specific embodiments in which the present disclosure may be performed by way of example. These embodiments are described in detail so that those skilled in the art may sufficiently perform the present disclosure. It should be understood that the various embodiments of the present disclosure are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the present disclosure. Further, it should be understood that a position or disposition of an individual component in each disclosed embodiment may be changed without departing from the spirit and scope of the present disclosure. Accordingly, the following detailed description is not intended to be taken in a limiting sense, and the scope of the present disclosure is limited only by the appended claims, in addition to all scope equivalent to the claims when appropriately described. Similar reference numerals in the drawings indicate the same or similar functions throughout the various aspects.

[0035] Hereinafter, preferable embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0036] FIG. 1 is a circuit diagram of a DC-DC converter including a main buck converter and an auxiliary buck converter. FIG. 2 is a view illustrating a mode-specific operation and a main waveform of a DC-DC converter circuit of FIG. 1.

[0037] When a load current (an output current) of a converter fluctuates, an output voltage of the converter does not maintain a constant value but fluctuates, and the present disclosure proposes an auxiliary circuit for controlling a DC-DC converter in order to suppress the fluctuation (ripple).

[0038] Referring to FIG. 1, a first switch Q.sub.1, a second switch Q.sub.2, and a first inductor L.sub.1 constitute the main buck converter, and a third switch Q.sub.3, a fourth switch Q.sub.4 and a second inductor L.sub.2 constitute the auxiliary buck converter (or auxiliary circuit). These converters are driven to maintain the output voltage v.sub.O constant even when an output current i.sub.O fluctuates.

[0039] The main buck converter and the auxiliary buck converter may be connected in parallel with the same type of circuit. A voltage source V.sub.in may supply DC power, and the main buck converter may be connected to the voltage source V.sub.in.

[0040] A capacitor C.sub.o may be connected to the other end of the main buck converter to perform at least one operation of charging or discharging according to operation of the main buck converter.

[0041] Accordingly, the main buck converter may operate as a switch controlling a direction of a DC current transmitted from a contact point of at least one of the voltage source V.sub.in or the capacitor C.sub.o connected to the other end.

[0042] Further, the capacitor C.sub.o may rectify an AC current from an output current from the main buck converter or the auxiliary buck converter.

[0043] A load may be connected to a contact point of the main buck converter and the capacitor C.sub.o, and a preset load current may flow through the load.

[0044] In this case, the load may include an external apparatus which uses DC power, and accordingly, load currents i.sub.O of different magnitudes may flow through the load, and the magnitude of the load current may vary according to operation of the load.

[0045] Here, the load may operate as a current source, and accordingly, when a current required in the load changes, it may be understood that a magnitude of the current source also changes, and it may be understood that a current flowing by the current source is the load current.

[0046] In this case, the load current i.sub.O may be appeared in various forms, such as a triangular wave, a sine wave, a sawtooth wave, a square wave, and the like.

[0047] The auxiliary buck converter is connected to the main buck converter in parallel, and may compensate for an inrush current shown up by a difference between a current flowing from the main buck converter to a contact point of the load and the capacitor C.sub.o and the load current i.sub.O.

[0048] Here, the inrush current may refer to at least one element of a deficiency or excess of the output current of the main buck converter for the load current i.sub.O which may be generated while a current flowing from the main buck converter to the load follows the load current when the load current flowing through the load changes according to the operation of the load.

[0049] Accordingly, it may be understood that the auxiliary buck converter reduces a ripple phenomenon which may occur in the output voltage of the main buck converter when the load current changes according to the operation of the load.

[0050] Meanwhile, the auxiliary buck converter may operate as a switch which controls a direction in which the DC current transmitted from a contact point with at least one of the voltage source V.sub.in and the capacitor C.sub.o connected to the other end flows.

[0051] The main buck converter may include the first switch Q.sub.1, the second switch Q.sub.2, and the first inductor L.sub.1.

[0052] The first switch Q.sub.1 may be connected to the voltage source V.sub.in, and the second switch Q.sub.2 may be connected to the voltage source V.sub.in in parallel at the other end of the first switch Q.sub.1.

[0053] Further, the first inductor L.sub.1 may be connected to a contact point of the first switch Q.sub.1 and the second switch Q.sub.2, and the other end of the first inductor L.sub.1 may be connected to a contact point of the capacitor C.sub.o and the load.

[0054] In this case, a semiconductor element such as a MOS field-effect transistor (MOSFET) or the like may be used as the first switch Q.sub.1 and the second switch Q.sub.2, and as shown in FIG. 1, each MOSFET may be provided with a diode connected to the MOSFET in parallel.

[0055] Further, a constant voltage may be input to a gate of each MOSFET so that a drain and a source of the MOSFET are conductive. In this case, the voltage source, which inputs a voltage to the gate, may be the voltage source V.sub.in, and may include a voltage source which inputs a voltage to the gate.

[0056] Meanwhile, while the capacitor C.sub.o performs charging, the first switch Q.sub.1 may be turned on and the second switch Q.sub.2 may be blocked, and while the capacitor C.sub.o performs discharging, the second switch Q.sub.2 may be turned on and the first switch Q.sub.1 may be blocked.

[0057] Here, when the load current flowing through the load is maintained at a constant magnitude, since the charging and the discharging of the capacitor C.sub.o are alternately performed and the auxiliary buck converter is electrically blocked, the first switch Q.sub.1 and the second switch Q.sub.2 of the main buck converter may be alternately turned on or blocked so that the charging and the discharging is performed in the capacitor C.sub.o.

[0058] In this case, the first inductor L.sub.1 may be connected to the capacitor C.sub.o to operate as a low pass filter, and to this end, the first inductor L.sub.1 and the capacitor C.sub.o may each be provided in a size sufficient to stably supply a current to the load.

[0059] Meanwhile, when the load current flowing through the load increases according to the operation of the load, the first switch Q.sub.1 may be turned on and the second switch Q.sub.2 may be blocked, and a state of each of the first switch Q.sub.1 and the second switch Q.sub.2 may be maintained while an inrush current, generated due to a difference between the current flowing in the first inductor L.sub.1 (hereinafter, a first inductor current, i.sub.L1) due to an increase in the load current and the load current i.sub.O, is present.

[0060] In this regard, the inrush current may be understood as referring to the difference between the first inductor current i.sub.L1and the load current i.sub.O flowing through the load.

[0061] Further, when the load current flowing through the load decreases according to the operation of the load, the first switch Q.sub.1 may be blocked and the second switch Q.sub.2 may be turned on, and the state of each of the first switch Q.sub.1 and the second switch Q.sub.2 may be maintained while an inrush current generated by a decrease in the load current i.sub.O is present.

[0062] The auxiliary buck converter may include the third switch Q.sub.3, the fourth switch Q.sub.4, and the second inductor L.sub.2.

[0063] The third switch Q.sub.3 may be connected to the voltage source V.sub.in, and the fourth switch Q.sub.4 may be connected to the voltage source V.sub.in in parallel at the other end of the third switch Q.sub.3.

[0064] In this regard, it may be understood that the third switch Q.sub.3 is connected to a contact point of the voltage source V.sub.in and the first switch Q.sub.1.

[0065] Further, the second inductor L.sub.2 may be connected to a contact point of the third switch Q.sub.3 and the fourth switch Q.sub.4, and the other end of the second inductor L.sub.2 may be connected to the contact point of the capacitor C.sub.o and the load.

[0066] In this regard, it may be understood that the second inductor L.sub.2 is connected to a contact point of the first inductor L.sub.1, the capacitor C.sub.o, and the load.

[0067] In this case, a semiconductor element such as a MOSFET or the like may be used as the third switch Q.sub.3 and the fourth switch Q.sub.4, and as shown in FIG. 1, each MOSFET may be provided with a diode connected to the MOSFET in parallel.

[0068] Further, a constant voltage may be input to a gate of each MOSFET so that a drain and a source of the MOSFET are conductive.

[0069] In this case, a voltage may be input to the gate by the voltage source V.sub.in, and the MOSFET may include a voltage source which inputs a voltage to the gate. Meanwhile, when the magnitude of the load current flowing through the load is constantly maintained and the first switch Q.sub.1 and the second switch Q.sub.2 are alternately turned on and blocked, the third switch Q.sub.3 and the fourth switch Q.sub.4 may be blocked.

[0070] Further, when an inrush current is generated due to a change in magnitude of the load current flowing through the load, the first switch Q.sub.1 and the second switch Q.sub.2 may each maintain a constant state, and the third switch Q.sub.3 and the fourth switch Q.sub.4 may be alternately turned on and blocked.

[0071] Meanwhile, the second inductor L.sub.2 may be connected to the capacitor C.sub.o to operate as a low pass filter, and to this end, the second inductor L.sub.2 and the capacitor C.sub.o may each be provided in a size sufficient to supply a stable load current to the load.

[0072] Main voltages and current waveforms of the converter system in FIG. 1 are shown in FIG. 2. When a current flowing in the second inductor L.sub.2 (hereinafter, a second inductor current, i.sub.L2) is controlled in the form of a triangular wave within a linear envelope P.sub.env of appropriate magnitude, high efficiency may be achieved and the ripple of the output voltage v.sub.O may be reduced through soft switching of the auxiliary circuit.

[0073] However, this method assumes that there is no time delay (delay) in a control circuit, there is no parasitic component of the converter, and the output current i.sub.O also changes in a perfect stepwise form, and thus is not suitable for implementation of an actual circuit.

[0074] In the present disclosure, even when the above-described non-ideal characteristics which occur when the actual converter is implemented, that is, delay in the control circuit, converter parasitic components, output current i.sub.O fluctuations in which the output current (i.sub.O) is not the perfect stepwise form, and the like are present, two envelopes are generated and used for control so that the output voltage v.sub.O is precisely controlled (that is, the ripple is minimized). In the present disclosure, this is referred to as double envelope control.

[0075] An example of the envelope is shown in FIG. 3. When a height of the envelope is set as k.sub.cB, the second inductor current i.sub.L2 operates as shown in a Ideal cycle-by-cycle CCB dashed line. In this case, it can be seen that the output voltage v.sub.O also operates as a dashed line at the very bottom, and the time taken to reach a target voltage V.sub.ref, that is, a settling time is very long due to the above-described non-ideal characteristic.

[0076] In order to reduce the settling time, the envelope height may be set like k.sub.tB or k.sub.1B, which is greater than k.sub.cB, and in the case of k.sub.tB (a waveform with second largest initial value, Transient-wise CCB), although the settling time is reduced, there is a limit in reduction, and when the envelope height is set as k.sub.1B (a waveform with largest initial value, First cycle CCB), the settling time is minimized, but it can be seen that the output voltage v.sub.O is overcompensated (the output voltage v.sub.O is generated above V.sub.ref).

[0077] Accordingly, the present disclosure proposes a control method (Cycle-by-Cycle CCB) selectively using an envelope of a height k.sub.1B to form a first triangular wave of the second inductor current i.sub.L2 and an envelope of a height k.sub.cB to form a subsequent triangular wave. Through this manner, it is possible to minimize the ripple of the output voltage v.sub.O by removing overcompensation while minimizing the settling time.

[0078] The double envelope control according to the present disclosure is shown in FIG. 4. FIG. 5 illustrates examples of a circuit diagram and a control block diagram to which the present disclosure is applied.

[0079] The circuit diagram and the control block diagram in FIG. 5 are only examples, and the control block diagram may be implemented by various analog and digital methods.

[0080] The control of the present disclosure may be described and implemented similarly with the above manner even when the load current i.sub.O vertically drops.

[0081] In FIG. 4, a magnitude of a first envelope (an envelope with a relatively larger magnitude of the two envelopes) corresponds to (1+k.sub.1)*B. A subscript 1 is given to k.sub.1 in a sense that it is involved only in the first triangle of the second inductor current i.sub.L2.

[0082] As described above, k.sub.1 is designed in consideration of the non-ideal characteristics which are present in the actual converter (for example, delay (Δt.sub.d) in the control circuit, parasitic components of circuit elements, an output current i.sub.O fluctuation waveform that is not a perfect stepwise form, and the like). For example, a case of implementation where Δt.sub.d is significant and the remaining non-ideal characteristics are negligible is shown in FIG. 1, and k.sub.1 in this case may be expressed as the following Equation 1.

[00001]$\begin{array}{cc}{k}_1=\frac{\beta L_2^2\left(V_{in}-V_o\right)-\alpha V_o\left(L_1+L_2\right)}{L_2\left[\alpha V_o-\beta \left\{L_1{V}_o+L_2\left(V_{in}-V_o\right)\right\}\right]}\alpha =\sqrt{\begin{array}{c}{L}_1^3{L}_2{V}_{in}[L_1{L}_2{V_{in}\left(\Delta I_o+\Delta i_{L1}\right)}^2+\\ \Delta t_d{V}_o\left(V_m-V_o\right)\left\{2L_1\left(\Delta I_o+\Delta i_{L1}\right)-\Delta t_d\left(V_{in}-V_o\right)\right\}]\end{array}}\beta =L_1{V}_{in}\left\{L_1\left(\Delta I_o+\Delta i_{L1}\right)-\Delta t_d\left(V_{in}-V_o\right)\right\}& \left[\mathrm{Equation}1\right]\end{array}$

[0083] In the above Equation, V.sub.in refers to an input voltage of a converter, V.sub.O refers to an output voltage of the converter, L.sub.1 refers to the inductance of a main inductor (first inductor), L.sub.2 refers to the inductance of an auxiliary inductor (second inductor), and Δt.sub.d refers to the delay of a control circuit. For example, when all circuit design details are as shown in the following Table 1, the relationship between the magnitude k.sub.1 of the envelope and the time delay Δt.sub.d is shown as a solid line in a graph in FIG. 6.

TABLE-US-00001 TABLE 1 Parameter Description V.sub.in 15 V V.sub.O 3.3 V D 0.22 i.sub.O1 4 A i.sub.O2 15 A Switching frequency (f) of Q.sub.1 and Q.sub.2 200 kHz L.sub.1 10 μH L.sub.2 500 nH C.sub.O 220 μF

[0084] In the embodiment of the present disclosure, the first envelope may be implemented by an analog circuit or a digital code instruction, and for example, a configuration of the analog circuit may be implemented as shown in FIGS. 7A and 7B.

[0085] FIG. 7A illustrates k.sub.1 in the control block diagram in FIG. 5, and FIG. 7B illustrates an example of a circuit for implementing k.sub.1.

[0086] FIG. 7B illustrates a differential amplifier circuit, wherein s_iL1 refers to a main inductor current detection value and s_iO refers to an output current detection value. In the case in which resistance values of resistors R19 and R20 are selected as 1 kΩ, the first envelope env1 may be output when resistance values of resistors R22 and R23 are designed as k.sub.1*1 kΩ.

[0087] In FIG. 4, a magnitude of a second envelope (an envelope with a smaller magnitude of the two envelopes) corresponds to (1+k.sub.c)*B. k.sub.c is involved only in second and subsequent triangles of the second inductor current i.sub.L2, and a subscript c is given in a sense that the output voltage v.sub.O returns to the target voltage V.sub.ref in each triangle (cycle-by-cycle). Since the non-ideal characteristics are reflected in the first envelope, k.sub.c may be designed as in the following Equation 2 by assuming an ideal converter.

[00002]$\begin{array}{cc}{k}_e=\frac{L_1{V}_o-L_2\left(V_{in}-2V_o\right)}{L_1{V}_o+L_2\left(V_{in}-2V_o\right)}& \left[\mathrm{Equation}2\right]\end{array}$

[0088] When design specifications of the circuit are the same as in Table 1, the relationship between k.sub.c and the output voltage v.sub.O is the same as in the case in which Δt.sub.d=0 in the graph in FIG. 8. FIG. 8 is a graph illustrating the relationship between the magnitude k.sub.c of the envelope and the output voltage v.sub.O. Here, k.sub.p is k.sub.c when the output current vertically increases, and k.sub.n is k.sub.c when the output current vertically decreases.

[0089] In the embodiment of the present disclosure, the second envelope may be implemented by an analog circuit or a digital code instruction, and for example, a configuration of the analog circuit may be implemented as shown in FIGS. 9A and 9B.

[0090] FIG. 9A illustrates k.sub.c in the control block diagram in FIG. 5, and FIG. 9B illustrates an example of a circuit for implementing k.sub.c.

[0091] FIG. 9B illustrates a differential amplifier circuit, wherein s_iL1 refers to a main inductor current detection value and s_iO refers to an output current detection value. In the case in which resistance values of resistors R26 and R27 are selected as 1 kΩ, the second envelope env2 may be output when resistance values of resistors R24 and R25 are designed as k.sub.1*1 kΩ.

[0092] Hereinafter, a simulation performed to verify the performance of the present disclosure will be described. Simulation conditions are shown in Table 1.

[0093] A simulation result is shown in FIGS. 10A and 10B.

[0094] FIG. 10A illustrates a simulation result of single envelope control, and FIG. 10B illustrates a simulation result of the double envelope control according to the present disclosure.

[0095] Referring to FIGS. 10A and 10B, it can be seen that the double envelope control according to the present disclosure significantly reduces the settling time of the output voltage v.sub.O compared to the single envelope control.

[0096] Accordingly, the present disclosure minimizes the ripple of the output voltage through the double envelope control. Further, a control technique in the present disclosure is applicable to various converter circuits other than the buck converter.

[0097] FIG. 11 is a flow chart of a method of controlling a DC-DC converter for reducing an output voltage ripple according to one embodiment of the present disclosure.

[0098] A method of driving the auxiliary circuit for reducing the output voltage ripple of the DC-DC converter according to the embodiment may be performed in substantially the same configuration as that of the DC-DC converter in FIG. 1. Accordingly, the same reference numerals are given to the same components as those of the DC-DC converter in FIG. 1, and repeated descriptions are omitted.

[0099] Further, the method of controlling the DC-DC converter for reducing the output voltage ripple according to the embodiment may be executed by software (an application) for performing DC-DC converter control for reducing the output voltage ripple.

[0100] When the load current (the output current) of the converter fluctuates, the output voltage of the converter does not maintain a constant value and fluctuates, and the present disclosure proposes a method of controlling the DC-DC converter in order to suppress this fluctuation (ripple).

[0101] The method of controlling the DC-DC converter for reducing the output voltage ripple according to the embodiment of the present disclosure may be performed through an auxiliary buck converter connected to a main buck converter in parallel. The main buck converter and the auxiliary buck converter may have the circuits of the same type.

[0102] Referring to FIG. 11, in the method of controlling the DC-DC converter for reducing the output voltage ripple according to the embodiment, two envelopes with different heights by using a first inductor current and an output current generated from the DC-DC converter are generated (Operation S10).

[0103] In the present disclosure, even when the above-described non-ideal characteristics which occur when an actual converter is implemented, that is, delay in the control circuit, converter parasitic components, output current i.sub.O fluctuations in which the output current (i.sub.O) is not a perfect stepwise form, and the like are present, two envelopes are generated and used for control so that the output voltage v.sub.O is precisely controlled (that is, the ripple is minimized). In the present disclosure, this is referred to as double envelope control.

[0104] The operation of generating two envelopes with different heights may be implemented by either an analog circuit or a digital code instruction.

[0105] A first envelope, which is higher of the two envelopes, is selected to control a second inductor current (Operation S20). A triangular wave in the first envelope is used to form a first triangular wave of the second inductor current (Operation S30).

[0106] A second envelope, which is lower of the two envelopes, is selected to control a second inductor current (Operation S40). A triangular wave in the second envelope is used to form the second and subsequent triangular waves of the second inductor current (Operation S50).

[0107] Accordingly, the present disclosure proposes a control method selectively using the envelope of a relatively high height to form the first triangular wave of the second inductor current i.sub.L2 and the envelope of a relatively low height to form the subsequent triangular waves. Accordingly, it is possible to minimize the ripple of the output voltage v.sub.O by removing overcompensation while minimizing the settling time.

[0108] The method of driving the auxiliary circuit for reducing the output voltage ripple of the DC-DC converter may be implemented by either an application or in the form of program instructions which may be executed through various computer components to be recorded in a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, or the like alone or in combination.

[0109] The program instructions recorded on the computer-readable recording medium are specially designed and configured for the present disclosure, and may be known and used by those skilled in the field of computer software.

[0110] Examples of the computer-readable recording medium include magnetic media such as a hard disk, a floppy disk, and a magnetic tape, optical recording media such as a CD-ROM and a DVD, and magneto-optical media such as a floptical disk, and hardware devices such as a read only memory (ROM), a random access memory (RAM), a flash memory, and the like specially configured to store and execute program instructions.

[0111] Examples of the program instructions include not only machine language code such as that generated by a compiler, but also high-level language code which may be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules for performing the processing according to the present disclosure, and vice versa.

[0112] According to a DC-DC converter for reducing an output voltage ripple and a method of controlling the same, a ripple of an output voltage generated when a load current (output current) of a converter fluctuates can be minimized through double envelope control. Further, according to high-efficiency and high-precision driving of an auxiliary circuit proposed in the present disclosure, a ripple of an output voltage can be precisely suppressed to a very low level while increasing the driving efficiency of an auxiliary circuit itself.

[0113] In the above, although the present disclosure is described with reference to the embodiments of the present disclosure, those skilled in the art may variously modify and change the present disclosure within a range not departing from the spirit and area of the present disclosure disclosed in the claims which will be described below.

Industrial Applicability

[0114] The present disclosure minimizes a ripple of an output voltage through double envelope control, and thus can be usefully used for high-precision and high-efficiency converter control. Further, a control method in the present disclosure is applicable to various converter circuits other than a buck converter.