Method and device for reducing bit error rate in CDMA communication system

Abstract

A method and a device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system are described, wherein this method includes: a sample sequence I.sub.in of an in-phase component signal I, and a sample sequence Q.sub.in of a quadrature component signal Q are obtained, and the signals are sent by a signal sending end; the obtained sample sequence I.sub.in and the sample sequence Q.sub.in are divided into different groups according to a sample number Ns of a chip, a sum-average operation is performed on a signal in each group, and a corresponding signal group is determined, wherein, the signal group determined by performing the sum-average operation on the sample sequence I.sub.in is W.sub.I, the signal group determined by performing the sum-average operation on the sample sequence Q.sub.in is W.sub.Q; and a signal in the signal group W.sub.I and the signal group W.sub.Q is grouped to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, and the determined signal is output. The disclosure solves a problem in the related art that a CDMA synchronization method possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, and reduces the bit error rate.

Claims

1. A method for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system, comprising: obtaining, by a Front End Processor (FEP), a sample sequence I.sub.in of an in-phase component signal I, and a sample sequence Q.sub.in of a quadrature component signal Q, which are sent by a signal sending end; dividing the obtained sample sequence I.sub.in and the sample sequence Q.sub.in by adopting a first delayer into different groups according to a sample number Ns of a chip, performing a sum-average operation on a signal in each group, and determining a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence I.sub.in is W.sub.I, the signal group determined by performing the sum-average operation on the sample sequence Q.sub.in is W.sub.Q; and grouping, by adopting a second delayer, a signal in the signal group W.sub.I and the signal group W.sub.Q, to determine, through a matched filter, a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group W.sub.I and the signal group W.sub.Q, and outputting the determined signal; wherein the first delayer is added in the FEP, and second delayer is added between a FEP output and the matched filter; wherein the dividing the obtained sample sequence I.sub.in and the sample sequence Q.sub.in by adopting a first delayer into different groups according to the sample number Ns of the chip, performing the sum-average operation on the signal in each group, and determining the corresponding signal group comprises: dividing adjacent Ns samples in the sample sequence I.sub.in into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group W.sub.I; and dividing adjacent Ns samples in the sample sequence Q.sub.in into one group, successively performing the sum-average operation on Ns samples in each group, and determining the signal group W.sub.Q; wherein the grouping the signal in the signal group W.sub.I and the signal group W.sub.Q comprises: in the signal group W.sub.I, beginning from a first signal, extracting a signal after Ns1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as W.sub.I1, W.sub.I2, . . . W.sub.INs; and in the signal group W.sub.Q, beginning from a first signal, extracting a signal after Ns1 signals, successively combining each extracted signal into one group; beginning from a second signal, extracting a signal after Ns1 signals, successively combining each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as W.sub.Q1, W.sub.Q2, . . . W.sub.QNs.

2. The method according to claim 1, wherein the determining, through the matched filter, the signal belonging to the same chip in the sample sequence which experiences the sum-average operation and outputting the determined signal comprises: sending the W.sub.I1, W.sub.I2, . . . W.sub.INs into the matched filter meeting a pre-set condition, obtaining a corresponding output result, and marking the output results separately as y.sub.I1, y.sub.I2, . . . y.sub.Ins; sending the W.sub.Q1, W.sub.Q2, . . . W.sub.QNs into the matched filter, obtaining a corresponding output result, and marking the output results separately as y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; determining signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results y.sub.I1, y.sub.I2, . . . y.sub.Ins and the output results y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; and determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal.

3. The method according to claim 2, wherein the determining signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results y.sub.I1, y.sub.I2, . . . y.sub.Ins and the output results y.sub.Q1, y.sub.Q2, . . . y.sub.QNs, determining the signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal comprises: determining the signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns according to a following formula: y.sub.1={square root over (Y.sub.I1.sup.2+Y.sub.Q1.sup.2)}, y.sub.2={square root over (Y.sub.I2.sup.2+Y.sub.Q2.sup.2)}, . . . y.sub.Ns={square root over (Y.sub.INs.sup.2+Y.sub.QNs.sup.2)}; and taking a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and outputting the signal corresponding to the maximum signal amplitude value.

4. A device for reducing a bit error rate in a Code Division Multiple Access (CDMA) communication system, comprising: a memory storing programming instructions; and a processor configured to be capable of executing the stored programming instructions to: obtain a sample sequence I.sub.in of an in-phase component signal I, and a sample sequence Q.sub.in of a quadrature component signal Q, which are sent by a signal sending end; divide the obtained sample sequence I.sub.in and the sample sequence Q.sub.in into different groups according to a sample number Ns of a chip, perform a sum-average operation on a signal in each group, and determine a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence I.sub.in is W.sub.I, the signal group determined by performing the sum-average operation on the sample sequence Q.sub.in is W.sub.Q; and group a signal in the signal group W.sub.I and the signal group W.sub.Q, to determine a signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group W.sub.I and the signal group W.sub.Q, and output the determined signal; wherein the processor is further configured to be capable of executing the stored programming instructions to: divide adjacent Ns samples in the sample sequence I.sub.in into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group W.sub.I; and divide adjacent Ns samples in the sample sequence Q.sub.in into one group, successively perform the sum-average operation on Ns samples in each group, and determine the signal group W.sub.Q; wherein the processor is further configured to be capable of executing the stored programming instructions to: in the signal group W.sub.I, begin from a first signal, extract a signal after Ns1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as W.sub.I1, W.sub.I2, . . . W.sub.INs; and in the signal group W.sub.Q, begin from a first signal, extract a signal after Ns1 signals, successively combine each extracted signal into one group; begin from a second signal, extract a signal after Ns1 signals, successively combine each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as W.sub.Q1, W.sub.Q2, . . . W.sub.QNs.

5. The device according to claim 4, wherein the processor is further configured to be capable of executing the stored programming instructions to: sending the W.sub.I1, W.sub.I2, . . . W.sub.INs into the matched filter meeting a pre-set condition, obtain a corresponding output result, and mark the output results separately as y.sub.I1, y.sub.I2, . . . y.sub.INs; sending the W.sub.Q1, W.sub.Q2, . . . W.sub.QNs into the matched filter, obtain a corresponding output result, and mark the output results separately as y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; determine signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results y.sub.I1, y.sub.I2, . . . y.sub.Ins and the output results y.sub.Q1, y.sub.Q2, . . . y.sub.QNs, and determine the signal belonging to the same chip, according to the determined signal amplitude value, and output the determined signal.

6. The device according to claim 5, wherein the processor is further configured to be capable of executing the stored programming instructions to: determining the signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns according to a following formula: y.sub.1={square root over (Y.sub.I1.sup.2+Y.sub.Q1.sup.2)}, y.sub.2={square root over (Y.sub.I2.sup.2+Y.sub.Q2.sup.2)}, . . . y.sub.Ns={square root over (Y.sub.INs.sup.2+Y.sub.QNs.sup.2)}; and take a signal corresponding to a maximum signal amplitude value as the signal belonging to the same chip, and output the signal corresponding to the maximum signal amplitude value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram of a sampling way in a CDMA communication system;

(2) FIG. 2 is a diagram of a wrong sampling situation occurred in a CDMA communication system;

(3) FIG. 3 is a preferred flowchart of a method for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;

(4) FIG. 4 is a diagram of a sample sequence in a method for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;

(5) FIG. 5 is a preferred structure diagram of a device for reducing a bit error rate in a CDMA communication system in an embodiment of the disclosure;

(6) FIG. 6 is another preferred structure diagram of the device for reducing the bit error rate in the CDMA communication system in an embodiment of the disclosure;

(7) FIG. 7 is another preferred structure diagram of the device for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure;

(8) FIG. 8 is a hardware logic diagram of the method for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure;

(9) FIG. 9 is a flowchart of grouping through software in the method for reducing the bit error rate in the CDMA communication system in an embodiment of the disclosure; and

(10) FIG. 10 is a logic diagram of determining a maximum amplitude value in the method for reducing the core error rate in the CDMA communication system in an embodiment of the disclosure.

DETAILED DESCRIPTION

(11) In order to solve a problem in the related art that a CDMA synchronization algorithm possesses a wrong sampling situation, which results in a high bit error rate of a receiving end, an embodiment of the disclosure provides a method and a device for reducing a bit error rate in a CDMA communication system, and the disclosure will be explained in detail below with reference to the drawings and in combination with embodiments. It shall be explained that, the embodiment in the application and a feature in the embodiment may be combined with each other without conflict.

Embodiment 1

(12) The preferred embodiment of the disclosure provides a method for reducing the core error rate in the CDMA communication system, and FIG. 3 shows a preferred flowchart of this method, as shown in FIG. 3, this method includes the following steps:

(13) S302, obtaining a sample sequence I.sub.in of an in-phase component signal I, and a sample sequence Q.sub.in of a quadrature component signal Q, which are sent by a signal sending end;

(14) S304, dividing the obtained sample sequence I.sub.in and the sample sequence Q.sub.in into different groups according to a sample number Ns of a chip, performing a sum-average operation on a signal in each group, and determining a corresponding signal group, wherein each signal group contains the signal experiencing the sum-average operation, the signal group determined by performing the sum-average operation on the sample sequence I.sub.in is W.sub.I, the signal group determined by performing the sum-average operation on the sample sequence Q.sub.in is W.sub.Q; and

(15) S306, grouping a signal in the signal group W.sub.I and the signal group W.sub.Q, to determine the signal belonging to the same chip in the sample sequence which experiences the sum-average operation, in the signal group W.sub.I and the signal group W.sub.Q, and outputting the determined signal.

(16) In the above preferred embodiment, after performing the sum-average operation on a signal sample sequence, the signal is grouped; in the grouped signal, the sample sequence experiencing the sum-average operation from the same chip is selected, and the signal of the sample sequence from the same chip is output; this signal processing way solves the problem in the related art that the CDMA synchronization algorithm possesses the wrong sampling situation, which results in the high bit error rate of the receiving end, and effectively reduces the bit error rate.

(17) In a preferred embodiment of the disclosure, a scheme is further provided, which groups and performs sum-average on the sample sequence I.sub.in and the sample sequence Q.sub.in, and specifically, this scheme includes the following steps: dividing adjacent Ns samples in the sample sequence I.sub.in into one group, and successively performing the sum-average operation on Ns samples in each group, and determining the signal group W.sub.I; and dividing adjacent Ns samples in the sample sequence Q.sub.in into one group, and successively performing the sum-average operation on Ns samples in each group, and determining the signal group W.sub.Q. For example, it is assumed that a sample number of each chip is Ns=2, and the sample sequence I.sub.in is shown in FIG. 4, which successively contains the following samples: X1 X2, X3, X4, X5, X6, X7, X8, then 2 adjacent sample signals in the sample sequence are obtained, and experience the sum-average operation, to obtain the signal group W.sub.I, which successively includes

(18) $\frac{x1+x2}{2},\frac{x2+x3}{2},\frac{x3+x4}{2},\frac{x4+x5}{2},\frac{x5+x6}{2},\frac{x6+x7}{2},\frac{x7+x8}{2}.$
Grouping the sample sequence Q.sub.in is the same as grouping the sample sequence I.sub.in, and will not be repeated again.

(19) In the above preferred technical scheme, grouping and sum-average are performed on all adjacent Ns samples in the sample sequence I.sub.in and the sample sequence Q.sub.in, to guarantee that the signal experiencing the sum-average operation not only contains an ideal sampling situation, but also contains the wrong sampling situation, and to reduce the core error rate by selecting the signal in the ideal sampling situation.

(20) In a preferred embodiment of the disclosure, a scheme is further provided, which groups the signal group W.sub.I and the signal group W.sub.Q, specifically, this scheme includes the following steps:

(21) in the signal group W.sub.I, beginning from a first signal, extracting a signal after Ns1 signals, successively grouping each extracted signal into one group; beginning from a second signal, extracting a signal after Ns1 signals, successively grouping each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as W.sub.I1, W.sub.I2, . . . , W.sub.INs; and

(22) in the signal group W.sub.Q, beginning from a first signal, extracting a signal after Ns1 signals, successively grouping each extracted signal into one group; beginning from a second signal, extracting a signal after Ns1 signals, successively grouping each extracted signal into one group, and so on, obtaining Ns groups of signals, which are successively marked as W.sub.Q1, W.sub.Q2, . . . W.sub.QNs.

(23) The example provided above is further explained, specifically, the above signal group W.sub.I is

(24) $\frac{x1+x2}{2},\frac{x2+x3}{2},\frac{x3+x4}{2},\frac{x4+x5}{2},\frac{x5+x6}{2},\frac{x6+x7}{2},\frac{x7+x8}{2},$
when performing grouping, beginning from the first signal, signal extraction is perform after 1 signal, therefore

(25) $\frac{x1+x2}{2},\frac{x3+x4}{2},\frac{x5+x6}{2}\mathrm{and}\frac{x7+x8}{2}$
are extracted successively, and are taken as the first group,

(26) $\frac{x2+x3}{2},\frac{x4+x5}{2},\mathrm{and}\frac{x6+x7}{2}$
are taken as the second group; it can be seen from FIG. 4, the group of data

(27) $\frac{x1+x2}{2},\frac{x3+x4}{2},\frac{x5+x6}{2}\mathrm{and}\frac{x7+x8}{2}$
do not come from the same chip, but come from adjacent chips, this is the wrong sampling situation; the group of data

(28) $\frac{x2+x3}{2},\frac{x4+x5}{2},\mathrm{and}\frac{x6+x7}{2}$
come from the same chip, this is the ideal sampling situation.

(29) In a preferred embodiment of the disclosure, a scheme is further provided, which determines signal belonging to the same chip in the sample sequence experiencing the sum-average operation, and outputs the determined signal; the scheme includes the following steps: sending W.sub.I1, W.sub.I2, . . . W.sub.INs into a matched filter meeting a pre-set condition, obtaining a corresponding output result, and marking the output results separately as y.sub.I1, y.sub.I2, . . . y.sub.Ins; sending W.sub.Q1, W.sub.Q2, . . . W.sub.QNs into the matched filter, obtaining the corresponding output result, and marking the output results separately as y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; determining signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results y.sub.I1, y.sub.I2, . . . y.sub.Ins and the output results y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; and determining a signal belonging to the same chip, according to the determined signal amplitude value, and outputting the determined signal.

(30) Specifically, the signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns are determined according to the following formula: y.sub.1={square root over (Y.sub.I1.sup.2+Y.sub.Q1.sup.2)}, y.sub.2={square root over (Y.sub.I2.sup.2+Y.sub.Q2.sup.2)}, . . . y.sub.Ns={square root over (Y.sub.INs.sup.2+Y.sub.QNs.sup.2)}; the corresponding signal when the signal amplitude value is maximum is taken as the signal belonging to the same chip, and the corresponding signal when the signal amplitude value is maximum is output.

Embodiment 2

(31) Based on the above method for reducing the bit error rate in the CDMA communication system provided by Embodiment 1, this preferred embodiment provides a device for reducing the bit error rate in the CDMA communication system; FIG. 5 is a preferred structure diagram of this device, as shown in FIG. 5, this device includes: an obtaining unit 502, configured to obtain a sample sequence I.sub.in of an in-phase component signal I, and a sample sequence Q.sub.in of a quadrature component signal Q, which are sent by a signal sending end; a sum-average unit 504, configured to divide the obtained sample sequence I.sub.in and the sample sequence Q.sub.in into different groups according to a sample number Ns of a chip, perform a sum-average operation on a signal in each group, and determine a corresponding signal group, wherein each signal group contains the signal experiencing the sum average operation, the signal group determined by performing the sum-average operation on the sample sequence I.sub.in is W.sub.I, the signal group determined by performing the sum-average operation on the sample sequence Q.sub.in is W.sub.Q; and a grouping unit 506, configured to group the signal in the signal group W.sub.I and the signal group W.sub.Q, to determine the signal belonging to the same chip in the sample sequence experiencing the sum-average operation, in the signal group W.sub.I and the signal group W.sub.Q, and output the determined signal.

(32) In the above preferred embodiment, after performing the sum-average operation on the signal sample sequence, the signal is grouped, in the grouped signal, the sample sequence experiencing the sum-average operation from the same chip is selected, and the signal of the sample sequence from the same chip is output; this kind of signal processing way solves the problem in the related art that the CDMA synchronization algorithm possesses the wrong sampling situation, which results in the high bit error rate of the receiving end, and effectively reduces the core error rate.

(33) In a preferred embodiment of the disclosure, the above device is further optimized, specifically, a scheme is provided which performs grouping and sum-average on the sample sequence I.sub.in and the sample sequence Q.sub.in, as shown in FIG. 6, the sum-average unit 504 includes: a first grouping sub-unit 602, configured to divide adjacent Ns samples in the sample sequence I.sub.in into one group, and successively perform the sum-average operation on Ns samples in each group, and determine the signal group W.sub.I; and a second grouping sub-unit 604, configured to divide adjacent Ns samples in the sample sequence Q.sub.in into one group, and successively perform the sum-average operation on Ns samples in each group, and determine the signal group W.sub.Q. For example, it is assumed that the sample number of each chip is Ns=2, and the sample sequence I.sub.in is shown in FIG. 4, which contains the following samples: X1, X2, X3, X4, X5, X6, X7, X8, then adjacent 2 sample signals in the sample sequence are obtained and experience the sum-average operation, to obtain the signal group W.sub.I, which successively includes

(34) $\frac{x1+x2}{2},\frac{x2+x3}{2},\frac{x3+x4}{2},\frac{x4+x5}{2},\frac{x5+x6}{2},\frac{x6+x7}{2},\frac{x7+x8}{2}.$
Grouping the sample sequence Q.sub.in is the same as grouping the sample sequence I.sub.in, and will not be repeated again.

(35) In the above preferred technical scheme, grouping and sum-average are performed on all adjacent Ns samples in the sample sequence I.sub.in and the sample sequence Q.sub.in, to guarantee that the signal experiencing the sum-average operation not only contains an ideal sampling situation, but also contains the wrong sampling situation, and to reduce the core error rate by selecting the signal in the ideal sampling situation.

(36) In a preferred embodiment of the disclosure, the above device is further optimized, specifically, a scheme is provided which groups the signal group W.sub.I and the signal group W.sub.Q, as shown in FIG. 7, the grouping unit 506 includes:

(37) a third grouping sub-unit 702, configured to, in the signal group W.sub.I, begin from a first signal, extract a signal after Ns1 signals, successively group each extracted signal into one group; begin from a second signal, extract a signal after Ns1 signals, successively group each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as W.sub.I1, W.sub.I2, . . . , W.sub.INs; and

(38) a forth grouping sub-unit 704, configured to, in the signal group W.sub.Q, begin from a first signal, extract a signal after Ns1 signals, successively group each extracted signal into one group; begin from a second signal, extract a signal after Ns1 signals, successively group each extracted signal into one group, and so on, obtain Ns groups of signals, which are successively marked as W.sub.Q1, W.sub.Q2, . . . W.sub.QNs.

(39) The example provided above is further explained, specifically, the above signal group W.sub.I is

(40) $\frac{x1+x2}{2},\frac{x2+x3}{2},\frac{x3+x4}{2},\frac{x4+x5}{2},\frac{x5+x6}{2},\frac{x6+x7}{2},\frac{x7+x8}{2},$
when performing grouping, beginning from the first signal, signal extraction is perform after 1 signal, therefore

(41) $\frac{x1+x2}{2},\frac{x3+x4}{2},\frac{x5+x6}{2}\mathrm{and}\frac{x7+x8}{2}$
are extracted successively, and are taken as the first group,

(42) 0$\frac{x2+x3}{2},\frac{x4+x5}{2},\mathrm{and}\frac{x6+x7}{2}$
are taken as the second group; it can be seen from the drawing, the group of data

(43) $\frac{x1+x2}{2},\frac{x3+x4}{2},\frac{x5+x6}{2}\mathrm{and}\frac{x7+x8}{2}$
do not come from the same chip, but come from adjacent chips, this is the wrong sampling situation; the group of data

(44) $\frac{x2+x3}{2},\frac{x4+x5}{2},\mathrm{and}\frac{x6+x7}{2}$
come from the same chip, this is the ideal sampling situation.

(45) Preferably, as shown in FIG. 7, the grouping unit 506 further includes: a first output sub-unit 706, configured to send the W.sub.I1, W.sub.I2, . . . W.sub.INs into a matched filter meeting a pre-set condition, obtain a corresponding output result, and mark the output results separately as y.sub.I1, y.sub.I2, . . . y.sub.Ins; a second output sub-unit 708, configured to send the W.sub.Q1, W.sub.Q2, . . . W.sub.QNs into the matched filter, obtain the corresponding output result, and mark the output results separately as y.sub.Q1, y.sub.Q2, . . . y.sub.QNs; an amplitude value output sub-unit 710, configured to determine signal amplitude values y.sub.1, y.sub.2, . . . y.sub.Ns grouped by the in-phase component signal I and the quadrature component signal Q, according to the output results y.sub.I1, y.sub.I2, . . . y.sub.Ins and the output results y.sub.Q1, y.sub.Q2, . . . y.sub.QNs, and a signal output sub-unit 712, configured to determine the signal belonging to the same chip, according to the determined signal amplitude value, and output the determined signal.

(46) Specifically, the amplitude value output sub-unit 710 includes: an amplitude value calculating module, configured to determine the signal amplitudes y.sub.1, y.sub.2, . . . y.sub.Ns according to the following formula:
y.sub.1={square root over (Y.sub.I1.sup.2+Y.sub.Q1.sup.2)},y.sub.2={square root over (Y.sub.I2.sup.2+Y.sub.Q2.sup.2)}, . . . y.sub.Ns={square root over (Y.sub.INs.sup.2+Y.sub.QNs.sup.2)};

(47) the signal output sub-unit 712 includes: a signal output module, configured to take the corresponding signal when the signal amplitude value is maximum as the signal belonging to the same chip, and output the corresponding signal when the signal amplitude value is maximum.

Embodiment 3

(48) Based on the method for reducing the bit error rate in the CDMA communication system provided by Embodiment 1 and the device for reducing the bit error rate in the CDMA communication system provided by Embodiment 2, this preferred embodiment provides another method for reducing the bit error rate in the CDMA communication system; FIG. 8 shows a hardware implementation logic diagram of this method, in FIG. 8, Tc is a chip delay time (chip period), and Ns is a sample number of the chip. In implementation of this method, mainly several groups of delayers and the matched filter group MF are separately added behind two channels of input signals I.sub.in and Q.sub.in, behind the filter, accurate synchronization of data is implemented through a maximum amplitude value selector, to eliminate a serious inter-code interference caused by wrong sampling, and to reduce a high bit error rate brought by an inter-code interference of a traditional method.

(49) Specifically, the above method includes the following steps:

(50) 1. performing sum-average on the sample sequence;

(51) as shown in FIG. 8, the input signals I.sub.in and Q.sub.in are a group of sample sequence, a sampling frequency is Ns times/one chip (one chip samples Ns times). Every adjacent Ns sample values are added and divided by Ns, to obtain W.sub.I and W.sub.Q, a purpose of this step is to store the results after performing sum-average in all sampling ways (ideal sampling, wrong sampling) into two channels of signals W.sub.I and W.sub.Q. Preferably, in order to make calculation convenient and reduce a hardware resource cost, Ns is set as powers of 2.

(52) 2. grouping two channels of signals W.sub.I and W.sub.Q;

(53) the purpose of grouping two channels of signals W.sub.I and W.sub.Q is to find a most ideal sample, and eliminate an inter-chip interference caused by wrong sampling, specifically, as shown in FIG. 8, in two channels of signals W.sub.I and W.sub.Q, elements separated by Ns1 (Ns is a sampling number of the chip) elements are separately grouped into one group. Specifically, W.sub.I is a signal group obtained by performing Step 1 on I channels of signals, and includes multiple signals, which are marked as W.sub.I=(W.sub.I(0), W.sub.I(1), WI(2), . . . , W.sub.I(Ns), W.sub.I(Ns+1), W.sub.I(Ns+2), . . . , W.sub.I(2*Ns), W.sub.I(2*Ns+1), W.sub.I(2*Ns+2), . . . ), that is, W.sub.I is composed of W.sub.I(i). In the same way, W.sub.Q and W.sub.I have the same structure feature, and W.sub.Q is composed of W.sub.Q(i). W.sub.I is grouped into Ns groups with a distance of Ns1 elements, w.sub.I1=(W.sub.I(0), W.sub.I(Ns), W.sub.I(2*Ns), W.sub.I(3*Ns), . . . ), w.sub.I2=(W.sub.I(1), W.sub.I(Ns+1), W.sub.I(2*Ns+1), W.sub.I(3*Ns+1), . . . ), wI3=(W.sub.I(2), W.sub.I(Ns+2), W.sub.I(2*Ns+2), W.sub.I(3*Ns+2), . . . ), . . . , w.sub.INs=(W.sub.I(Ns1), W.sub.I(Ns+Ns1), W.sub.I(2*Ns+Ns1), W.sub.I(3*Ns+Ns1), . . . ), and a grouping relationship of W.sub.Q is the same as that of W.sub.I, and will not be repeated again.

(54) In FIG. 8 adopts a delayer to implement grouping. Tc represents a chip delay time (a chip transmission rate is 1/Tc), MF in the drawing is the matched filter, and a work clock frequency is 1/Tc. A simple delayer is added between the traditional matched filter and a Front End Processor (FEP) output, and the signals are divided into Ns groups through driving of a sample clock (a sample clock frequency is Ns/Tc). Through improvement of this method, all grouped W.sub.Ii and W.sub.Qi are sent to a matched filter group, in which one group of data must come from the same chip, the amplitude value matched and output in this way will be larger than that obtained in a traditional method, and an interference resistance ability of a system is improved.

(55) In addition, a grouping way may also be implemented through software programming, a specific algorithm flowchart is shown in FIG. 9, during grouping, first a variable flag (called a variable f for short) is defined, of which an initial value is 0, and then W.sub.I and W.sub.Q output by the sum-average unit are read through driving of each sample clock, simultaneously a modulo of the sample number Ns is calculated with the variable flag, namely flag=flag % Ns; assigning the sample value of the current W.sub.I and W.sub.Q to corresponding groups W.sub.Ij and W.sub.Qj, is decided according to a value of the variable flag (0, 1, . . . Ns2, Ns1), and simultaneously flag is added by 1, and a next signal in W.sub.I and W.sub.Q is obtained continuously to perform grouping, until grouping is completed, and finally W.sub.I and W.sub.Q are separately divided into Ns groups of signals.

(56) 3. calculating the maximum amplitude value;

(57) the grouped signals W.sub.Ij and W.sub.Qj are separately sent into the matched filter MF, as shown in FIG. 10. Matched outputs y.sub.Ij and y.sub.Qj are obtained. y.sub.Ij and y.sub.Qj are sent to an amplitude generator MAG, the amplitude generator MAG calculates a root of a quadratic sum of y.sub.Ij and y.sub.Qj to obtain the amplitude value y.sub.j. In step 2, W.sub.I and W.sub.Q are divided into Ns groups, then there are totally Ns amplitude values output here. All output amplitude values are sent to the maximum amplitude selector MAX, and the maximum amplitude selector MAX selects a maximum value from y.sub.1 to y.sub.Ns as the current output y. Simultaneously y.sub.Ij and y.sub.Qj constructing this maximum amplitude value are separately assigned to I.sub.sum shown in FIG. 8 and Q.sub.sum shown in FIG. 8.

(58) 4. judgment and demodulation;

(59) when the output y is larger than a threshold, the sign shown in FIG. 8 changes from a high electrical level to a low electrical level, otherwise the sign is the low electrical level. When the sign changes from the low electrical level to the high electrical level, a demodulator reads I.sub.sum and Q.sub.sum to perform a code demodulation operation.

(60) Through the above several steps, a group of sample values may be found which are all weighted signal values in the same chip; a serious inter-chip interference existed in a traditional rough synchronization algorithm is eliminated, and the bit error rate is reduced to a big extent. Accurate CDMA synchronization is implemented.

(61) Although for the purpose of making an example, the preferred embodiment of the disclosure is disclosed, those skilled in the art will be conscious of a possibility of improvement, increase, and substitution. Therefore, the scope of the disclosure shall not be limited to the above embodiment.