BIPOLAR JUNCTION TRANSISTORS WITH A NANOSHEET INTRINSIC BASE

Abstract

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

Claims

1. A structure for a bipolar junction transistor, the structure comprising: a collector including a first semiconductor layer; an emitter including a second semiconductor layer; an intrinsic base including a plurality of nanosheet channel layers positioned with a spaced arrangement in a layer stack, each nanosheet channel layer extending laterally from the first semiconductor layer to the second semiconductor layer; a base contact laterally positioned between the first semiconductor layer and the second semiconductor layer, the base contact including a plurality of sections that are respectively positioned in spaces between the nanosheet channel layers; a first plurality of spacers laterally positioned between the sections of the base contact and the first semiconductor layer; and a second plurality of spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

2. The structure of claim 1 further comprising: a plurality of heavily-doped semiconductor layers respectively positioned between the nanosheet channel layers and the sections of the base contact.

3. The structure of claim 2 wherein each heavily-doped semiconductor layer fully wraps about a central portion of one of the nanosheet channel layers.

4. The structure of claim 3 wherein each nanosheet channel layer includes a first end portion abutted with the first semiconductor layer and a second end portion abutted with the second semiconductor layer, and the central portion is laterally arranged between the first end portion and the second end portion.

5. The structure of claim 2 wherein each heavily-doped semiconductor layer is in direct contact with one of the nanosheet channel layers.

6. The structure of claim 2 wherein the nanosheet channel layers comprise silicon-germanium, and the heavily-doped semiconductor layers comprise silicon.

7. The structure of claim 2 wherein the first plurality of spacers are laterally arranged between the heavily-doped semiconductor layers and the first semiconductor layer, and the second plurality of spacers are laterally arranged between the heavily-doped semiconductor layers and the second semiconductor layer.

8. The structure of claim 1 wherein each nanosheet channel layer includes a central portion, a first end portion abutted with the first semiconductor layer, and a second end portion abutted with the second semiconductor layer, the central portion is laterally arranged between the first end portion and the second end portion, and one of the sections of the base contact is positioned in each space adjacent to the central portion of one of the nanosheet channel layers.

9. The structure of claim 1 wherein the base contact comprises a metal.

10. The structure of claim 1 wherein the base contact comprises tungsten.

11. The structure of claim 10 wherein the nanosheet channel layers comprise silicon-germanium.

12. The structure of claim 1 wherein the first plurality of spacers and the second plurality of spacers comprise a dielectric material that is an electrical insulator.

13. The structure of claim 1 wherein the base contact extends in a vertical direction above the nanosheet channel layers in the layer stack.

14. The structure of claim 13 wherein the base contact comprises a metal.

15. A method of fabricating a structure for a bipolar junction transistor, the method comprising: forming a collector including a first semiconductor layer; forming an emitter including a second semiconductor layer; forming an intrinsic base including a plurality of nanosheet channel layers positioned with a spaced arrangement in a layer stack, wherein each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer; forming a base contact laterally positioned between the first semiconductor layer and the second semiconductor layer, wherein the base contact includes a plurality of sections that are respectively positioned in spaces between the nanosheet channel layers; forming a first plurality of spacers laterally positioned between the sections of the base contact and the first semiconductor layer; and forming a second plurality of spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

16. The method of claim 15 further comprising: forming a plurality of heavily-doped semiconductor layers respectively positioned between the nanosheet channel layers and the sections of the base contact.

17. The method of claim 16 wherein each heavily-doped semiconductor layer fully wraps about a central portion of one of the nanosheet channel layers, each nanosheet channel layer includes a first end portion abutted with the first semiconductor layer and a second end portion abutted with the second semiconductor layer, and the central portion is laterally arranged between the first end portion and the second end portion.

18. The method of claim 16 wherein the first plurality of spacers are laterally arranged between the heavily-doped semiconductor layers and the first semiconductor layer, and the second plurality of spacers are laterally arranged between the heavily-doped semiconductor layers and the second semiconductor layer.

19. The method of claim 16 wherein each heavily-doped semiconductor layer is in direct contact with one of the nanosheet channel layers, the nanosheet channel layers comprise silicon-germanium, and the heavily-doped semiconductor layers comprise silicon.

20. The method of claim 15 wherein the base contact extends in a vertical direction above the nanosheet channel layers in the layer stack, and the base contact comprises a metal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.

[0009] FIG. 1 is a cross-sectional view of a structure for a lateral bipolar transistor at an initial fabrication stage of a fabrication method in accordance with embodiments of the invention.

[0010] FIG. 2 is a top view of the structure at a fabrication stage subsequent to FIG. 1.

[0011] FIG. 3 is a cross-sectional view taken generally along line 3-3 in FIG. 2.

[0012] FIG. 4 is a top view of the structure at a fabrication stage subsequent to FIG. 2.

[0013] FIG. 5 is a cross-sectional view taken generally along line 5-5 in FIG. 4.

[0014] FIGS. 6-13 are cross-sectional views of the structure at successive fabrication stages subsequent to FIGS. 4, 5.

[0015] FIG. 14 is a cross-sectional view of a structure in accordance with embodiments of the invention.

[0016] FIG. 15 is a cross-sectional view of a structure in accordance with embodiments of the invention.

DETAILED DESCRIPTION

[0017] With reference to FIG. 1 and in accordance with embodiments of the invention, semiconductor layers 10 and semiconductor layers 12 are formed in an alternating sequence as a layer stack on a dielectric layer 15 and a substrate 14. The semiconductor layers 12 may be comprised of a semiconductor material, such as silicon-germanium (SiGe). In an embodiment, the semiconductor layers 12 may be comprised of silicon-germanium with a germanium content of twenty-five percent (25%) to thirty-five percent (35%). The semiconductor layers 10 may be comprised of a semiconductor material, such as silicon, that is chosen to be removable selective to the semiconductor material of the semiconductor layers 12. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. To generate the layer stack, the semiconductor layers 10, 12 may be sequentially formed by an epitaxial growth process with the composition varied during growth to provide the alternating sequence. In an embodiment, the semiconductor layers 12 may contain a p-type dopant (e.g., boron) to provide p-type conductivity. In an alternative embodiment, the semiconductor layers 12 may contain an n-type dopant (e.g., arsenic or phosphorus) to provide n-type conductivity. The number of pairs of the semiconductor layers 10, 12 in the layer stack may differ from the number of pairs depicted in the representative embodiment.

[0018] The semiconductor layers 12 may subsequently provide nanosheet channel layers in a completed device structure for a bipolar junction transistor. In an embodiment, the thickness of each semiconductor layer 12 may range from about 3 nanometers (nm) to about 30 nm. In an embodiment, the thickness of each semiconductor layer 12 may range from about 5 nm to about 20 nm. In an embodiment, the semiconductor layers 12 may have equal thicknesses. In an embodiment, the semiconductor layers 10 may have equal thicknesses.

[0019] With reference to FIGS. 2, 3 in which like reference numerals refer to like features in FIG. 1 and at a subsequent fabrication stage, fins 16 are formed by patterning the semiconductor layers 10, 12 of the layer stack with lithography and etching processes. Sacrificial structures 20 are formed that extend longitudinally across the fins 16. The sacrificial structures 20 may be comprised of a polycrystalline semiconductor material, such as polycrystalline silicon (i.e., polysilicon), that is deposited by, for example, chemical vapor deposition and patterned, for example, with reactive ion etching. Each sacrificial structure 20 is covered by a dielectric cap 22 that may be associated with the patterning.

[0020] With reference to FIGS. 4, 5 in which like reference numerals refer to like features in FIGS. 2, 3 and at a subsequent fabrication stage, spacers 21 are formed on the sidewalls of each sacrificial structure 20. The fins 16 are then patterned by etching by a self-aligned process using the sacrificial structures 20 and spacers 21 as an etch mask to define bodies 26 where overlapped by the sacrificial structures 20 and spacers 21. Each body 26 includes patterned semiconductor layers 10 and semiconductor layers 12 that alternate in a vertical direction to provide a stacked arrangement.

[0021] With reference to FIG. 6 in which like reference numerals refer to like features in FIGS. 4, 5 and at a subsequent fabrication stage, the semiconductor layers 10 are laterally recessed relative to the semiconductor layers 12 with a dry or wet isotropic etching process that etches the semiconductor material constituting the semiconductor layers 10 selective to the semiconductor material constituting the semiconductor layers 12. The lateral recessing of the semiconductor layers 10 generates indents in the sidewalls of the bodies 26 because the semiconductor layers 12 are not laterally recessed due to the etch selectivity of the isotropic etching process. The device base width (Wb) may be self-defined by the length Lg of the semiconductor layers 10 after being laterally recessed.

[0022] With reference to FIG. 7 in which like reference numerals refer to like features in FIG. 6 and at a subsequent fabrication stage, inner spacers 27 are formed in the indents adjacent to the recessed opposite end portions of the semiconductor layers 10. The inner spacers 27 may be comprised of a dielectric material, such as silicon nitride, that is an electrical insulator. The inner spacers 27 may be formed by depositing a conformal layer of the dielectric material that fills the indents in the sidewalls of the bodies 26 by pinch-off, followed by performing an anisotropic etching process that removes portions of the conformal layer deposited outside of the indents.

[0023] With reference to FIG. 8 in which like reference numerals refer to like features in FIG. 7 and at a subsequent fabrication stage, portions of the dielectric layer 15 are removed by, for example, a pre-clean (e.g., a wet etch using dilute hydrofluoric acid or a dry etch) to expose surfaces of the substrate 14 in the spaces between the bodies 26 and adjacent to the opposite sidewalls of each body 26. Semiconductor layers 28, 30 are formed on the exposed surfaces of the substrate 14. The semiconductor layers 28, 30 may contain a doped semiconductor material, such as silicon doped with an n-type dopant (e.g., phosphorus) to provide n-type conductivity. The semiconductor layers 28, 30 may be formed by an epitaxial growth process in which single-crystal semiconductor material grows (with in situ doping) from the exposed surfaces of the substrate 14.

[0024] The semiconductor layers 28, 30 provide terminals (i.e., an emitter and a collector) of a bipolar junction transistor, and the semiconductor layers 12 may collectively provide an intrinsic base of the bipolar junction transistor. The semiconductor layers 12 extend laterally from the semiconductor layer 28 to the semiconductor layer 30. Each semiconductor layer 12 may have an end portion that directly contacts, and is abutted with, the semiconductor layer 28 and an opposite end portion that directly contacts, and is abutted with, the semiconductor layer 30.

[0025] With reference to FIG. 9 in which like reference numerals refer to like features in FIG. 8 and at a subsequent fabrication stage, a dielectric layer 32 is deposited as fill material and planarized. The dielectric layer 32 may be comprised of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized by chemical mechanical polishing. The sacrificial structures 20 are removed with one or more etching processes. The removal of the sacrificial structures 20 opens access to the semiconductor layers 10 in each body 26.

[0026] The semiconductor layers 10 are then removed from each body 26 by a selective etching process. In an embodiment, the semiconductor layers 10 may be fully removed from each body 26 by a selective etching process. The removal of the semiconductor layers 10 generates spaces 24 that are arranged in a vertical direction between adjacent pairs of semiconductor layers 12 and that extend in a lateral direction across each body 26 between opposite inner spacers 27. The semiconductor layers 12, which has a spaced arrangement in the vertical direction, may collectively provide nanosheet channel layers defining the intrinsic base of a bipolar junction transistor. In an embodiment, the semiconductor layers 12 may have a uniform pitch in the vertical direction. In an embodiment, the semiconductor layers 12 may have a uniform pitch in the vertical direction, as well as a uniform thickness. The dielectric layer 32 masks and protects the semiconductor layers 28, 30 during the removal of the semiconductor layers 10.

[0027] With reference to FIG. 10 in which like reference numerals refer to like features in FIG. 9 and at a subsequent fabrication stage, a semiconductor layer 34 is formed as a coating on the exterior surface of each semiconductor layer 12. In an embodiment, the semiconductor layer 34 may directly contact the exterior surface of each semiconductor layer 12. The semiconductor layers 34 may contain heavily-doped semiconductor material, such as silicon heavily doped with a concentration of a p-type dopant (e.g., boron) to provide p-type conductivity. In an embodiment, the dopant concentration may be greater than 1×10.sup.19 cm.sup.−3. The semiconductor layers 34 may be formed by an epitaxial growth process in which single-crystal semiconductor material grows (with in situ doping) from growth seeds supplied by the semiconductor layers 12. The semiconductor layers 34 may provide a base extension (i.e., extrinsic base) for contacting the intrinsic based defined by the semiconductor layers 12.

[0028] Each semiconductor layer 34 fully wraps about a portion of each semiconductor layer 12. In an embodiment, each semiconductor layer 34 fully wraps about a central portion of each semiconductor layer 12. The inner spacers 27 are laterally positioned between the semiconductor layers 34 and the semiconductor layers 28, 30. The end portion of each semiconductor layer 12 that is abutted with the semiconductor layer 28 and the opposite end portion of each semiconductor layer 12 that is abutted with the semiconductor layer are masked by the inner spacers 27 and are not coated by the semiconductor layer 34. The coated portion (e.g., the coated central portion) of each semiconductor layer 12 is laterally positioned between the opposite end portions that are uncoated.

[0029] With reference to FIG. 12 in which like reference numerals refer to like features in FIG. 11 and at a subsequent fabrication stage, a base contact 36 comprised of a metal, such as tungsten, is formed that includes sections in the spaces 24 between the semiconductor layers 12 that were formerly occupied by the removed semiconductor layers 10. More specifically, the sections of the base contact 36 may be positioned in the spaces 24 adjacent to the central portions of the semiconductor layers 12. The inner spacers 27 are laterally positioned between the sections of the base contact 36 in the spaces 24 and the semiconductor layers 28, 30, and furnish electrical isolation.

[0030] The base contact 36 may be formed by depositing a layer of the metal and planarizing the deposited layer with, for example, chemical-mechanical polishing (CMP). The base contact 36 is coupled by the semiconductor layers 34 to the semiconductor layers 12 as a wrap-around contact. More specifically, the base contact 36 fully wraps around (i.e., surrounds) each of the semiconductor layers 12 with the semiconductor layers 34 separating the sections of the base contact 36 from the semiconductor layers 12.

[0031] With reference to FIG. 13 in which like reference numerals refer to like features in FIG. 12 and at a subsequent fabrication stage, middle-of-line (MOL) processing follows to form an interconnect structure having contacts 40 and contacts 42 that are coupled to the bipolar junction transistor. The contacts 40, which may be comprised of a trench silicide, are formed in trenches patterned in the dielectric layer 32. The contacts 42 may be comprised of a metal, such as tungsten, and may be formed in a dielectric layer 44.

[0032] The resultant structure is a lateral bipolar junction transistor that includes terminals (i.e., an emitter and a collector) defined by the semiconductor layers 28, 30 and an intrinsic base having multiple nanosheet channel layers (i.e., semiconductor layers 12) laterally connecting the emitter and collector. The nanosheet channel layers defined by the semiconductor layers 12 may satisfy large current drivability requirements. In particular, the nanosheet channel layers providing the intrinsic base may permit the current drive to be maximized within a compact footprint. For example, the number of semiconductor layers 12 in the compact footprint can be flexibly varied to satisfy a given current drive requirement. The resultant structure may be suitable for high current drive (high Beta) and high frequency (high Ft and/or high Fmax) applications. The base width (Wb) is self-defined by Lg (FIG. 6), which can be less than or equal to about 20 nm for advanced technologies and may thereby boost Ft and/or Fmax. The intrinsic base (i.e., semiconductor layers 12), the wrap-around extrinsic base (i.e., semiconductor layers 34), and the wrap-around base contact 36 may function to minimize the base resistance (Rb), which may also boost Ft and/or Fmax.

[0033] With reference to FIG. 14 in which like reference numerals refer to like features in FIG. 13 and in accordance with embodiments, the dielectric layer 15 may be retained in an intact condition before forming the semiconductor layers 28, 30, which may be epitaxially grown from growth seeds provided by the semiconductor layers 12.

[0034] With reference to FIG. 15 in which like reference numerals refer to like features in FIG. 13 and in accordance with embodiments, for normal NPN bipolar junction transistor operation, the intrinsic base (i.e., semiconductor layers 12) and emitter (e.g., semiconductor layer 28) may be forward biased relative to each other, and the intrinsic base (i.e., semiconductor layers 12) and collector (e.g., semiconductor layer 30) may be reversed biased relative to each other. Due to the biasing, electrons are collected by the collector due to electron flow through the nanosheet channel layers (i.e., the semiconductor layers 12) of the intrinsic base. The substrate 14 may include a well 48 (e.g., a P-well for an NPN bipolar junction transistor) that may be tapped to ground (or, alternatively, negatively biased) to provide electrical isolation, during operation, that cuts off the substrate channel between the emitter and collector and a portion of the substrate 14 beneath the well 48.

[0035] The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

[0036] References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).

[0037] References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.

[0038] A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features overlap if a feature extends over, and covers a part of, another feature.

[0039] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.