PRODUCING METHOD OF WIRED CIRCUIT BOARD

Abstract

Provided is a method for producing a wired circuit board in which a first preparation step of preparing a first substrate having an insulating layer and a conductive layer disposed on one surface of the insulating layer; a second preparation step of preparing a second substrate having a metal layer; a bonding step of laminating the first substrate and the second substrate so that the conductive layer and the metal layer are in contact with each other, and metal-bonding the conductive layer and the metal layer; and a patterning step of forming a conductive pattern on the other surface of the insulating layer are carried out.

Claims

1. A method for producing a wired circuit board, comprising: a first preparation step of preparing a first substrate having an insulating layer and a conductive layer disposed on one surface of the insulating layer; a second preparation step of preparing a second substrate having a metal layer; a bonding step of laminating the first substrate and the second substrate so that the conductive layer and the metal layer are in contact with each other, and metal-bonding the conductive layer and the metal layer; and a patterning step of forming a conductive pattern on the other surface of the insulating layer, wherein the patterning step is carried out after the bonding step, or the bonding step is carried out after the patterning step.

2. The method for producing a wired circuit board according to claim 1, wherein, in the bonding step, the conductive layer and the metal layer are bonded by interface bonding.

3. The method for producing a wired circuit board according to claim 2, wherein, in the bonding step, the conductive layer and the metal layer are bonded by solid phase bonding.

4. The method for producing a wired circuit board according to claim 3, wherein, in the bonding step, a first step of activating a surface of the conductive layer and a surface of the metal layer, and a second step of bonding the activated surface of the conductive layer and the activated surface of the metal layer are carried out in vacuum.

5. The method for producing a wired circuit board according to claim 1, wherein, in the first preparation step, a first roll that is a roll of the first substrate is prepared; in the second preparation step, a second roll that is a roll of the second substrate is prepared; and in the bonding step, the first substrate delivered from the first roll and the second substrate delivered from the second roll are laminated.

6. The method for producing a wired circuit board according to claim 5, wherein the patterning step is carried out after the bonding step.

7. The method for producing a wired circuit board according to claim 1, wherein the conductive layer is made of copper, and the metal layer is made of copper alloy.

8. The method for producing a wired circuit board according to claim 1, wherein the conductive pattern comprises a ground pattern electrically connected to the conductive layer; and a wiring pattern insulated from the conductive layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is a plan view showing an example of a wired circuit board.

[0029] FIG. 2 is a cross sectional view taken along line A-A in FIG. 1.

[0030] FIGS. 3A to 3F graphically illustrate a first embodiment of a method for producing a wired circuit board; FIG. 3A illustrates a step of preparing a first substrate and a second substrate (first preparation step and second preparation step), FIG. 3B illustrates a step of bonding between a conductive layer of the first substrate and a metal layer of the second substrate (bonding step), FIG. 3C illustrates a step of forming a via hole in the insulating layer, FIG. 3D illustrates a step of forming a conductive pattern (patterning step), FIG. 3E illustrates a step of forming a cover insulating layer, and FIG. 3F illustrates a step of etching the metal layer and the conductive layer (etching step).

[0031] FIG. 4 graphically illustrates details of the bonding step.

[0032] FIGS. 5A to 5F graphically illustrate a second embodiment of the method for producing a wired circuit board; FIG. 5A illustrates a step of preparing a first substrate (first preparation step), FIG. 5B illustrates a step of forming a via hole in the insulating layer, FIG. 5C illustrates a step of forming a conductive pattern (patterning step), FIG. 5D illustrates a step of forming a cover insulating layer, FIG. 5E illustrates a step of preparing a second substrate (second preparation step), and a step of bonding between the conductive layer of the first substrate and the metal layer of the second substrate (bonding step), and FIG. 5F illustrates a step of etching the metal layer and the conductive layer (etching step).

[0033] FIGS. 6A to 6D graphically illustrate a third embodiment of the method for producing a wired circuit board; FIG. 6A, subsequent to FIG. 5D, illustrates a step of etching the conductive layer (first etching step), FIG. 6B illustrates a step of preparing a second substrate (second preparation step), FIG. 6C illustrates a step of etching the metal layer (second etching step), and FIG. 6D illustrates a step of bonding between the conductive layer of the first substrate and the metal layer of the second substrate (bonding step).

DESCRIPTION OF THE EMBODIMENTS

1. Wired Circuit Board

[0034] As shown in FIG. 1, a wired circuit board 1 extends in a first direction and a second direction. In the present embodiment, the wired circuit board 1 has a generally rectangular shape. The shape of the wired circuit board 1 is not limited.

[0035] As shown in FIG. 2, the wired circuit board 1 has a base insulating layer 11, a conductive pattern 12, a plurality of conductive layers 13A, 13B, 13C, 13D, and 13E, a plurality of metal layers 14A, 14B, 14C, 14D, and 14E, and a cover insulating layer 15.

[0036] (1) Base Insulating Layer

[0037] The base insulating layer 11 is disposed between the conductive pattern 12 and the conductive layers 13A, 13B, 13C, 13D, and 13E in a thickness direction. The thickness direction is orthogonal to each of the first direction and the second direction. The base insulating layer 11 insulates wiring patterns 12A, 12B, 12C, and 12D from the conductive layers 13A, 13B, 13C, and 13D. The wiring patterns 12A, 12B, 12C, and 12D will be described later. The base insulating layer 11 is made of resin. Examples of the resin include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester. The base insulating layer 11 has one surface S1 and the other surface S2 in the thickness direction.

[0038] (2) Conductive Pattern

[0039] The conductive pattern 12 is disposed on the other surface S2 of the base insulating layer 11 in the thickness direction. The conductive pattern 12 is made of metal. Examples of the metal include copper, silver, gold, iron, aluminum, chromium, and alloys thereof. From the viewpoint of obtaining good electrical properties, copper is preferably used. The shape of the conductive pattern 12 is not limited.

[0040] As shown in FIG. 1, the conductive pattern 12 has the plurality of wiring patterns 12A, 12B, 12C, and 12D, and a ground pattern 12E.

[0041] (2-1) Wiring Pattern

[0042] The wiring pattern 12A has a terminal 121A, a terminal 122A, and a wire 123A. The wiring pattern 12A electrically connects an electronic component connected to the terminal 121A to an electronic component connected to the terminal 122A.

[0043] The terminal 121A is disposed at one end portion of the wired circuit board 1 in the first direction. The terminal 121A has a square land shape.

[0044] The terminal 122A is disposed at the other end portion of the wired circuit board 1 in the first direction. The terminal 122A has a square land shape.

[0045] One end of the wire 123A is connected to the terminal 121A. The other end of the wire 123A is connected to the terminal 122A. The wire 123A electrically connects the terminal 121A to the terminal 122A.

[0046] Each of the wiring patterns 12B, 12C, and 12D can be described in the same manner as the wiring pattern 12A. Therefore, descriptions of each of the wiring patterns 12B, 12C, and 12D are omitted.

[0047] (2-2) Ground Pattern

[0048] The ground pattern 12E has a ground terminal 121E and a ground wire 122E. The ground pattern 12E connects an electronic component connected to the ground terminal 121E to a ground with the conductive layer 13E interposed therebetween.

[0049] The ground terminal 121E is disposed at one end portion of the wired circuit board 1 in the first direction. The ground terminal 121E has a square land shape. The terminals 121A, 121B, 121C, and 121D and the ground terminal 121E are spaced apart from each other and are aligned in the second direction.

[0050] One end of the ground wire 122E is connected to the ground terminal 121E. The other end of the ground wire 122E is connected to the conductive layer 13E through a via hole 11A (ref: FIG. 2) in the base insulating layer 11.

[0051] (3) Conductive Layer

[0052] As shown in FIG. 2, the conductive layers 13A, 13B, 13C, 13D, and 13E are disposed on one surface S1 of the base insulating layer 11 in the thickness direction. The conductive layers 13A, 13B, 13C, 13D, and 13E are made of metal. Examples of the metal include copper, silver, gold, iron, aluminum, chromium, and alloys thereof. From the viewpoint of obtaining good electrical properties, copper is preferably used. The conductive layers 13A, 13B, 13C, 13D, and 13E are spaced apart from each other and are aligned in the second direction, corresponding to the wiring patterns 12A, 12B, 12C, and 12D and the ground pattern 12E.

[0053] Specifically, the conductive layer 13A is disposed on the opposite side of the wiring pattern 12A with respect to the base insulating layer 11 in the thickness direction. The conductive layer 13A extends along the wiring pattern 12A. The conductive layer 13A reduces transmission loss in the wiring pattern 12A.

[0054] The conductive layer 13B is disposed on the opposite side of the wiring pattern 12B with respect to the base insulating layer 11 in the thickness direction. The conductive layer 13B extends along the wiring pattern 12B. The conductive layer 13B reduces transmission loss in the wiring pattern 12B.

[0055] The conductive layer 13C is disposed on the opposite side of the wiring pattern 12C with respect to the base insulating layer 11 in the thickness direction. The conductive layer 13C extends along the wiring pattern 12C. The conductive layer 13C reduces transmission loss in the wiring pattern 12C.

[0056] The conductive layer 13D is disposed on the opposite side of the wiring pattern 12D with respect to the base insulating layer 11 in the thickness direction. The conductive layer 13D extends along the wiring pattern 12D. The conductive layer 13D reduces transmission loss in the wiring pattern 12D.

[0057] The conductive layer 13E is electrically connected to the ground pattern 12E. As shown in FIG. 1, the conductive layer 13E has a wire portion 131E and a terminal portion 132E. One end of the wire portion 131E is connected to the ground wire 122E. The other end of the wire portion 131E is connected to the terminal portion 132E. The terminal portion 132E is disposed at one end portion of the wired circuit board 1 in the first direction. The terminal portion 132E has a square land shape.

[0058] (4) Metal Layer

[0059] As shown in FIG. 2, the metal layers 14A, 14B, 14C, 14D, and 14E are spaced apart from each other and are aligned in the second direction, corresponding to the conductive layers 13A, 13B, 13C, 13D, and 13E. The metal layers 14A, 14B, 14C, 14D, and 14E are made of metal. Examples of the metal include stainless steel and copper alloy.

[0060] Specifically, the metal layer 14A is disposed on the opposite side of the wiring pattern 12A with respect to the conductive layer 13A in the thickness direction. The metal layer 14A is bonded to the conductive layer 13A. The metal layer 14A supports the conductive layer 13A and the wiring pattern 12A.

[0061] The metal layer 14B is disposed on the opposite side of the wiring pattern 12B with respect to the conductive layer 13B in the thickness direction. The metal layer 14B is bonded to the conductive layer 13B. The metal layer 14B supports the conductive layer 13B and the wiring pattern 12B.

[0062] The metal layer 14C is disposed on the opposite side of the wiring pattern 12C with respect to the conductive layer 13C in the thickness direction. The metal layer 14C is bonded to the conductive layer 13C. The metal layer 14C supports the conductive layer 13C and the wiring pattern 12C.

[0063] The metal layer 14D is disposed on the opposite side of the wiring pattern 12D with respect to the conductive layer 13D in the thickness direction. The metal layer 14D is bonded to the conductive layer 13D. The metal layer 14D supports the conductive layer 13D and the wiring pattern 12D.

[0064] The metal layer 14E is disposed on the opposite side of the ground pattern 12E with respect to the conductive layer 13E in the thickness direction. The metal layer 14E is bonded to the conductive layer 13E. The metal layer 14E supports the conductive layer 13E and the ground pattern 12E.

[0065] (5) Cover Insulating Layer

[0066] As shown in FIG. 1, the cover insulating layer 15 covers wires 123A, 123B, 123C, and 123D, and the ground wire 122E. The cover insulating layer 15 is disposed on the other surface S2 of the base insulating layer 11 in the thickness direction. The cover insulating layer 15 does not cover the terminals 121A, 121B, 121C, and 121D, terminals 122A, 122B, 122C, and 122D, and the ground terminal 121E. The cover insulating layer 15 is made of resin. Examples of the resin include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester.

2. Method for Producing Wired Circuit Board

[0067] Next, a first embodiment of a method for producing the wired circuit board 1 will be described.

[0068] As shown in FIGS. 3A to 3F, the method for producing the wired circuit board 1 includes a first preparation step (ref: FIG. 3A), a second preparation step (ref: FIG. 3A), a bonding step (ref: FIG. 3B), a patterning step (ref: FIG. 3D), an etching step (ref: FIG. 3F), and an outline processing step.

[0069] (1) First Preparation Step

[0070] As shown in FIG. 3A, in the first preparation step, a first substrate 21 is prepared. In the present embodiment, a first roll R1 (ref: FIG. 4) which is a roll of the first substrate 21 is prepared in the first preparation step. The first substrate 21 has an insulating layer 211 and a conductive layer 212.

[0071] The insulating layer 211 is a material for the above-mentioned base insulating layer 11. The insulating layer 211 is made of resin. Examples of the resin include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester. The insulating layer 211 has one surface S1 and the other surface S2 in the thickness direction.

[0072] The insulating layer 212 is a material for the above-mentioned conductive layers 13A, 13B, 13C, 13D, and 13E. The conductive layer 212 is disposed on one surface S1 of the insulating layer 211. The conductive layer 212 is made of metal. Examples of the metal include copper, silver, gold, iron, aluminum, chromium, and alloys thereof. From the viewpoint of obtaining good electrical properties, the conductive layer 212 is preferably made of copper. That is, the first substrate 21 is preferably a copper-clad laminate.

[0073] (2) Second Preparation Step

[0074] In the second preparation step, a second substrate 22 is prepared. In the present embodiment, a second roll R2 (ref: FIG. 4) which is a roll of the second substrate 22 is prepared in the second preparation step. The second substrate 22 has a metal layer 221. In the present embodiment, the second substrate 22 is made of the metal layer 221 only.

[0075] The metal layer 221 is a material for the above-mentioned metal layers 14A, 14B, 14C, 14D, and 14E. The metal layer 221 is made of metal. Examples of the metal include stainless steel and copper alloy. The metal layer 221 is preferably made of copper alloy.

[0076] (3) Bonding Step

[0077] Next, as shown in FIG. 3B, in the bonding step, the first substrate 21 and the second substrate 22 are laminated so that the conductive layer 212 and the metal layer 221 are in contact with each other, and the conductive layer 212 and the metal layer 221 are then metal-bonded. In the bonding step, the conductive layer 212 and the metal layer 221 are bonded by preferably, interface bonding, more preferably, solid phase bonding.

[0078] In the present embodiment, as shown in FIG. 4, the first substrate 21 delivered from the first roll R1 and the second substrate 22 delivered from the second roll R2 are laminated (roll-to-roll system) in the bonding step. Specifically, in the bonding step, a first step and a second step to be described below are carried out in vacuum.

[0079] “Vacuum” herein refers to a state in a space filled with a gas at a pressure lower than normal atmospheric pressure (JIS Z 8126-1: 1999). More specifically, “vacuum” refers to a state in a space filled with a gas at a pressure lower than standard atmospheric pressure. From the viewpoint of suppressing oxidation of the conductive layer 212 and the metal layer 221, and gas molecule adsorption to the conductive layer 212 and the metal layer 221, the higher the degree of vacuum, the more it is preferred.

[0080] The first step and the second step are carried out, for example, in high vacuum (10.sup.−1 to 10.sup.−5 Pa), preferably in ultra-high vacuum (10.sup.−5 Pa or less).

[0081] In the first step, a surface S11 of the conductive layer 212 (ref: FIG. 3A) and a surface S12 of the metal layer 221 (ref: FIG. 3A) are activated.

[0082] To activate the surface S11 of the conductive layer 212, the surface S11 of the conductive layer 212 of the first substrate 21 delivered from the first roll R1 is ion-etched by a first ion etching apparatus 31. For example, the surface S11 of the conductive layer 212 of the first substrate 21 delivered from the first roll R1 is irradiated with an argon ion beam by the first ion etching apparatus 31. This eliminates oxides and adsorbates on the surface S11 of the conductive layer 212, and the surface S11 of the conductive layer 212 is activated.

[0083] To activate the surface S12 of the metal layer 221, the surface S12 of the metal layer 221 of the second substrate 22 delivered from the second roll R2 is ion-etched by a second ion etching apparatus 32. This eliminates oxides and adsorbates on the surface S12 of the metal layer 221, and the surface S12 of the metal layer 221 is activated.

[0084] Next, in the second step, the activated surface S11 of the conductive layer 212 and the activated surface S12 of the metal layer 221 are bonded.

[0085] To be specific, the first substrate 21 and the second substrate 22 are brought together so that the activated surface S11 of the conductive layer 212 and the activated surface S12 of the metal layer 221 are in contact with each other, and then pressed by a press apparatus 33.

[0086] Then, as shown in FIG. 3B, the surface S11 of the conductive layer 212 and the surface S12 of the metal layer 221 are bonded.

[0087] Since oxides and adsorbates are eliminated from the surface S11 of the conductive layer 212 and the surface S12 of the metal layer 221 by carrying out the first step and the second step in vacuum, electrical resistance at the interface between the conductive layer 212 and the metal layer 221 can be further reduced. In addition, adhesion strength between the conductive layer 212 and the metal layer 221 can be further improved.

[0088] (4) Patterning Step

[0089] Next, in the present embodiment, the patterning step is carried out after the bonding step. This allows reliable bonding between the conductive layer 212 and the metal layer 221 without requiring the consideration of deformation or the like in the conductive pattern 12 in the bonding step, as compared with the case of carrying out the bonding step after the patterning step as in second and third embodiments to be described later. In particular, it is preferable in the case of carrying out the bonding step by the roll-to-roll system.

[0090] In the patterning step, the conductive pattern 12 is formed on the other surface S2 of the insulating layer 211.

[0091] Specifically, as shown in FIG. 3C, first, a via hole 11A is formed in the insulating layer 211 as required. In the present embodiment, the via hole 11A is formed in order to connect the ground pattern 12E (ref: FIG. 2) to the conductive layer 13E (ref: FIG. 2).

[0092] Then, in the present embodiment, as shown in FIG. 3D, the conductive pattern 12 is formed on the other surface S2 of the insulating layer 211 by electroless plating. That is, the conductive pattern 12 is formed by an additive method. The conductive pattern 12 has the ground pattern 12E that is electrically connected to the conductive layer 212, and the wiring patterns 12A, 12B, 12C, and 12D that are insulated from the conductive layer 212. The conductive pattern 12 may be formed by a subtractive method.

[0093] Then, as shown in FIG. 3E, the above-mentioned cover insulating layer 15 is formed on the other surface S2 of the insulating layer 211.

[0094] (5) Etching Step

[0095] Next, as shown in FIG. 3F, the metal layer 221 and the conductive layer 212 are etched to form the conductive layers 13A, 13B, 13C, 13D, and 13E, and the metal layers 14A, 14B, 14C, 14D, and 14E.

[0096] (6) Outline Processing Step

[0097] Next, as shown in FIG. 2, the insulating layer 211 is outline-processed into a predetermined shape, so that the above-mentioned wired circuit board 1 is obtained. An outline processing method is not limited. Examples of the outline processing method include etching and cutting.

3. Effects

[0098] (1) According to the method for producing the wired circuit board 1, as shown in FIG. 2, the wired circuit board 1 in which the conductive layers 13A, 13B, 13C, 13D, and 13E are metal-bonded to the metal layers 14A, 14B, 14C, 14D, and 14E, respectively, can be obtained.

[0099] Therefore, electrical resistance between the conductive layers 13A, 13B, 13C, 13D, and 13E and the metal layers 14A, 14B, 14C, 14D, and 14E can be reduced.

[0100] (2) According to the method for producing the wired circuit board 1, in the bonding step (ref: FIG. 3B), the conductive layer 212 and the metal layer 221 are bonded by interface bonding.

[0101] Therefore, electrical resistance between the conductive layers 13A, 13B, 13C, 13D, and 13E and the metal layers 14A, 14B, 14C, 14D, and 14E can be further reduced.

[0102] (3) According to the method for producing the wired circuit board 1, in the bonding step (ref: FIG. 3B), the conductive layer 212 and the metal layer 221 are bonded by solid phase bonding.

[0103] Therefore, electrical resistance between the conductive layers 13A, 13B, 13C, 13D, and 13E and the metal layers 14A, 14B, 14C, 14D, and 14E can be even further reduced.

[0104] (4) According to the method for producing the wired circuit board 1, as shown in FIG. 4, the first step in which the surface S11 of the conductive layer 212 is activated by the first ion etching apparatus 31 and the surface S12 of the metal layer 221 is activated by the second ion etching apparatus 32, and the second step in which the activated surface S11 of the conductive layer 212 and the activated surface S12 of the metal layer 221 are bonded by the press apparatus 33 are carried out in vacuum in the bonding step.

[0105] By performing the first step and the second step in vacuum, the surface S11 of the conductive layer 212 and the surface S12 of the metal layer 221 are activated while suppressing oxidation and gas molecule adsorption, so that these surfaces can be bonded.

[0106] As a result, electrical resistance at the interface between the conductive layer 212 and the metal layer 221 can be further reduced.

[0107] (5) According to the method for producing the wired circuit board 1, as shown in FIG. 4, the first substrate 21 delivered from the first roll R1 and the second substrate 22 delivered from the second roll R2 are laminated in the bonding step.

[0108] Therefore, the roll-to-roll system allows the conductive layer 212 and the metal layer 221 to be bonded, so that production efficiency can be improved.

[0109] (6) According to the method for producing the wired circuit board 1, as shown in FIG. 3D, the patterning step is carried out after the bonding step (ref: FIG. 3B).

[0110] Therefore, as compared with the case of carrying out the bonding step after the patterning step, the conductive layer 212 and the metal layer 221 can be reliably bonded without requiring the consideration of deformation or the like in the conductive pattern 12 in the bonding step.

[0111] (7) According to the method for producing the wired circuit board 1, as shown in FIG. 2, when the conductive layer 212 is made of copper and the metal layer 221 is made of copper alloy, electrical resistance between the conductive layers 13A, 13B, 13C, 13D, and 13E made of copper and the metal layers 14A, 14B, 14C, 14D, and 14E made of copper alloy can be reduced.

[0112] (8) According to the method for producing the wired circuit board 1, as shown in FIG. 2, electrical resistance between the conductive layer 13E to which the ground pattern 12E is connected and the metal layer 14E can be reduced.

4. Second Embodiment

[0113] Next, a second embodiment will be described. In the second embodiment, the same reference numerals are provided for the same members as those in the first embodiment, and the description thereof is omitted.

[0114] As shown in FIGS. 5A to 5F, in the second embodiment, the bonding step (ref: FIG. 5E) is carried out after the patterning step (ref: FIG. 5C).

[0115] Specifically, first, as shown in FIG. 5A, the first substrate 21 having the insulating layer 211 and the conductive layer 212 is prepared (first preparation step).

[0116] Then, the conductive pattern 12 is formed on the other surface S2 of the insulating layer 211.

[0117] Specifically, as shown in FIG. 5B, a via hole 11A is formed in the insulating layer 211 as required.

[0118] Then, as shown in FIG. 5C, the conductive pattern 12 is formed on the other surface S2 of the insulating layer 211 by an additive method or a subtractive method (patterning step).

[0119] Then, as shown in FIG. 5D, the above-mentioned cover insulating layer 15 is formed on the other surface S2 of the insulating layer 211.

[0120] Then, as shown in FIG. 5E, a second substrate 22 having a metal layer 221 is prepared (second preparation step), the first substrate 21 and the second substrate 22 are laminated so that the conductive layer 212 and the metal layer 221 are in contact with each other, and the conductive layer 212 and the metal layer 221 are bonded (bonding step).

[0121] Then, as shown in FIG. 5F, the metal layer 221 and the conductive layer 212 are etched to form conductive layers 13A, 13B, 13C, 13D, and 13E, and metal layers 14A, 14B, 14C, 14D, and 14E (etching step).

[0122] Thereafter, as shown in FIG. 2, the insulating layer 211 is outline-processed into a predetermined shape (outline processing step), so that the above-mentioned wired circuit board 1 is obtained.

[0123] The second embodiment can also achieve the same effects as those in the first embodiment.

5. Third Embodiment

[0124] Next, a third embodiment will be described. In the third embodiment, the same reference numerals are provided for the same members as those in the second embodiment, and the description thereof is omitted.

[0125] In the third embodiment, as shown in FIGS. 5A to 5D, steps including the first preparation step (ref: FIG. 5A) and the patterning step (ref: FIG. 5C) are carried out in the same manner as in the second embodiment, and as shown in FIG. 6A, the conductive layer 212 is then etched to form the above-mentioned conductive layers 13A, 13B, 13C, 13D, and 13E (first etching step).

[0126] Then, as shown in FIG. 6B, a second substrate 22 having a metal layer 221 is prepared (second preparation step), as shown in FIG. 6C, the metal layer 221 is etched to form the above-mentioned metal layers 14A, 14B, 14C, 14D, and 14E (second etching step).

[0127] Thereafter, as shown in FIG. 6D, the first substrate 21 and the second substrate 22 are laminated so that the conductive layers 13A, 13B, 13C, 13D, and 13E and the metal layers 14A, 14B, 14C, 14D, and 14E are in contact with each other, respectively, and the conductive layers 13A, 13B, 13C, 13D, and 13E are bonded to the metal layers 14A, 14B, 14C, 14D, and 14E, respectively (bonding step).

[0128] The third embodiment can also achieve the same effects as those in the first embodiment.

6. Modification

[0129] (1) In the above-mentioned embodiments, the first substrate 21 having the conductive layer 212 only on one surface S1 of the insulating layer 211 is prepared. However, the first substrate 21 may have the conductive layer 212 on each of one surface S1 and the other surface S2 of the insulating layer 211. In this case, in the patterning step, the conductive layer 212 on the other surface S2 is patterned in the conductive pattern 12 by a subtractive method.

[0130] (2) In the above-mentioned embodiments, the first substrate 21 and the second substrate 22 are bonded by the roll-to-roll system. However, a sheet of the first substrate 21 and a sheet of the second substrate 22 may be bonded.

[0131] While the illustrative embodiments of the present invention are provided in the above-described invention, such is for illustrative purpose only and it is not to be construed restrictively. Modification and variation of the present invention that will be obvious to those skilled in the art is to be covered by the following claims.

INDUSTRIAL APPLICABILITY

[0132] The method for producing a wired circuit board according to the present invention is used for production of a wired circuit board.

DESCRIPTION OF REFERENCE NUMERALS

[0133] 1 wired circuit board

[0134] 12 conductive pattern

[0135] 12A wiring pattern

[0136] 12B wiring pattern

[0137] 12C wiring pattern

[0138] 12D wiring pattern

[0139] 12E ground pattern

[0140] 21 first substrate

[0141] 22 second substrate

[0142] 211 insulating layer

[0143] 212 conductive layer

[0144] 221 metal layer

[0145] R1 first roll

[0146] R2 second roll

[0147] S1 one surface of insulating layer

[0148] S2 the other surface of insulating layer

[0149] S11 surface of conductive layer

[0150] S12 surface of metal layer