Light emitting diode (LED) using carbon materials

Abstract

Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

Claims

1. A light emitting diode (LED), comprising: a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first and second bottom gates; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED, and wherein at least one region of the carbon material is doped and another region of the carbon material is undoped, wherein at least one first region of the carbon material on top of the first bottom gate and at least one second region on top of the second bottom gate are doped; and metal source and drain contacts on top of the carbon material with the carbon material being present between the gate dielectric and the metal source and drain contacts, wherein the carbon material terminates under the metal source and drain contacts such that the metal source and drain contacts i) surround a top and sides of opposing ends of the carbon material and ii) are in direct contact with both the carbon material and the gate dielectric.

2. The LED of claim 1, wherein the substrate comprises a silicon substrate.

3. The LED of claim 1, wherein the insulator layer comprises silicon dioxide.

4. The LED of claim 1, wherein the insulator layer has a bilayer configuration.

5. The LED of claim 4, wherein the insulator layer comprises i) a nitride layer on the substrate and ii) an oxide layer on the nitride layer, and wherein the first bottom gate and the second bottom gate are present in the oxide layer.

6. The LED of claim 1, wherein the first bottom gate and the second bottom gate each comprises doped polysilicon, and wherein the first bottom gate and the second bottom gate are doped with a same dopant as one another.

7. The LED of claim 1, wherein the first bottom gate and the second bottom gate each comprises at least one metal.

8. The LED of claim 1, wherein the gate dielectric comprises hafnium oxide, aluminum oxide or silicon nitride.

9. The LED of claim 1, wherein the carbon material comprises carbon nanotubes.

10. The LED of claim 1, wherein the carbon material comprises graphene.

11. The LED of claim 1, wherein the metal source and drain contacts each comprises titanium.

12. The LED of claim 1, wherein the insulator layer comprises a single layer of silicon dioxide, and wherein the first bottom gate and the second bottom gate extend only part way through the insulator layer and a portion of the insulator layer separates the first bottom gate and the second bottom gate from the substrate.

13. The LED of claim 1, wherein the first bottom gate and the second bottom gate are spaced apart from one another by a distance of from about 50 nm to about 2,000 nm.

14. The LED of claim 1, comprising exactly two bottom gates one of which is the first bottom gate, and another of which is the second bottom gate.

15. The LED of claim 1, wherein at least one third region of the carbon material between the at least one first region and the at least one second region of the carbon material is undoped.

16. The LED of claim 15, wherein the at least one third region of the carbon material comprises an ungated region of the carbon material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional diagram illustrating a starting structure for a light emitting diode (LED) fabrication process that includes a silicon (Si) substrate and an insulator layer formed on the substrate according to an embodiment of the present invention;

(2) FIG. 1A is a cross-sectional diagram illustrating an alternative starting structure for the LED fabrication process that includes a Si substrate and a bilayer insulator layer formed on the substrate according to an embodiment of the present invention;

(3) FIG. 2 is a cross-sectional diagram illustrating trenches having been patterned in the insulator layer of FIG. 1 according to an embodiment of the present invention;

(4) FIG. 2A is a cross-sectional diagram illustrating trenches having been patterned in the bilayer insulator layer of FIG. 1A according to an embodiment of the present invention;

(5) FIG. 3 is a cross-sectional diagram illustrating a gate material having been deposited over the structure filling the trenches according to an embodiment of the present invention;

(6) FIG. 4 is a cross-sectional diagram illustrating the gate material having been polished down to the surface of the oxide layer resulting in bottom gates embedded in the insulator layer (and an ion implantation when poly-silicon (poly-Si) is used as the gate material) according to an embodiment of the present invention;

(7) FIG. 5 is a cross-sectional diagram illustrating a gate dielectric having been deposited on the bottom gates according to an embodiment of the present invention;

(8) FIG. 6 is a cross-sectional diagram illustrating a carbon material having been deposited on the gate dielectric according to an embodiment of the present invention;

(9) FIG. 7 is a cross-sectional diagram illustrating source and drain metal contacts having been formed to the carbon material according to an embodiment of the present invention;

(10) FIG. 8 is a cross-sectional diagram illustrating that during operation of the device, the bottom gates will each be biased at a different gate voltage which electrically dopes the overlaying carbon channel to become n-type or p-type according to an embodiment of the present invention;

(11) FIG. 9a is an image taken of an LED device fabricated using the present techniques having a poly-Si bottom gate and metal source and drain contacts according to an embodiment of the present invention; and

(12) FIG. 9b is an image which provides a close-up view of the present poly-Si bottom gate structure according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(13) Provided herein are carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof. FIG. 1 is cross-sectional diagram illustrating a starting structure for the fabrication process. As shown in FIG. 1 a substrate 102 is provided. According to an exemplary embodiment, substrate 102 is a silicon (Si) substrate. However, any other suitable substrate material may be employed in the same manner. By way of example only, bulk germanium (Ge) or silicon germanium (SiGe) wafers may also be used as the substrate. Alternatively, glass or plastic substrates may also be used.

(14) Next, an insulator layer 104 is formed (deposited or grown) on substrate 102. According to an exemplary embodiment, insulator layer 104 is formed from an oxide material, such as silicon dioxide (SiO.sub.2), that is deposited on substrate 102 using chemical vapor deposition (CVD) to a thickness of from about 10 nanometers (nm) to about 1,000 nm, e.g., from about 100 nm to about 500 nm. Alternatively, when the substrate 102 is formed from a semiconductor material, such as Si, Ge or SiGe as described above, the insulator layer 104 can be grown on the substrate 102 using an oxidation process, such as thermal oxidation. By way of example only, when the substrate 102 is formed from Si, then the insulator layer 104 formed by thermal oxidation would be SiO.sub.2. According to the exemplary embodiment wherein the insulator layer 104 is formed from a thermal oxide, the insulator layer can have a thickness of from about 50 nm to about 2,000 nm, e.g., from about 100 nm to about 1,000 nm.

(15) As will be described in detail below, trenches will be etched in the insulator layer 104 that extend part way through the layer. To facilitate the etching process, it might be preferable to instead employ a bilayer insulator layer configuration (i.e., wherein the insulator layer 104 is actually composed of two different materials). According to this exemplary alternative embodiment, the insulator layer 104 can be formed by depositing a first insulating layer on the substrate 102 and then depositing a second insulating layer on the first insulating layer. The first insulating layer and the second insulating layer will together form the insulating layer 104a (see FIG. 1A). In this case, the insulating layer is given the reference numeral 104a so as to distinguish it from the single layer insulating layer embodiment shown in FIG. 1.

(16) The idea behind this bi-layer insulating layer embodiment is that the trenches (to be formed later in the process) can be formed selectively through the top insulating layer (in this case the second insulating layer), stopping on the bottom insulating layer (in this case the first insulating layer). Since, as highlighted above, the trenches will extend only part way through the insulating layer, this bi-layer configuration makes etching the trenches easier, and in some cases more precise than with the single insulating layer embodiment (of FIG. 1). Thus, the first/second insulating materials should be selected so as to permit etch selectivity between the two materials.

(17) Two insulating materials that provide the desired etch selectivity are oxide and nitride materials. Thus, according to an exemplary embodiment, the first insulating layer is formed from a nitride material, such as silicon nitride (Si.sub.3N.sub.4), that is deposited on the substrate 102 using CVD. By way of example only, the first insulating layer is deposited onto the substrate 102 to a thickness of from about 50 nm to about 500 nm, e.g. from about 100 nm to about 300 nm. In this exemplary embodiment, the second insulating layer is formed from an oxide material, such as SiO.sub.2, that is deposited on the first insulating layer also using CVD. By way of example only, the second insulating layer is deposited onto the first insulating layer to a thickness of from about 50 nm to about 500 nm, e.g. from about 100 nm to about 300 nm.

(18) This configuration is shown illustrated in FIG. 1A. Accordingly, to etch trenches that extend part way through the insulator layer 104 is then easily accomplished using an oxide-selective etch (such as an oxide-selective reactive ion etching (RIE)) to etch the oxide portion of the bilayer insulator using the underlying nitride portion of the bilayer insulator as an etch stop (see below).

(19) At least two trenches 202a and 202b are then formed adjacent to one another in insulator layer 104. See FIG. 2. As shown in FIG. 2, the trenches 202a and 202b extend part way through the insulator layer 104. This configuration ensures electrical isolation between the gates which will be formed in the trenches later on in the process.

(20) According to an exemplary embodiment, trenches 202a and 202b each have a depth of from about 50 nm to about 500 nm, e.g., from about 100 nm to about 300 nm in the insulator layer 104, and are spaced apart from one another by a distance of from about 50 nm to about 2,000 nm, e.g., from about 100 nm to about 1,000 nm (see, e.g., FIG. 2). According to an exemplary embodiment, trenches 202a and 202b are patterned as lines in the insulating layer 104 (or 104a, see FIG. 2A). These lines would not be visible in the cross-sectional depiction shown in the figures, but it would be apparent to one of ordinary skill in the art how patterned lines would appear. In that case, the patterned lines would preferably be formed parallel to one another.

(21) Trenches 202a and 202b may be formed using standard lithography and etching processes. By way of example only, a patterned hardmask may first be formed on the insulating layer 104. The patterning of the hardmask will correspond to the footprint and location of the trenches 202a and 202b. A dry etching process, such as RIE, can then be used to pattern the trenches 202a and 202b. Any remaining hardmask after the RIE step can then be removed, e.g., by etching.

(22) When, as described above, the insulator layer 104 is composed of a single layer, such as single SiO.sub.2 layer, a timed etch can be used to achieve the proper depth of the trenches 202a and 202b in the (single layer) insulator layer 104. Since the trenches 202a and 202b would in this case be patterned in the same RIE step, these trenches would naturally have approximately the same depth (e.g., 1 nm).

(23) Alternatively, when as described above a bilayer insulator layer 104a is employed, then an etch selective for the upper layer (the second insulating layer in the example above) may be employed to achieve the desired depth of the trenches 202a and 202b in the insulator layer 104a. In the case of a bilayer insulator layer 104a having an oxide layer over a nitride layer, an oxide-selective RIE etch may be performed to etch the trenches 202a and 202b in the oxide layer using the nitride layer as an etch stop. In this case, the depth of the trenches would be commensurate with the thickness of the oxide layer portion of the bilayer insulator layer. This configuration is shown illustrated in FIG. 2A. The remainder of the process will be illustrated by way of reference to the embodiment employing a single material insulator layer 104 (i.e., that of FIGS. 1 and 2) with the understanding that, from this point forward in the process, the exact same steps would be employed in the case of a bilayer insulator.

(24) A gate material 302 is then blanket deposited over the structure, filling trenches 202a and 202b. See FIG. 3. Suitable gate materials include, but are not limited to, polysilicon, a metal (such as a TaN, TiN, W, or aluminum) or a combination of metals (such as TiN/Al). Polysilicon may be deposited using a CVD process, such as low-pressure CVD (LPCVD) or plasma-enhanced CVD (PECVD). Metal gate materials may be deposited using e-beam evaporation, a physical vapor deposition (PVD), atomic layer deposition (ALD) or an electroplating process. When multiple metals are employed, the metals can be deposited as separate layers in a stack or as an alloy.

(25) Next, the gate material 302 is polished down to the surface of insulator layer 104, e.g., using chemical-mechanical polishing (CMP) or other suitable etching process. The result is a pair of either metal or polysilicon bottom gates 402a and 402b of the device embedded in the insulator layer 104. See FIG. 4. When polysilicon is used as the gate material, an additional ion implantation step is needed to dope the polysilicon. This step is shown illustrated by arrows 404 in FIG. 4. Suitable dopants for the implantation step include, but are not limited to, arsenic (As), boron (B) and phosphorus (P). This is a maskless process since each of the (in this case polysilicon) bottom gates 402a and 402b will receive the same dopant. The ion implantation process parameters would be apparent to one of skill in the art. No ion implantation is needed when a metal gate material is being employed.

(26) To form an LED, electrostatic doping will be used to form an n-gate and a p-gate. Specifically, during operation of the device, bottom gates 402a and 402b will each be biased at a different gate voltage, e.g., Vg1 and Vg2, respectively, which electrically dopes the overlaying carbon channel to become n-type or p-type. See, for example, FIG. 8, described below. An p-type/n-type LED is the result.

(27) Advantageously, the use of a bottom-gated structure in the present techniques prevents the gates from covering and blocking light emission from the device. As described above, with conventional configurations, the gates are positioned such that light emission from the device is at least partially blocked by the gates thus reducing the overall device efficiency.

(28) A gate dielectric 504 is then deposited on the bottom gates 402a and 402b and at least a portion of insulator layer 104. See FIG. 5. The gate dielectric will separate the bottom gates 402a and 402b from a (carbon-based) channel of the device (see FIG. 6, described below). According to an exemplary embodiment, the gate dielectric 504 is composed of a high-K dielectric material, such as hafnium oxide (HfO.sub.2), aluminum oxide (Al.sub.2O.sub.3) or Si.sub.3N.sub.4 and is deposited on the bottom gates 402a and 402b using CVD or ALD.

(29) Advantageously, with the present techniques a higher quality dielectric (as compared to conventional top-gated designs) can be formed since the above-described problems associated with forming a dielectric on a carbon material are avoided. Namely, since the carbon material will be deposited/transferred (see below) onto an already formed gate/gate dielectric structure, then issues related to depositing dielectric materials onto the carbon material are altogether avoided.

(30) A carbon material 602 is then deposited on the gate dielectric 504 over the bottom gates 402a and 402b (i.e., the gate dielectric 504 separates the carbon material 602 from the bottom gates 402a and 402b). See FIG. 6. According to an exemplary embodiment, the carbon material 602 is made up of carbon nanotubes. As is known in the art, carbon nanotubes are allotropes of carbon having a cylindrical structure. Either single-walled or multi-walled carbon nanotubes may be employed in accordance with the present techniques. Carbon nanotubes can be randomly dispersed onto the gate dielectric 504 or can be deposited onto the gate dielectric 504 using a transfer process as is known in the art.

(31) Alternatively, the carbon material can be made up of graphene. As is known in the art, graphene is an allotrope of carbon with a structure resembling a honeycomb configuration. A graphene sheet or sheets can be deposited onto the gate dielectric 504 using a transfer process, such as exfoliation.

(32) The carbon material 602 will serve as a channel region of the device. If necessary, the carbon material 602 can be patterned. For example, if a transfer process is used, the length of the transferred carbon nanotube film is typically greater than 10 micrometers (m) (and can sometimes be as long as 200 m). Films of this dimension might electrically short adjacent devices if the film is not patterned. The desired dimensions, of course, depend on the particular device at hand.

(33) Standard patterning processes may be employed to pattern the carbon material 602. By way of example only, patterned photoresist can be used to protect the carbon material 602 within the channel region (i.e., the region above the gates). An oxygen (O.sub.2) plasma can then be used to etch away the exposed carbon nanotubes.

(34) Source and drain metal contacts 702s and 702d are then formed to the carbon material 602. See FIG. 7. According to an exemplary embodiment, contacts 702s and 702d are formed by first depositing a metal or metals and then patterning the metal(s) into contacts 702s and 702d. Suitable metals for use in forming contacts 702s and 702d include, but are not limited to, titanium (Ti). The contact metal may be deposited using, for example, e-beam evaporation. By way of example only, the contact metal may be patterned using a lift-off patterning process. Lift-off patterning techniques are known to those of skill in the art. In general however, lift-off patterning involves first forming a mask covering areas on which deposition of the metal is not desired. The metal is then deposited through the mask such that when the mask is removed, the metal on the mask is also removed. Fabrication of the LED device is now complete.

(35) As shown in FIG. 8, during operation of the device, bottom gates 402a and 402b will each be biased at a different gate voltage, e.g., Vg1 and Vg2, respectively, which electrically dopes the overlaying carbon channel to become n-type or p-type. According to an exemplary embodiment, Vg1 is a negative gate voltage and Vg2 is a positive gate voltage, or vice-a-versa. Because there are two gates with different gate biases, a region 802 of the carbon material 602 on top of the gate with the negative gate voltage (bottom gate 402a in FIG. 8) will become p-doped (p region) (hole carrier dominates) and a region 804 of the carbon material 602 on top of the gate with the positive gate voltage (bottom gate 402b in FIG. 8) will be n-doped (n region) (electron dominates). An ungated region 806 of the carbon material 602 (i.e., a portion under which no gate is present) will become an intrinsic region (i region). The result is a p-i-n diode. When the diode is biased under forward bias condition, electron and hole will start to recombine (mostly in the intrinsic region) and light emission will occur.

(36) FIG. 9a is an image taken of an LED device fabricated using the present techniques. FIG. 9a illustrates the poly-Si bottom gated structure and metal source and drain contacts. FIG. 9b is an image which provides a more close-up view of the poly-Si bottom gate.

(37) Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.