Impedance Driver for Bi-Stable and Multi-Stable Displays and Method to Drive Same

Abstract

A method to drive bi-stable liquid crystal displays and related drivers and displays using same are disclosed. The method and driver use additional high impedance states of the outputs to save power while addressing bi-stable and multi-stable liquid crystal displays. The invention implements high impedance states at the driver outputs, allowing non-addressed sections of the display to electrically “float” and by doing so reduces the required power to drive the display. Other advantages include improved visual effect of an update, such as reduced flash during the update, simpler operation, and better yields due to a larger operating window.

Claims

1. A method of addressing a passive matrix liquid crystal display comprising: providing a plurality of pixels, wherein the plurality of pixels is arranged into a plurality of rows and a plurality of columns to form an array, and wherein each pixel in the plurality of pixels comprises a plurality of liquid crystal molecules, and wherein an electric signal applied to one of the plurality of rows and one of the plurality of columns creates an electric field across plurality of liquid crystal molecules of each pixel in the plurality of pixels at an intersection of the one of the plurality of rows and the one of the plurality of columns; providing a row driver comprising a plurality of row outputs; providing a column driver comprising a plurality of column outputs; outputting a row signal on at least one of the plurality of row outputs; outputting a column signal on at least one of the plurality of column outputs; driving a target image using the row signal and the column signal; setting at least one of the plurality of row outputs or at least one of the plurality of column outputs to a high impedance state; and addressing the passive matrix liquid crystal display by applying a voltage to at least one of the plurality of pixels within the array.

2. The method of addressing a passive matrix liquid crystal display of claim 1, wherein the row driver and the column driver are integrated into a display driver.

3. The method of addressing a passive matrix liquid crystal display of claim 1, wherein at least one of the plurality of row outputs assumes a high impedance state when at least one column is addressed.

4. The method of addressing a passive matrix liquid crystal display of claim 1, wherein at least one of the plurality of column outputs assumes a high impedance state when at least one row is addressed.

5. The method of addressing a passive matrix liquid crystal display of claim 1, wherein at least one of the plurality of row outputs and at least one of the plurality of column outputs assume a high impedance state when at least one row is addressed.

6. The method of addressing a passive matrix liquid crystal display of claim 1 further comprising: applying a positive voltage and a negative voltage to the plurality of rows and the plurality of columns, and applying a voltage reduction to reduce the required active row and column voltage swing.

7. The method of addressing a passive matrix liquid crystal display of claim 1, wherein the passive matrix liquid crystal display is a zenithal bi-stable display.

8. The method of addressing a passive matrix liquid crystal display of claim 1, wherein the passive matrix liquid crystal display is a cholesteric liquid crystal display.

9. The method of addressing a passive matrix liquid crystal display of claim 1 further comprising: providing an external stimulus; and selecting a high impedance state based on the external stimulus.

10. The method of addressing a passive matrix liquid crystal display of claim 9, wherein the external stimulus is an environmental operating parameter.

11. A low power passive matrix liquid crystal display comprising: a plurality of pixels, wherein: the plurality of pixels is arranged into a plurality of rows and a plurality of columns to form an array; each pixel in the plurality of pixels comprises a plurality of liquid crystal molecules, and an electric signal applied to one of the plurality of rows and one of the plurality of columns creates an electric field across plurality of liquid crystal molecules of each pixel in the plurality of pixels at an intersection of the one of the plurality of rows and the one of the plurality of columns; a row driver comprising a plurality of row outputs, wherein the row driver outputs a row signal on at least one of the plurality of row outputs; a column driver comprising a plurality of column outputs, wherein the column driver outputs a column signal on at least one of the plurality of column outputs; and wherein at least one of the plurality of row outputs or one of the plurality of column outputs assumes a high impedance state while applying a voltage to at least one of the plurality of pixels within the array to address the low power passive matrix liquid crystal display.

12. The low power passive matrix liquid crystal display of claim 11, wherein the plurality of row drivers and the plurality of column drivers is an integrated row and column driver.

13. The low power passive matrix liquid crystal display of claim 12, wherein the integrated row and column driver further comprises an integrated display.

14. The low power passive matrix liquid crystal display of claim 11, wherein the low power passive matrix liquid crystal display is a bi-stable display.

15. The low power passive matrix liquid crystal display of claim 11, wherein the low power passive matrix liquid crystal display is a multi-stable display.

16. The low power passive matrix liquid crystal display of claim 11, wherein the low power passive matrix liquid crystal display is a zenithal bi-stable display.

17. The low power passive matrix liquid crystal display of claim 11, wherein the low power passive matrix liquid crystal display is a cholesteric liquid crystal display.

18. The low power passive matrix liquid crystal display of claim 11, further comprising: a plurality of modes of operation selected from the group consisting of high impedance row addressing, high impedance column addressing, high impedance row and column addressing, and standard no high impedance addressing; and wherein the plurality of modes of operation are selected based on an external stimulus.

19. The low power passive matrix liquid crystal display of claim 18, wherein the external stimulus is an environmental operating parameter.

20. A liquid crystal display driver for a passive matrix liquid crystal display comprising: a row driver comprising a plurality of row outputs; a column driver comprising a plurality of column outputs; and wherein at least one of the plurality of row outputs or one of the plurality of column outputs assumes a high impedance state while addressing a low power passive matrix liquid crystal display.

20. The liquid crystal display driver for the low power passive matrix liquid crystal display of claim 20 further comprising: an integrated display; and a timing controller.

21. The liquid crystal display driver for the low power passive matrix liquid crystal display of claim 20 further comprising at least two selectable modes of operation for determining whether high impedance addressing is used for rows, columns, rows and columns, or neither rows nor columns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG. 1 shows an equivalent capacitor circuit for a two-by-two pixels display.

[0038] FIG. 2 shows an example of a two-by-two pixels display.

[0039] FIG. 3 shows an example embodiment of a linear switch array that can be used to achieve a high impedance state at the output of a driver.

[0040] FIG. 4 shows a block diagram of an example embodiment of a display driver including the linear switch array of FIG. 3.

[0041] FIG. 5 shows the schematic of an example embodiment of a ZBD display in two polarizer reflective geometry.

[0042] FIG. 6 shows an example embodiment of Path 110 with SEG2 and COM2 active and the effect of high impedance on COM1 and SEG1.

[0043] FIG. 7 shows oscilloscope traces for an example embodiment of a two-by-two pixels display when a FLOAT voltage is applied to inactive SEG and COM using a black and white checkerboard similar to that in FIG. 2.

[0044] FIG. 8 shows a FLOAT voltage on both SEG and COM in Column [1] compared with standard addressing using typical values for non-select voltages in Column [2]. Both cases use the same values for active SEG and COM.

[0045] FIG. 9 shows a table of example relative power consumption under different addressing modes and images.

[0046] FIG. 10 shows an example embodiment of a method of addressing a bi-stable display utilizing a high impedance driver being applied to both inactive COM and SEG whereby all active pixel voltages are fully balanced across COM and SEG in Column [1], compared with standard addressing using typical values for non-select voltages in Column [2].

[0047] FIG. 11 shows an example embodiment of a method of passive matrix liquid crystal display addressing.

[0048] FIG. 12 shows a table of example absolute power consumption under different addressing modes and images using an integrated circuit.

[0049] FIG. 13 shows a further table of example relative power consumption under different addressing modes and images using an integrated circuit.

DETAILED DESCRIPTION OF THE INVENTION

[0050] The following is a detailed description of various embodiments to illustrate the principles of the invention. The embodiments are provided to illustrate aspects of the invention, but the invention is not limited to any embodiment. The scope of the invention encompasses numerous alternatives, modifications, and equivalents. The scope of the invention is limited only by the claims.

[0051] While numerous specific details are set forth in the following description to provide a thorough understanding of the invention, the invention may be practiced according to the claims without some or all of these specific details.

[0052] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0053] As used herein, the terms “row-”, “common-”, “coms-”, such as in row electrode, row signal, or row driver shall mean pertaining to the group of items such as electrodes, drivers, outputs, or signals, that are involved with scanning one or a few rows at a time until each have been scanned once during a frame time. The terms “column-”, “segment-”, “seg-”, such as in column electrode, columnsignal, or columndriver shall mean pertaining to the group of items such as electrodes, drivers, outputs, or signals that are involved in determining the resulting state the pixel will adopt. The terms “select-” and “sel-” as in select state, select voltage, or select signal and “non-select-”, “n-sel” as in non-select state, non-select voltage, or non-select signal, shall mean pertaining to an item such as state, voltage, or signal, that relates to one of two final states of the pixel. Whether or not select will lead to a bright or a dark pixel is determined by the optical configuration. “Select-” and “non-select-” may differ in voltage level, polarity, or a specific or inverted sequence of pulses. A “select” voltage turns a pixel “On,” a “non-select” voltage turns a pixel “Off.” “On” can mean bright or dark, depending on the optical configuration, and “Off” is the opposite of “On.”

Equivalent Circuit 100 for a Two-by-Two Pixel Display

[0054] FIG. 1 illustrates equivalent circuit 100 for a two-by-two pixels display 150, as shown in FIG. 2.

[0055] Equivalent circuit 100 includes columns SEG1 and SEG2, rows COM1 and COM2, and pixel capacitors C1, C2, C4, and C5. FIG. 1 further shows example path 110 for electrical charge to flow to SEG1 and COM1 when a high impedance state is applied to inactive columns and rows, such as where only COM2 and SEG2 are active. In other embodiments, such as for larger LCDs with larger pixel counts, the principles as disclosed herein are the same, except that there will be multiple charge paths. Thus, the principles as disclosed herein apply to any other matrix of larger dimensions, for example a 6 x 14 or a 480 x 360 or any other matrix in landscape, portrait or square format. As one of skill in the art would understand, for these larger matrix displays there are many and more complex capacitive charge divider paths involving series of pixel capacitors between floating rows and columns and terminating at the driven row and column, analogous to the path 110 shown for equivalent circuit 100.

[0056] A display driver according to this invention needs to be able to output specific voltage levels or settings, such as 0 V/GND, 5 V, 20 V, or other voltages at some of the common and segment driver outputs, while other common and/or segment outputs are held at a high impedance state, thus allowing the voltages on the corresponding rows and columns to float.

[0057] FIG. 4 illustrates a block diagram of an example display driver 200 including linear switch array 210, column driver 220, and row driver 230 that may be used to drive a display. FIG. 3 illustrates linear switch array 210 within display driver 200 that can enable a high impedance state to be applied to any given row or column driver output.

[0058] In alternative embodiments, some display drivers are not integrated with both COM and SEG driver functions, but are specialized COM drivers and specialized SEG drivers. The same concept applies to these types of drivers. Adding, for example, a linear switch array to a dedicated COM or SEG driver will allow such modified drivers to be used for this invention.

[0059] For example, in one embodiment as shown in FIG. 1, a column driver 220 (as shown in FIG. 4) applies a voltage pulse to the column SEG2, while a row driver 230 (as shown in FIG. 4) applies another voltage pulse to the row COM2. COM1 and SEG1 are floating, as the column driver 220 and the row driver 230 hold the corresponding outputs at high impedance. As a result, the potential difference between COM2 and SEG2 is directly applied to pixel capacitor C5 and is divided across pixel capacitors C1, C2, and C4 in path 110.

[0060] The resulting capacitance between the row driver 230 and the column driver 220 is substantially the capacitance of C5, which experiences the full voltage differential, as all other pixel capacitors C1, C2 and C4 are floating and the voltages across C1, C2 and C4 are smaller and defined by various possible capacitive voltage dividers formed by a larger display matrix.

[0061] Further, as with the simplified embodiment shown in FIG. 1, such a capacitive voltage divider may be the capacitance between the driven column SEG2 to floating row COM1, and from there to floating column SEG1 and from there back to the driven row COM2. In other embodiments, other such paths are possible in a larger display matrix. The resulting voltage levels on all the pixels of the undriven rows depend on the image that is being displayed. And, if such voltage differences are small compared to the threshold voltage at which the liquid crystal changes state, there is no detrimental impact on the image quality.

[0062] Further, such an addressing scheme without full control of pixel voltages, meaning control over when they are allowed to float, may cause a small residual DC voltage despite polarity inversion in the drive signals. However, such DC voltage is small and only temporary as it discharges through the display after addressing is stopped.

[0063] A sufficiently small DC voltage below the electrochemical potential for possible redox reactions will not damage the display and if the duration of the applied DC voltage is short, no significant detrimental image quality effects, such as retention of ghost images, will result. This addressing scheme may be designed within the display driver 200 function that provides the relevant voltage and high impedance states that allow the present invention to be applied, in various embodiments, for bi-stable and multi-stable displays such as Binem (bistable nematic) displays, ZBD (Zenithal bistable) displays or ChLCD (cholesteric liquid crystal) displays. However, in alternative embodiments, other passive matrix type displays may be used.

[0064] Thus, the detrimental effects of high impedance row driving remain below a threshold at which they are of concern. And, driving only one row or a few rows at a time while holding all other rows at high impedance reduces the capacitive load of the addressing circuit by the number of rows driven divided by the total number of rows plus stray capacitances.

[0065] In other embodiments, the same concept can be applied to high impedance addressing with column drivers 220 where the addressing and the power benefits depend on the image content. For example, in one exemplary embodiment, if a white pixel requires zero volts or only a small voltage while a black pixel requires a large voltage, the column driver 220 could alternate between driving the voltage at the level for turning a pixel black and holding the output at high impedance.

[0066] In another example embodiment as shown in FIG. 5, a ZBD display 300 in crossed polarizer reflective configuration is shown. In ZBD display 300, grating 330 on one of the internal surfaces stabilizes two possible optical states, TN state 310 or HAN state 320. Ambient light 340 and 345 incident on ZBD display 300 is polarized by the front polarizer 360 and passes through the device. If the liquid crystal cell 350 is in the Defect or TN state 310, then this polarized light is rotated on both passes through the liquid crystal cell 350 via the rear polarizer 370 and reflector 380 that then provides a white state 390 on the second pass through the front polarizer 360. If the liquid crystal cell 350 is in the Continuous or HAN state 320 then the polarized light is not rotated and is absorbed by the rear polarizer 370 to provide the black state 395. Defect state and Continuous state refer to the specifics of the liquid crystal director configuration inside the liquid crystal cell, being either continuous or discontinuous, respectively, and thus allowing for bi-stability.

[0067] In this configuration, a two-field addressing scheme is used where the ZBD display 300 is fully latched (or blanked) into the all-white state 390 in the first field, before in a second field only those pixels that need to be black are changed. In the case of both the row COM2 and column SEG2 of display 150 being active, the given pixel is written and latched into the black state. For all cases with a row and/or column being inactive (floating), the pixel’s state remains unchanged, e.g., white.

[0068] Turning to FIG. 6, charge path 110 is shown in a linear representation together with the expected resulting voltage levels at Com 1 and Seg 1. Column SEG2 is loaded with a voltage Vseg2 and row COM2 is held at zero volts, or ground. Both row COM1 and column SEG1 have a high impedance state or FLOAT voltage applied.

[0069] In various embodiments, the magnitude of the FLOAT voltage will vary from display to display, depending on the resistive and capacitive effects of the pixel within a given display. Also, the magnitude will be dependent upon the number of paths across the cell gap of the display and the voltages applied to adjacent “active” tracks.

[0070] FIG. 7 shows oscilloscope traces of the measured output of a two-by-two pixels display, such as display 150 (FIG. 2), while a black and white checkerboard image is updated. Oscilloscope traces are actual output results when applying a high impedance state (i.e. FLOAT voltage) to inactive rows and columns and bipolar pulses to active rows and columns as per the two-field addressing scheme normally applied to ZBD display 300 (FIG. 5) as shown in FIGS. 1 and 2.

[0071] The oscilloscope traces show some of the possible permutations and resultant voltages including the charge path 110 that follows the sequence SEG2-COM1-SEG1-COM2 in the case where SEG2 and COM2 are active and COM1 and SEG1 are inactive and therefore floating.

[0072] FIG. 8 illustrates a comparison of both COM and SEG traces as a function of time during the write phase of a black and white checkerboard in ZBD display 300 (FIG. 5) for high impedance (FLOAT) addressing in column 1 and for standard ZBD addressing in column 2. These illustrations use signal profiles derived from the measured signal profiles of the two-by-two pixels display, such as display 150 (FIG. 2), as shown in FIG. 7.

[0073] FIG. 8 also shows the resultant signal profile across pixel capacitor C1 (a black pixel) given by the differential SEG1-COM1 and pixel capacitor C4 (a white pixel) given by the differential SEG1-COM2.

[0074] In this example, where a FLOAT voltage is applied to inactive COM and SEG, there may be some effect on the operating window due to the large monopolar pulses shown in the resultant of [SEG1 - COM2]. However, whether the effect on operating window is positive or negative will be dependent upon the parameters selected, such as data voltage under standard addressing, as well as display size and resolution. It is also expected that in the case of a FLOAT voltage applied to only inactive COM (rows) that there may be a more positive effect on the operating window.

[0075] FIG. 9 shows power savings table 900 summarizing the relative power savings for the different modes and images measured with a small test display and a using arbitrary function generators to create the row and column signals. High impedance outputs are truly disconnected during this measurement. The power consumption is shown for a display with resolution 6(SEG) x 14(COM) while applying the three different modes: SEG & COM floating 510, COM floating 520, and under normal addressing mode 530. In this particular embodiment, results for three different images are illustrated where one image is all White 550, meaning all pixels are off or inactive, one image is a black and white checkerboard 560, and one image is all Black 570, meaning all pixels are on or active. Also measured is the blanking field only where the first field in the two-field scheme that blanks the display is fully White.

[0076] In a further embodiment, one of skill in the art would understand a custom driver can be designed in order to utilize float addressing on a full-sized display. One example embodiment of such a driver can use a ZBD LCD display containing 400 × 300 pixels with a size of 4.2 inches diagonal.

[0077] FIG. 12 shows absolute power consumption table 1200 summarizing power consumption data taken for this example embodiment of this ZBD LCD display using an integrated circuit. In this case, the data shown in table 1200 is the total power consumption for both the blank and selection fields.

[0078] FIG. 13 shows relative power consumption table 1300 summarizing power consumption data taken for this same example embodiment of this ZBD LCD display using an integrated circuit. Both absolute and relative update energy, as shown in FIGS. 12 and 13 respectively, is compared for a 1 × 1 checkerboard pattern, full white, full black, and a black text on white background image. The power saving is greatest for full white or full black images, while a 1 × 1 checkerboard pattern shows no saving.

[0079] In a further embodiment, a novel method for bipolar addressing can be applied using a driver that is able to apply positive and negative voltages to both COM and SEG as well as a high impedance state. As data voltage is irrelevant in the case of a high impedance state being applied to inactive COMs and SEGs, it is possible to balance the active bipolar pulses across both the COM and SEG, thereby resulting in a reduction of up to half the voltage that would otherwise be applied to the electrode opposite a high impedance electrode. For example, pulse 805 in FIG. 10 shows one-half the amplitude compared to a similar location in FIG. 8. The consequence of this is that the floating electrode can tend towards a lower voltage level, but more importantly, the sign of the voltage will be the same sign as the potential applied to the adjacent “active” electrode.

[0080] An example of this method is illustrated in FIG. 10 in column 1, again compared to standard ZBD addressing in column 2 as reflected, for example, in U.S. Pat. No. 6,784,968. The high impedance state is applied to both inactive COMs and SEGs. Estimates of the floating voltage levels on the inactive COMs and SEGs are shown on FIG. 10 (801-804). The active COMs and SEGs are addressed synchronously with bipolar pulses of equal amplitude (1/2 V.sub.select) but opposite sign (805-808), where V.sub.select is the highest amplitude occurring in the standard ZBD drive scheme.

[0081] For example, pulse pairs 805|807 and 806|808 have inverted polarity and floating voltage levels 801 and 802 drift in the same direction as pulses 808 and 807, respectively. The resultant signal profile across C1 [SEG1 - COM1], a selected pixel, has a selection pulse 811 of equal amplitude to the standard ZBD addressing scheme shown in column 2, while the second pulse 812, which must be below the threshold for impacting the liquid crystal state, is even lower than in the standard ZBD addressing scheme.

[0082] Similarly, the resultant signal profile across C4 [SEG1 - COM1], a non-selected pixel has two pulses that are both lower than the higher pulse in the standard ZBD addressing scheme, which must be below the threshold of impacting the liquid crystal state. The maximum amplitude of the resultant signal of a non-select pixel (813, 814) is now reduced to below 1/2 V.sub.select, which is lower than the non-select voltage (V.sub.nonselect) under standard ZBD addressing.

[0083] The sign of the FLOAT potential is the important factor here. If the magnitude of the FLOAT potential is higher than that determined from FIG. 10, then the performance will be improved further.

[0084] FIG. 11 shows passive matrix liquid crystal display addressing method 1000. Starting at step 1010, a liquid crystal display cell comprising a plurality of rows and a plurality of columns is provided wherein the plurality of rows and the plurality of columns are arranged to form a plurality of pixels within an array, at least one row driver comprising a plurality of row outputs is provided, and at least one column driver comprising a plurality of column outputs is provided. Then, at step 1020, a target image is driven using the row display driver to provide the row signals and the column driver to provide the column signals. And, at step 1030, at least one of the plurality of pixels within the array is addressed, while at least one of the plurality of row outputs or one of the plurality of column outputs is set to a high impedance state.

[0085] In an alternative embodiment, the row driver and the column driver in step 1020 can be integrated into a display driver. In a further embodiment, at least a portion of the non-addressed plurality of row outputs at step 1030 assume a high impedance state. In a further embodiment, at least a portion of the plurality of column outputs assume a high impedance state when at least one row is addressed at step 1030. In a further embodiment, at least a portion of the non-selected plurality of row outputs and at least a portion of the plurality of column outputs assume a high impedance state during step 1030. In a further embodiment, the row signals and column signals are selected to address a zenithal bi-stable display or a cholesteric liquid crystal display. In a further embodiment, passive matrix liquid crystal display addressing method 1000 further comprises providing an external stimulus and selecting a high impedance state based on the external stimulus, which in one embodiment is an environmental operating parameter such as temperature or how much charge is left in a battery.

[0086] While the invention has been specifically described in connection with certain specific embodiments thereof, it is to be understood that this is by way of illustration and not of limitation. Reasonable variations and modifications are possible within the scope of the foregoing disclosure and drawings without departing from the spirit of the invention.