Digital ranging systems and methods

Abstract

A radar or sonar system amplifies the signal received by an antenna of the radar system or a transducer of the sonar system is amplified and then subject to linear demodulation by a linear receiver. There may be an anti-aliasing filter and an analog-to-digital converter between the amplifier and the linear receiver. The system may also have a digital signal processor with a network stack running in the processor. That processor may also have a network interface media access controller, where the system operates at different ranges, the modulator may produce pulses of two pulse patterns differing in pulse duration and inter-pulse spacing, those pulse patterns are introduced and used to form two radar images with the two images being derived from data acquired in a duration not more than twenty times larger than the larger inter-pulse spacing, or for a radar system, larger than one half of the antenna resolution time. One or more look-up tables may be used to control the amplifier. The radar system may generate digital output which comprises greater than eight levels of radar video.

Claims

1. A system comprising: an amplifier configured to amplify a plurality of return signals received in response to a plurality of transmitted ranging signals; an analog-to-digital converter configured to convert the amplified return signals to digital return signals; a linear demodulator configured to generate digital demodulated signals in response to the digital return signals; and a signal processor configured to process the digital demodulated signals for display and/or analysis.

2. The system of claim 1, wherein the analog-to-digital converter is a sub-sampling analog-to-digital converter.

3. The system of claim 2, further comprising: an anti-aliasing filter configured to filter the amplified return signals provided to the sub-sampling analog-to-digital converter; and a digital filter configured to filter the sub-sampled digital return signals provided to the linear demodulator.

4. The system of claim 2, wherein: the system further comprises a converter configured to convert the return signals to an intermediate frequency for amplification by the amplifier; and the sub-sampling analog-to-digital converter is configured to operate at a sample rate less than the intermediate frequency.

5. The system of claim 1, further comprising: a media access controller; a physical layer interface configured to communicate with a network; and wherein the signal processor is configured to pass the processed digital demodulated signals to the network through the media access controller and the physical layer interface.

6. The system of claim 5, wherein the media access controller and the physical layer interface are implemented by the signal processor.

7. The system of claim 1, wherein: the system is a radar or sonar system; the ranging signals are radar or sonar signals; and the ranging signals comprise a plurality of pulses.

8. The system of claim 1, further comprising: a controller configured to control a gain of the amplifier; and wherein the controller comprises at least one look-up table comprising data to compensate for range-dependent variation of the return signals.

9. The system of claim 1, wherein: the amplifier, the analog-to-digital converter, the linear demodulator, and the signal processor are provided by a receiver configured to process the return signals received in response to the ranging signals; and the system further comprises a transmitter configured to transmit the ranging signals.

10. The system of claim 1, further comprising: a display; and wherein the signal processor is configured to perform dynamic range compression on the processed digital demodulated signals to provide a pseudo-colour representation of the return signals comprising greater than eight levels of video to the display.

11. A method comprising: receiving a plurality of return signals in response to a plurality of transmitted ranging signals; amplifying the return signals; converting the amplified return signals to digital return signals; generating, by a linear demodulator, digital demodulated signals in response to the digital return signals; and processing the digital demodulated signals for display and/or analysis.

12. The method of claim 11, wherein the converting is performed by a sub-sampling analog-to-digital converter.

13. The method of claim 12, further comprising: filtering, by an anti-aliasing filter, the amplified return signals provided to the sub-sampling analog-to-digital converter; and filtering, by a digital filter, the sub-sampled digital return signals provided to the linear demodulator.

14. The method of claim 12, further comprising: converting the return signals to an intermediate frequency for the amplifying; and wherein the sub-sampling analog-to-digital converter is configured to operate at a sample rate less than the intermediate frequency.

15. The method of claim 11, further comprising passing the processed digital demodulated signals to a network through a media access controller and a physical layer interface.

16. The method of claim 15, wherein the media access controller and the physical layer interface are implemented by a signal processor performing the processing.

17. The method of claim 11, wherein: the ranging signals are radar or sonar signals; and the ranging signals comprise a plurality of pulses.

18. The method of claim 11, further comprising: controlling, by at least one look-up table, a gain associated with the amplifying; and wherein the look-up table comprises data to compensate for range-dependent variation of the return signals.

19. The method of claim 11, further comprising transmitting the ranging signals.

20. The method of claim 11, further comprising: performing dynamic range compression on the processed digital demodulated signals to provide a pseudo-colour representation of the return signals comprising greater than eight levels of video; and providing the video to a display.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) An embodiment of the present invention will now be described in detail, by way of example, with reference to the accompanying drawings in which:

(2) FIG. 1 is a block diagram of a known radar apparatus, and has already been described;

(3) FIG. 2 is a block diagram of a radar apparatus embodying the present invention;

(4) FIG. 3 is a graph of the relationship between gain and sensitivity of an amplifier against range;

(5) FIG. 4 is a graph showing the frequency characteristic of a filter of the embodiment to FIG. 2;

(6) FIG. 5 is a block diagram showing part of the apparatus of FIG. 2;

(7) FIG. 6 illustrates down-conversion of signals in the embodiment of FIG. 2;

(8) FIG. 7 illustrates data buffering in the embodiment of FIG. 2;

(9) FIG. 8 illustrates the time varying gain generator in FIG. 2;

(10) FIG. 9 illustrates the typical characteristic of the PIN diode attenuator shown in FIG. 2;

(11) FIG. 10 shows pulse patterns which may be used in the embodiment of the present invention;

(12) FIG. 11 is a block diagram of a known sonar system, and is similar to FIG. 1; and

(13) FIG. 12 is a block diagram of a sonar apparatus embodying the present invention, and is similar to FIG. 2.

DETAILED DESCRIPTION

(14) A radar apparatus embodying the various aspects of the invention will now be described in detail. FIG. 2 shows the general structure of the apparatus of this embodiment. As in the known arrangement of FIG. 1, the apparatus comprises five components, namely a control processor 100, a transmitter section 200, an antenna section 300, a receiver section 400, and a display section 500. Some of the sub-components of the transmitter section 200, antenna section 300, and receiver section 400 correspond to components of the transmitter section 20, the antenna section 30 and the receiver section 40 of the arrangement of FIG. 1, and the same reference numerals will be used for corresponding parts.

(15) However, the apparatus of FIG. 2 is intended to generate multiple displays at different radar ranges. Thus, the control processor 100 generates two types of pulse repetition frequency signals which are transmitted via separate digital buses 101, 102 to separate pulse duration units 201, 202. Each of those pulse duration units 201, 202 determines the duration of the respected pulses, in a manner similar to pulse duration unit 21. However, the duration of the pulses generated by the pulse duration units 201, 202 will be different. The resulting signals are combined by a logical OR component 203 before being passed to the modulator 22. As will be described in more detail later, the pulses are generated so that they are interleaved, with the manner of interleaving being determined by the desired ranges of images to be displayed.

(16) In the arrangement of FIG. 2, the structure of the antenna section 300 is similar to the antenna section 30 of the arrangement of FIG. 1. As in the arrangement of FIG. 1, signals received by the antenna 31 are passed via the circulator, a low noise converter (LNC) 41, a PIN attenuator 42 to a variable gain amplifier 44. However, the output of that variable gain amplifier 44 is processed in a different way from the arrangement of FIG. 1, as will be described in more detail later.

(17) In the embodiment of FIG. 2, the time varying gain (TVG) generator 401 is implemented using a series of combination of fixed and variable gain amplifiers and a PIN diode attenuator. Again, the TVG generator 401 is controlled using signals from the control processor 100 via a digital bus 12. However, in this embodiment, the output of the TVG generator 401 is converted by respective digital-to-analog converters 402, 403 to control the PIN attenuator 42 and the variable gain amplifier 44 respectively.

(18) FIG. 3 then illustrates the variation in gain sensitivity of the variable gain amplifier 44 which is needed for different ranges. These are controlled by the TVG generator 401.

(19) A fixed frequency anti-alias filter 404 follows the variable gain amplifier 44 to restrict the input signal bandwidth to:
Anti-alias filter bandwidth=IF frequency+/BW.sub.max.
where BW.sub.max is the bandwidth required for the optimum reception of the shortest pulses and IF is the desired intermediate frequency. The anti-aliasing filter 404, as above, cannot have an infinite roll-off rate. However it is possible to let some signal through outside this range, including that which is aliased. This signal will comprise thermal (white) noise, interference and higher harmonics of the received target signal. The subsequent digital filtering will remove most of the aliased, distorted signal, when used with narrower bandwidths (longer pulses) when the lowest noise and best performance is required. Interference from other pulsed radars is rejected, even when aliased into the selected bandwidth. A correlation technique is used based on multiple radar pulses. The remaining white noise, aliased into the selected bandwidth, simply degrades the noise performance marginally according to the ratio of selected bandwidth to aliasing filter skirt.

(20) The radar receiver described may use a single integrated circuit 14 bit ADC with integrated high-speed digital filter. The small size of this component and the high level of integration reduce the noise coupled into the low-noise front-end of the receiver.

(21) FIG. 4 then illustrates the frequency response of the anti-alias filter 404.

(22) The output of the anti alias filter 404 is passed via an analog-to-digital converter 405 to respective digital filters 406, 407 for each range of the radar. Those digital filters 406, 407 receives synchronising signals from the control processor 100 via a digital bus 103. The outputs of those digital filters 406, 407 are passed via respective spoke buffers 408, 409 to a signal processor 410, which generates a network output via network unit 411 to the display section 500.

(23) FIG. 5 shows part of the apparatus of FIG. 2 in more detail. As shown in FIG. 5, the signal processor 410 comprises a digital processor (DSP) 470, a static random access memory (SRAM) 471, a flash memory 472, a serial EEPROM 473 and serial digital-to-analog converter 474.

(24) FIG. 5 also shows a field programmable gate array (FPGA) 412 in which the TVG generator 401 and buffers 408, 409 are embodied. In fact, although shown as a separate component in FIG. 5, the digital filter 406 (and the digital filter 407) may also be embodied within the FPGA 412.

(25) FIG. 5 also shows that the network unit 410 comprises a host ported media access controller (MAC) and physical layer interface (PHY) 413, and an Ethernet connector 414.

(26) FIG. 5 also shows a sequencer 415 which controls the timing of the various components.

(27) The FPGA 412 generates an output on line 475 which is passed to the control processor.

(28) This embodiment uses a sub-sampling approach to reduce the analog-to-digital conversion sample rate. To facilitate sub-sampling, the IF frequency has been raised to 70 MHz. Without sub-sampling, the analog-to-digital conversion would require a minimum sample rate of 2*(70 MHz+(BW/2)) to satisfy the Nyquist criteria. For a 75 ns pulse, this equates to an analog-to-digital conversion sample rate of 2*76.6=153.2 MHz. High resolution analog-to-digital conversions working at this sample rate are expensive and may be subject to export restrictions. In practice the analog anti-alias filter 404 cannot have an infinite roll-off in the frequency domain, so the sample rate would need to be somewhat higher to avoid aliasing the signal in the skirt of the filter.

(29) The embodiment described uses a 57 MHz sample rate. The under-sampling in the analog-to-digital conversion aliases the signal to: 13 MHz+/BW/2. This sub-sampled signal is mixed in a complex mixer, also part of the digital filter IC, to produce a complex I,Q baseband signal. The complex base-band signal is then filtered in the digital filter to produce the matched bandwidth required of 0 Hz+/BW/2 (The mixed signal is complex I,Q). Under-sampling reduces the cost of the analog-to-digital conversion and the processing and memory required.

(30) When a large number of pulse-widths (say 8) is used, providing matched analog filtering becomes onerous to set-up, and liable to drift. This embodiment uses digital filtering of the IF, prior to conversion to base-band. Such digital filtering is linear and optimal; digitising then filtering conventional base-band log video cannot achieve the same result. In this design the entire digital signal processing, takes place in the linear domain, for which many processing algorithms are available (e.g. Fast Fourier Transform (FFT))

(31) The digital filter 406 can be re-loaded with different parameters when the user changes instrumented range, such that the optimised matched bandwidth is always used on each instrumented range. Thus there is no restriction on the number of different pulse-widths that can be optimally filtered. Alternatively, two or more filters can be made simultaneously available and the output of these selected, on a pulse-by-pulse basis, according to the required range. These filters can be reloaded separately when the user changes one of the instrumented ranges.

(32) FIG. 6 then illustrates the down-conversion from IF to baseband. The output of the digital filter 406 is in the form of complex I,Q pairs of sample data, which are converted into magnitude form and buffered in the FPGA 412. This buffer is illustrated in more detail in FIG. 7 in which respective dual ports pulse repetition interval (PRI) buffers 420, 421 controlled by respective address generators 422, 423 will receive appropriate inputs via parallel input ports 424 and output via a link port output 425.

(33) The TVG generator 401 will now be described in more detail. IL should be noted that the TVG generator 401 effectively comprises a plurality of generators for the different ranges at which the radar apparatus is operating. FIG. 8 illustrates the part of the structure of the TVG generator 401 for one such range. There will be similar structures within the TVG generator 401 for each range at which the radar system is to operate.

(34) The TVG generator needs to operate in real-time and thus calculation of the TVG function against time is identical and repeated on each transmitted pulse, for the same instrumented range. In this design one innovation is that the TVG function is implemented digitally using look-up tables. The look-up table contents only require re-calculation on each instrumented range change. The recalculation is the combination of the measured non-linearity of the gain control stages, which is measured at the time of manufacture, and the required range or time dependant gain function, including rain or sea-clutter curves if required. The final function is scaled for the sample rate of the output of the digital filter. These tables are loaded under software control only when the instrumented range is changed.

(35) Those look-up tables are illustrated at 430 and 431 in FIG. 8. In practice, those look-up tables may be implemented in a single table, with different table areas for the two tables 430, 431 illustrated in FIG. 8. Moreover, where there are different TVG generator structures for the different ranges, the look-up tables of the structures for the respective ranges may themselves be combined in a single look-up table, again with

(36) different table areas for the different structures.

(37) The loading of the lookup tables in this design is simplified by the use of dual ported SRAMs. These have a second address and data bus that is connected to the microprocessor bus that does not interfere with reading of the lookup tables by the hardware described below. The loading of the tables and error checking if required takes place over this second data and address bus in the same way that normal SRAM is accessed by a microprocessor. The loading of the tables is ignored for the remainder of this discussion.

(38) One gain control stage is normally inadequate to deal with the dynamic arrange of the input signal and preserve linearity in each of the analog stages. in this embodiment a PIN diode attenuator 42 is used before the variable gain amplifier (VGA) 44, to prevent saturation of the input of the VGA 44 for large signals. This gain also needs to be varied with range. Thus the gain control circuit should modify the gain of both the PIN diode attenuator 42 and the VGA throughout the acquisition of a single spoke.

(39) The PIN diode attenuator 42 is heavily non-linear with a control voltage as illustrated in FIG. 9; thus the lookup table contents for the PIN diode gain control apply the inverse non-linearity to transform the linearly increasing (with range) lookup table address to be the multiplication of the required range dependant gain (typically power gain of R^4) and the inverse non-linear function of the PIN diode attenuator.

(40) In FIG. 8, the signal PRI_PLS received on line 436 synchronises the circuit to the start of reception. A delay counter 432 delays the start of the range dependant gain control circuit to cancel the delay in the transmitter. The delay required is loaded from the TVG delay register 437 The read address counter 433 then increments, under control of clock Ts, as time progresses to access the lookup table contents appropriate for that range. In this embodiment the data for both digital-to-analog converters 402, is interleaved, with a multiplexor, over a single 8-bit RDAC bus, the multiplexing normally occurring at a rate faster than the output sample rate of the digital filters.

(41) A multiplexor 438 selects, using the digital-to-analog select signal received on line 439, the output of the appropriate lookup table 430 or 431 dependant on which digital-to-analog converter is to be driven, the digital-to-analog 402 connected to the PIN diode 42, or the digital-to-analog 403 connected to the variable gain amplifier 44.

(42) In a multi-range system, the lookup tables 430 and 431 are made large enough to accommodate the required tables for each of the ranges, and the most significant bits of the table read address are modified to determine which table is to be accessed for the current range to be acquired. The range to be acquired is signalled by the control processor 100 using digital bus 103.

(43) The delay counter 432 is decremented and read address counter 433 is incremented at a rate that can be modified dependant on the output rate of the digital filter, rather than the sample rate of the analog-to-digital converter. This sample rate is not externally accessible for the preferred digital filter used (AD6654); hence it is re-created by division of the analog-to-digital converter clock to produce a clock (Ts) at this rate. Rate divider circuitry 440, delay registers 441, rate divider phase 442 and frequency registers 443 synchronise the clock Ts to commence in synchronism with signal PRI_PLS and to recur at the sample rate, and sample phase applicable to that range. Thus the rate divider and registers are duplicated for each range that may be simultaneously acquired (one of two for dual ranging systems are shown in FIG. 8).

(44) The use of the lower rate, Ts, reduces the number of entries required in the range dependant table. The number of lookup table entries would typically be at least as long as the maximum samples in the digital filter output for the range to be acquired. In practice it is possible to reduce the number of entries. The analog output of the gain digital-to-analog converter 434 is filtered in an analog filter, which provides interpolation. Alternatively, the matching of the range dependant gain function to the desired function can be a stepwise approximation, provided the resulting gain steps are small and may be filtered in a later digital process before the final display.

(45) Simultaneously to range dependant gain control, another lookup table (EXP lookup data) 435 is accessed using the EXP bits as address. These bits are sourced from an AGC circuit that varies the gain of the analog stages to keep the signal within the dynamic range of the analog-to-digital converter. Three bits of EXP are available from the analog-to-digital converter used in this embodiment. Thus in this implementation 8 entries are required in the EXP lookup table 435. The EXP lookup table 435 can be used to control the gain or the EXP table can be set to all zeros to disable this function. Likewise if the analogue gain control circuit is non-linear, then the EXP lookup table 435 can contain the inverse non-linearity, to make the actual gain vary linearly with the value of the EXP bits. The slope of the thus linearised function can be varied to accommodate different scaling. For example the analog-to-digital converter used expects the gain to vary by 6 dB on each increment of EXP.

(46) The analog-to-digital converter used in this implementation, provides EXP outputs to request a gain change in the external analog stages:

(47) The gain in the gain-ranging block (external) is compensated for by relinearizing, using the exponent bits EXP[2:0] of the input port. For this purpose, the gain control bits are connected to the EXP[2:0] bits, providing an attenuation of 6.02 dB for every increase in the gain control output. After the gain in the external gain-ranging block and the attenuation in the AD6654 (using EXP bits), the signal gain is essentially unchanged. The only change is the increase in the dynamic range of the analog-to-digital converter.

(48) The outputs of the selected lookup table 430 or 431 and the AGC lookup tables are added together with saturating logic that ensures the result is kept within the range of the analog-to-digital converter and no over or underflow occurs. The contents of a diagnostic register, RDAC_DEBUG_DATA are added in this path to facilitate testing of the TVG generator 402.

(49) All of the lookup table contents are twos complement numbers that can be added together with the correct result given when negative numbers occur. To ensure the correct timing relationship of the digital-to-analog conversion data and control signals, the RDAC data is resynchronised in register 434 prior to leaving the TVG generator 402.

(50) The instantaneous signal, at a particular range, can still vary due to RCS variation and fading. The overall dynamic range of received radar signals is very large. It comprises the following elements:

(51) Range: The received signal power for a point reflector follows the law 1/R^4, (Ref. 1) where R is range. From the minimum range of say 50 m to a range of 20 NM, the dynamic range is 115 dB.

(52) The radar cross-section (RCS) of targets of interest varies by 50 dB

(53) Fading and multi-path effects contribute a further 30 dB of variation

(54) Thus the total dynamic range of interest is the sum of these: 195 dB

(55) Fortunately the range variation is predictable. TVG is applied to cancel the effect of the range variation, subject to the limits of thermal noise and variable gain amplifier noise and dynamic range.

(56) The instantaneous signal, at a particular range, may vary due to radar cross section (RCS) variation and fading. In practice there is a requirement for 80 dB of instantaneous dynamic range. The theoretical dynamic range of a 14 bit ADC is 84 dB. Signal processing, including Azimuth integration, is used to retrieve signals below one least significant bit (LSB), to further extend the dynamic range. Thus with full range compensation using TVG, adequate instantaneous dynamic range exists, using such a converter, for fully linear IF processing.

(57) The dynamic range of the radar signal, following signal processing, is still larger than the dynamic intensity range of the display. Dynamic range compression is used, but following the signal processing. A choice of algorithms for compression is then feasible, because the compression is performed in the DSP. These can be log, square root, or in special cases, linear for no compression.

(58) The output data comprises 8 bits (256 levels) that is converted to pseudo-colour in the display's processor.

(59) To facilitate connection of multiple displays, Ethernet is used as the connection from the scanner to the displays.

(60) The Ethernet media access controller/physical layer interface (MAC/PHY) connects to the bus of the digital signal processor and the network software stack runs on the digital signal processor itself, not a separate communications processor. This saves the additional cost and complexity of a multi-processor architecture.

(61) FIG. 2 also shows that the display section 500 of the radar apparatus generates different displays in multiple windows 501, 502, 503 (the total number n of such windows depending on the number of ranges at the which the radar is operated). Each window 501, 502, 503 receives a digital signal from the network unit 411 and displays an images corresponding to one of the ranges of the radar.

(62) Known multiple range radars interleave target detection of ranges on a revolution-by-revolution basis. The radar of this embodiment interleaves detection of targets on different instrumented ranges, and the display of the data for these ranges on a pulse-by-pulse basis. Thus there is simultaneous display of radar images from multiple instrumented ranges that was acquired at virtually the same instant, and is fully time-locked. The images are updated in real time so that the images are not displaying radar data older than that from a fraction of a revolution of the antenna.

(63) Interleaving of radar pulses of different characteristics is known, but the information from the different pulses is used to create separate, simultaneous displays for different instrumented ranges.

(64) Radar pulse characteristics including pulse width and repetition rate have to be optimised for range discrimination or signal to noise ratio dependent on the range to be displayed. Likewise pulses cannot be transmitted until the echoes for that range have been received. The processing of the received signals is filtered to optimise reception for each of the pulses characteristics. Pulses of different types are interleaved on transmission and the targets' echoes received are passed along separate paths. In the receiver each path is separately optimised for that pulse shape. More than one pulse of each type can be transmitted as part of the pulse pattern to permit the higher repetition rates required at shorter ranges. The pulse pattern is arranged to give the required ratio of pulse repetition rates for each range such that the transmitter's duty cycle is not exceeded.

(65) A suitable pulse pattern is illustrated in FIG. 10. In FIG. 10 pulses of pulse width P1 is the pulse duration for pulses optimised for a first range, and T1 is the acquisition interval for targets at that range. Similarly, P2 is the pulse duration for pulses optimised for a second range, with T2 being the corresponding acquisition interval. In each case, the acquisition interval follows the corresponding pulse, but is separated from the immediately following pulse by a variable interference rejection inter-pulse jitter period . This de-correlates targets at each range. In such an arrangement, the pulse repetition interval is the sum of the pulse duration, the acquisition interval and the maximum value of for each range.

(66) FIG. 10 shows that the pulses are interleaved, and in this embodiment there are three pulses for the second range between each pulse for the first range. Other combinations are, however, possible. However, table 1 then illustrates a possible pulse pattern, where (a, b) is the number of pulses of each type that are interleaved from (column a, row b).

(67) TABLE-US-00001 TABLE 1 Pattern Range (2) Pulse width (seconds) 75.0E9 100.0E9 150.0E9 250.0E9 350.0E9 450.0E9 600.0E9 1.0E6 Range (1) Pulse Nominal Nominal PRI, (sec) width PRI 333.3E6 333.3E6 333.3E6 333.3E6 500.0E6 625.0E6 769.2E6 1 .2E3 (seconds) (sec) Mode 1 2 3 4 5 6 7 8 75.0E9 333.3E6 1 1.1 1.1 1.1 1.1 3.2 2.1 7.3 11.3 100.0E9 333.3E6 2 0.0 1.1 1.1 1.1 3.2 2.1 7.3 11.3 150.0E9 333.3E6 3 0.0 0.0 1.1 1.1 3.2 2.1 7.3 11.3 250.0E9 333.3E6 4 0.0 0.0 0.0 1.1 3.2 1.1 7.3 11.3 350.0E9 500.0E6 5 0.0 0.0 0.0 0.0 1.1 4.3 3.2 5.2 450.0E9 625.0E6 6 0.0 0.0 0.0 0.0 0.0 1.1 7.6 11.6 600.0E9 769.2E6 7 0.0 0.0 0.0 0.0 0.0 0.0 1.1 8.5 1.0E6 1.2E3 8 0.0 0.0 0.0 0.0 0.0 0.0 0.0 1.1
These patterns are calculated from the ratio of PRIs for each row or column.

(68) In general, the pulse repetition rate (PRI) needs to be sufficient that enough pulses are generated within a suitable time to generate the appropriate displays simultaneously. In general, the pulse repetition must be sufficient that the data in any image is acquired over a time which is not greater than twenty times the longest interpulse period, in the case of FIG. 10 being the period between each pulse P1 for a radar, this duration also needs to be longer than one half of the antenna resolution time. Thus, in the embodiment of FIG. 2, it is necessary that the pulse repetition frequency determined by the control processor 100 is related to the speed of the motor 33. This may be pre-set, or could be based on measurement.

(69) When used with radar, the magnetron transmitter 23 can be replaced by another source of microwaves, such as an oscillator, and high power travelling wave tube amplifier or lower power solid state amplifier. In both sonar and radar, if lower power transmitters are used, it is normal to employ pulse compression to increase the average power transmitted, whilst not reducing the range resolution. The linear receiver used in this is suitable for use with radar and sonar employing pulse compression.

(70) The above embodiment illustrates a radar apparatus. A sonar system embodying the present invention may be similar, although with the antenna 31 replaced by a transducer, and with the magnetron replaced by a high power RF generator. Moreover, the pulse intervals and pulse widths. of Table 1 would then be modified to accommodate the slower velocity of acoustic waves in water to that of radio waves in air.

(71) FIG. 11 of the accompanying drawings shows a known sonar apparatus. Most of the sonar apparatus of FIG. 11 is similar to the radar apparatus of FIG. 1, and corresponding parts will be indicated by the same reference numerals. Thus, the sonar apparatus of FIG. 11 comprises five principal components, namely a processor 10, a transmitter section 20, an antenna structure 603, a receiver structure 40 and a display structure 50. The processor 10 generates pulse initiation signals which are passed via a digital bus 11 to the transmitter section 20. The processor also generates signals for controlling the receiver section 40, which are passed from the processor 10 to the receiver section 40 via a second digital signal bus 12. The display structure 50 of this sonar apparatus is the same as the display structure 50 of the radar apparatus of FIG. 1 and thus will not be described in detail now.

(72) The pulse initiation signals from the processor 10 are received at a pulse duration unit 21 in the transmitter section 20, which determines the pulse width of the pulses to be generated. The pulses are initiated by an edge of the pulse initiation signal, and their duration is thus fixed. This is the same as in the radar apparatus of FIG. 1 however, the resulting pulse information is passed to a high power amplifier 601 which drives a transformer 602 to match the oscillator to the sonar transducer 603. That transformer 602 passes the sonar pulse to the transducer 603 from which they are transmitted. That sonar transducer 603 is normally a piezo-electric device that produces high power acoustic pulses in water, which will form the sonar signals. When return signals are received at the transducer 603, they are passed via the transformer 602 to a low noise amplifier 604 which increases the amplitude of the signals to an appropriate level. Band-pass filter 605 filters the received signals to reduce unwanted noise. Generally, the high power oscillator will produce pulses in the Long and Medium wave-band region 50 to 250 KHz, in which case the band-pass filter will be tuned to the appropriate centre frequency.

(73) The signals from the band pass filter 605 are passed to an attenuator 606 which, in a similar way to the PIN alternator 42 of FIG. 1, is controlled by a Time Varying Gain (TVG) generator 43 which is controlled by the processor 10 on the basis of the signals passed via a bus 12. That TVG generator 43 controls the gain of the receiver section 40 to compensate for range variation of the signal received by the transducer. The TVG generator 43 also controls a variable amplifier 44 which receives the output of the attenuator 606 and controls the gain of the received signal. The output of the variable gain amplifier 44 is passed to a log detector 45 which generates an output which is the logarithm of the envelope with a received signal. That output is passed to a selectable band filter (video filter 46) which generates the output to the display section 50.

(74) A sonar apparatus embodying the various aspects of the invention will now be described in detail. FIG. 12 shows the general structure of the apparatus of this embodiment. Again, most of the sonar apparatus of FIG. 12 is similar to the radar apparatus of FIG. 2, and corresponding parts are indicated by the same reference numerals. The sonar apparatus of FIG. 12 also has many of the features of the sonar apparatus of FIG. 11, and again corresponding parts are indicated by the same reference numerals. Thus, the apparatus comprises five components, namely a control processor 100, a transmitter section 200, a transducer section 603, a receiver section 400, and a display section 500. The display section of the sonar apparatus of FIG. 11 is the same as the display section 500 of the radar apparatus of FIG. 2, and so will not be described in detail now.

(75) Unlike the sonar apparatus of FIG. 11, the apparatus of FIG. 12 is intended to generate multiple displays at different sonar ranges. Thus, the control processor 100 generates two types of pulse repetition frequency signals which are transmitted via separate digital buses 101, 102 to separate pulse duration units 201, 202. Each of those pulse duration units 201, 202 determines the duration of the respected pulses, in a manner similar to pulse duration unit 21. However, the duration of the pulses generated by the pulse duration units 201, 202 will be different. The resulting signals are combined by a logical OR component 203 before being passed to the high power oscillator 601. The pulses are generated so that they are interleaved, with the manner of interleaving being determined by the desired ranges of images to be displayed.

(76) In the arrangement of FIG. 12, the structure of the transducer section 603 is similar to the transducer section 603 of the arrangement of FIG. 11. As in the arrangement of FIG. 11, the transducer 603 receives signals from the high power amplifier 601 via the transformer 602. The return signals received by the transducer 602 are passed via the transformer 602, a low amplifier (LNA) 604 a band-pass filter 605, an attenuator 606 to a variable gain amplifier 44. However, the output of that variable gain amplifier 44 is processed in a different way from the arrangement of FIG. 11, namely in the same way as the output of the variable gain amplifier 44 is processed in the embodiment of FIG. 2.

(77) In the embodiment of FIG. 12, the time varying gain (TVG) generator 401 is implemented using a series of combination of fixed and variable gain amplifiers and an attenuator. Again, the TVG generator 401 is controlled using signals from the control processor 100 via a digital bus 12. However, in this embodiment, the output of the TVG generator 401 is converted by respective digital-to-analog converters 402, 403 to control the attenuator 606 and the variable gain amplifier 44 respectively.

(78) As mentioned above, the output of the variable gain amplifier 44 is processed in the same way as the output of the variable gain amplifier 44 in the embodiment of FIG. 2. The components of the receiver section 400 and display section 500 which process signals from the variable gain amplifier 44 are the same in FIGS. 2 and 11. Thus, the processing of the signals is as described with reference to FIGS. 3 to 10. Normally, there will then be differences in the display generator, since radar apparatuses tend to generate circular display, which is not appropriate for sonar arrangements. Also, as previously mentioned, the pulse intervals and pulse widths of Table 1 would have to be modified to accommodate the slow velocity of acoustic waves in water, as compared with radio waves in air. However, these differences do not affect the signal processing described with reference to the first embodiment.