METHOD AND DEVICE FOR THE PROTECTION OF DATA INTEGRITY THROUGH AN EMBEDDED SYSTEM HAVING A MAIN PROCESSOR CORE AND A SECURITY HARDWARE MODULE

Abstract

A method for protecting data integrity through an embedded system having a main processor core and a security hardware module. The method includes the following: the main processor core generates transmit data, the security hardware module calculates a transmit message authentication code from the transmit data, the main processor core links the transmit data and the transmit message authentication code to form a transmit message, and the main processor core transmits the transmit message to a receiver.

Claims

1. A method for protecting data integrity through an embedded system having a main processor core and a security hardware module, the method comprising: generating, by the main processor core, transmit data; calculating, by the security hardware module, a transmit message authentication code from the transmit data; linking, by the main processor core, the transmit data and the transmit message authentication code to form a transmit message; and transmitting, by the main processor core, the transmit message to a receiver.

2. The method as recited in claim 1, further comprising one of: recognizing, by the receiver, based on the transmit message, if the transmit message authentication code is calculated with errors; or recognizing, by the receiver, based on the transmit message, if the transmit message authentication code (16) is transmitted with errors from the security hardware module to the main processor core.

3. The method as recited in claim 1, further comprising: receiving, by the main processor core, a receive message having receive data and a first receive message authentication code; calculating, by the security hardware module, from the receive message, a second receive message authentication code; carrying out, by the security hardware module, based on the first receive message authentication code and the second receive message authentication code, an information security test; and carrying out, by the main processor core, based on the first receive message authentication code and the second receive message authentication code, a functional safety test.

4. The method as recited in claim 3, wherein, in the information security test, the first receive message authentication code is compared with the second receive message authentication code, if the first receive message authentication code differs from the second receive message authentication code, the information security test fails, and if the first receive message authentication code agrees with the second receive message authentication code, the information security test ends successfully.

5. The method as recited in claim 3, wherein, in the functional safety test, the first receive message authentication code is compared with the second receive message authentication code, if the first receive message authentication code differs from the second receive message authentication code, the functional safety test fails, and if the first receive message authentication code agrees with the second receive message authentication code, the main processor core uses the receive data.

6. The method as recited in claim 3, wherein the main processor core or the security hardware module recognize if the second receive message authentication code is calculated with errors.

7. The method as recited in claim 3, wherein the main processor core recognizes if the second receive message authentication code is transmitted with errors from the security hardware module to the main processor core.

8. A non-transitory machine-readable storage medium on which is stored a computer program for protecting data integrity through an embedded system having a main processor core and a security hardware module, the computer program, when executed by a processor, causing: generating, by the main processor core, transmit data; calculating, by the security hardware module, a transmit message authentication code from the transmit data; linking, by the main processor core, the transmit data and the transmit message authentication code to form a transmit message; and transmitting, by the main processor core, the transmit message to a receiver.

9. A device for protecting data integrity, the device comprising an embedded system having a main processor core and a security hardware module, wherein the main processor core is designed to transmit data, the security hardware module is designed to calculate a transmit message authentication code from the transmit data, the main processor core is designed to link the transmit data and the transmit message authentication code to form a transmit message, and the main processor core is designed to transmit the transmit message to a receiver.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 shows the flow diagram of a transmit method according to a first specific embodiment of the present invention.

[0012] FIG. 2 shows the flow diagram of FIG. 1 with identification of new malfunctions relevant to functional safety.

[0013] FIG. 3 shows the flow diagram of a receive method according to a second specific embodiment of the present invention.

[0014] FIG. 4 shows the flow diagram of FIG. 3 with identification of new malfunctions relevant to functional safety.

[0015] FIG. 5 schematically shows a control device according to a third specific embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0016] Specific embodiments of the present invention include two main designs (10, 30) for realizing the MAC processing.

[0017] The first design (10) is to route the data path through the main processor core (11) so that the data themselves cannot be damaged by the security hardware module (12). This module can use a copy of the data for the processing, but for the transmission the main processor core (11) should use data that cannot be modified or manipulated by the security hardware module (12). In this way, the functional safety properties of the main processor core (11) are maintained.

[0018] FIG. 1 shows this in the case of transmission: the main processor core (11) first produces (13) transmit data (14). The security hardware module (12) calculates (15) from these transmit data (14) a transmit message authentication code (16). The main processor core (11) links (17) the transmit data (14) and the transmit message authentication code (16) to form a transmit message (18), and, finally, transmits (19) this message to the provided receiver.

[0019] FIG. 2 also shows the remaining potential malfunctions: if the transmit message authentication code (16) is calculated (15) with errors (21), the receiver nonetheless recognizes (20) this on the basis of the transmit message (18). The same holds correspondingly if the transmit message authentication code (16) is transmitted with errors (22) from the security hardware module (12) to the main processor core (11).

[0020] The second design (30) relates to the case in which the main processor core (11) receives (31) a receive message (32) having receive data (33) and having a first receive message authentication code (35). Here, the check of the first receive message authentication code (35) includes two basic steps that are standardly combined in a function call verifyMAC: first, a second receive message authentication code (36) is generated (34) on the basis of the receive message (32), containing a first receive message authentication code (35), and the preinstalled key. Second, the calculated second receive message authentication code (36) is compared (42) with the received first receive message authentication code (35). Because this comparison is a process relevant to functional safety, this should be executed on the main processor core (11), as is shown in FIG. 3 and in FIG. 4 together with the remaining relevant malfunctions: if the second receive message authentication code (36) is calculated (34) with errors (45), this is easily recognized (44) by the main processor core (11) or by the security hardware module (12). The main processor core (11) likewise recognizes (46) if the second receive message authentication code (36) is transmitted with errors (47) from the security hardware module (12) to the main processor core (11). A redundant evaluation (39) of the receive message authentication codes by the security hardware module (12) ensures information security in this case as well.

[0021] It can be pointed out that this separation (30) of the two substeps of MAC verification may stand in conflict with certain design principles of information security. Because the receiver has only to verify, and not to generate, the first receive message authentication code (35), the fundamental security paradigm of least privilege would require limiting of the functional access at the receiver side to the checking of the first receive message authentication code (35), instead of permitting the generation (34) of the second receive message authentication code (36). The latter functionality (34) could be used by an attacker to use a compromised receiver node to impersonate a transmitter. Therefore, it is recommended to choose the variant realization (30) in accordance with system priorities.

[0022] This method (10, 30) can for example be implemented in software or hardware, or in a mixed form of software and hardware, for example in a control device (50), as illustrated by the schematic representation of FIG. 5.