Semiconductor device having improved heat dissipation

Abstract

A semiconductor device having improved heat dissipation is disclosed. The semiconductor device includes a semi-insulating substrate and epitaxial layers disposed on the semi-insulating substrate wherein the epitaxial layers include a plurality of heat conductive vias that are disposed through the epitaxial layers with the plurality of heat conductive vias being spaced along a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers. The semiconductor device further includes an electrode having a plurality of electrically conductive fingers that are disposed along the plurality of finger axes such that the electrically conductive fingers are in contact with the first plurality of heat conductive vias.

Claims

1. A method of fabricating a semiconductor device having improved heat dissipation comprising: providing a semi-insulating substrate; disposing epitaxial layers on the semi-insulating substrate; disposing a plurality of heat conductive vias through the epitaxial layers with the plurality of heat conductive vias being arranged in rows that are aligned parallel to a plurality of finger axes that are aligned generally parallel across a surface of the epitaxial layers; and disposing an electrode with a plurality of electrically conductive fingers along the plurality of finger axes such that individual ones of the plurality of electrically conductive fingers extend over corresponding rows of the plurality of heat conductive vias and are in contact with the plurality of heat conductive vias.

2. The method of claim 1 further including disposing a second plurality of heat conductive vias through the epitaxial layers with the second plurality of heat conductive vias being arranged in rows that are aligned parallel to a second plurality of finger axes that are interdigitated with the plurality of finger axes, and disposing a second electrode with a second plurality of electrically conductive fingers along the second plurality of finger axes such that individual rows of the second plurality of electrically conductive fingers extend over corresponding rows of the second plurality of heat conductive vias and are in contact with the second plurality of heat conductive vias.

3. The method of claim 1 further including extending the plurality of heat conductive vias into the semi-insulating substrate.

4. The method of claim 1 further including filling the plurality of heat conductive vias with an electrically conductive material.

5. The method of claim 4 further disposing a through-hole via into the semi-insulating substrate to electrically couple and thermally couple the plurality of heat conductive vias to a back metal.

6. The method of claim 1 wherein the semi-insulating substrate is made of silicon carbide (SiC) polytypes.

7. The method of claim 6 wherein the SiC polytypes have a bulk thermal conductivity that ranges from around about 3.6 W/cm.Math.K to around about 4.9 W/cm.Math.K.

8. The method of claim 1 wherein a bulk electrical resistivity of the semi-insulating substrate ranges from around about 10.sup.7 ohm-cm to around about 10.sup.12 ohm-cm.

9. The method of claim 8 further including selecting material for making up the semi-insulating substrate from at least one member of the group consisting of SiC, silicon (Si), GaN, zinc oxide (ZnO), aluminum oxide (Al.sub.2O.sub.3), and gallium oxide (Ga.sub.2O.sub.3).

10. The method of claim 1 wherein the semiconductor device is a GaN HEMT.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1A is a cross-sectional view of a prior art gallium nitride (GaN) high electron mobility transistor (HEMT) depicting a buffer layer between GaN device layers and a semi-insulating substrate.

(3) FIG. 1B is a plan view of the prior art GaN HEMT depicting through-wafer vias electrically coupled to a bus of the source electrode near the edge of a die periphery.

(4) FIG. 2A is a cross-sectional view of an exemplary semiconductor device in the form of a GaN HEMT having heat conductive vias coupled to drain and source electrodes in accordance with the present disclosure.

(5) FIG. 2B is a plan view of the GaN HEMT of FIG. 2A showing pluralities of heat conductive vias in contact with drain and source fingers.

(6) FIG. 3 is a cross-sectional view of an exemplary embodiment of a semiconductor device in the form of a GaN HEMT in which heat conductive vias are further extended into a semi-insulating substrate.

(7) FIG. 4A is a cross-sectional view of an exemplary embodiment of a semiconductor device in the form of a GaN HEMT having through-wafer vias that provide an electrical connection to heat conductive vias.

(8) FIG. 4B is a plan view of the GaN HEMT of FIG. 4A showing a plurality of heat conductive vias in contact with drain fingers and the through-wafer vias.

DETAILED DESCRIPTION

(9) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(10) It will be understood that when an element such as a layer, region, or substrate is referred to as being over, on, in, or extending onto another element, it can be directly over, directly on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over, directly on, directly in, or extending directly onto another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

(11) Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. Moreover, the term high resistivity and the term semi-insulating are used interchangeably throughout the disclosure. Furthermore, the term semi-insulating refers to being electrically insulating.

(12) FIG. 2A is a cross-sectional view of an exemplary semiconductor device 40 in the form of a GaN HEMT with a buffer layer 42 between GaN device layer(s) 44 and a semi-insulating substrate 46. The buffer layer 42 and the GaN device layer(s) 44 make up epitaxial layers 48. A source electrode 50, a gate electrode 52 and a drain electrode 54 are disposed onto a surface 56 of the epitaxial layers 48. FIG. 2A also shows one of a first plurality of heat conductive vias 58 that that are disposed through the epitaxial layers 48 to collectively thermally couple the source electrode 50 to the semi-insulating substrate 46. Similarly, FIG. 2A further shows one of a second plurality of heat conductive vias 60 that are disposed through the epitaxial layers 48 to collectively thermally couple the drain electrode 54 to the semi-insulating substrate 46.

(13) The semi-insulating substrate 46 has a bulk electrical resistivity that ranges from around about 10.sup.7 ohm-cm to around about 10.sup.12 ohm-cm. As a result of this high bulk resistivity range, no significant electrical current flows through the semi-insulating substrate 46 between the source electrode 50 and the drain electrode 54. Suitable materials for the semi-insulating substrate 46 include, but are not limited to high electrical resistivity silicon carbon (SiC), silicon (Si), gallium nitride (GaN), zinc oxide (ZnO), aluminum oxide (Al.sub.2O.sub.3), and gallium oxide (Ga.sub.2O.sub.3).

(14) FIG. 2B is a plan view of the semiconductor device 40 of FIG. 2A showing the first plurality of the heat conductive vias 58 being spaced along a first plurality of finger axes 62 that are aligned generally parallel across the surface 56 of the epitaxial layers 48. The source electrode 50 includes a first plurality of electrically conductive fingers 64 that are disposed along the first plurality of finger axes 62 such that the first plurality of electrically conductive fingers 64 are in contact with the first plurality of the heat conductive vias 58. Each of the second plurality of the heat conductive vias 60 are spaced along a second plurality of finger axes 66 that are interdigitated with the first plurality of finger axes 62. The drain electrode 54 includes a second plurality of electrically conductive fingers 68 that are disposed along the second plurality of finger axes 66 such that the second plurality of electrically conductive fingers 68 is in contact with the second plurality of the heat conductive vias 60. Excess heat generated around the first plurality of electrically conductive fingers 64 and the second plurality of electrically conductive fingers 68 is relatively efficiently conducted through the first plurality of the heat conductive vias 58 and the second plurality of the heat conductive vias 60 to the semi-insulating substrate 46 where the excess heat is dissipated.

(15) FIG. 3 is a cross-sectional view of an exemplary embodiment of the semiconductor device 40 in which the first plurality of the heat conductive vias 58 and the second plurality of the heat conductive vias 60 are further extended into a semi-insulating substrate 46. By extending the first plurality of the heat conductive vias 58 and the second plurality of the heat conductive vias 60 into the semi-insulating substrate 46, even greater heat dissipation can be realized.

(16) FIG. 4A is a cross-sectional view of an exemplary semiconductor device 70 in the form of a GaN HEMT with a buffer layer 72 between GaN device layer(s) 74 and a semi-insulating substrate 76. The buffer layer 72 and the GaN device layer(s) 74 make up epitaxial layers 78. A source electrode 80, a gate electrode 82 and a drain electrode 84 are disposed onto a surface 86 of the epitaxial layers 78. FIG. 4A shows one of a plurality of heat conductive vias 88 that are disposed through the epitaxial layers 78 to collectively thermally couple the drain electrode 84 to the semi-insulating substrate 76. In addition, FIG. 4A shows one of a plurality of through hole vias 90 disposed into the semi-insulating substrate 76 to collectively thermally and electrically couple the drain electrode 84 to a back metal 92. Through hole vias 90 are relatively large compared to heat conductive vias 88 therefore direct contact between through hole vias 90 and drain electrode 84 would require relatively wider drain electrodes 84 which would undesirably increase chip size.

(17) FIG. 4B is a plan view of the semiconductor device 70 of FIG. 4A showing the plurality of the heat conductive vias 88 being spaced along a plurality of finger axes 94 that are aligned generally parallel across the surface 86 of the epitaxial layers 78. The drain electrode 84 includes a plurality of electrically conductive fingers 96 that are disposed along the plurality finger axes 94 such that the plurality of electrically conductive fingers 96 are in contact with the plurality of the heat conductive vias 88. In this exemplary embodiment, each of the plurality of heat conductive vias 88 are filled with an electrically conductive material such as metal. Excess heat generated around the plurality of electrically conductive fingers 96 is relatively efficiently conducted through the plurality of the heat conductive vias 88 to the semi-insulating substrate 76 and the back metal 92 where the excess heat is dissipated. While FIGS. 4A and 4B only show the drain being electrically and thermally coupled to the back metal 92 it is to be understood that the drain and/or source can be routed to the back metal 92 to improve thermal and/or electrical performance while reducing die area by eliminating a need for bond pads (not shown) on the front side of a die.

(18) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.