SIMO POWER CONVERTER AND CONTROL METHOD THEREOF

Abstract

A SIMO power converter includes: a power stage having an inductor and a plurality of switches, the power stage generating a plurality of output voltages from an input voltage; a control circuit, the control circuit controlling the SIMO power converter to be operated at either an OPDC (Ordered Power Distributive Control) mode or a Peak Current Control (PCC) mode according with different loading conditions, the control circuit further generating a plurality of duty cycles based on an inductor current of the inductor and the plurality of output voltages; and a logic control and gate driver for generating a plurality of switch control signals based on the duty cycles from the control circuit, the plurality of switch control signals for controlling the plurality of switches of the power stage.

Claims

1. A SIMO (Single Inductor Multiple Output) power converter including: a power stage having an inductor and a plurality of switches coupled to the inductor, the power stage generating a plurality of output voltages from an input voltage; a control circuit coupled to the power stage, the control circuit controlling the SIMO power converter to be operated at either an OPDC (Ordered Power Distributive Control) mode or a Peak Current Control (PCC) mode according with different loading conditions, the control circuit further generating a plurality of duty cycles based on an inductor current of the inductor and the plurality of output voltages; and a logic control and gate driver, coupled to the control circuit and the power stage, the logic control and gate driver generating a plurality of switch control signals based on the duty cycles from the control circuit, the plurality of switch control signals for controlling the plurality of switches of the power stage.

2. The SIMO power converter according to claim 1, wherein in the OPDC mode, at least one channel of a plurality of channels needs energy for every clock cycle continuously; and wherein a plurality of energy distributing duty cycles are decided by a corresponding error amplifier (EA) output of the channel and the inductor current.

3. The SIMO power converter according to claim 2, wherein when the corresponding error amplifier (EA) output of the channel of the plurality of channels is lower than a predetermined voltage, the channel does not need energy for a next clock cycle and the channel enters a pulse skipping mode (PSM) mode.

4. The SIMO power converter according to claim 3, wherein when all the channels operate at the PSM mode or there are a predetermined successive cycles of zero inductor current signal detected, the SIMO power converter enters the PCC mode.

5. The SIMO power converter according to claim 4, wherein in the PCC mode, when no channel needs energy and the inductor current is discharged to zero, the SIMO power converter enters a sleep mode, in the sleep mode, an oscillator and a plurality of EAs of the SIMO power converter are all turned off; and in the sleep mode, if any channel of the plurality of channels needs energy, the oscillator is enabled, and the SIMO power converter goes back to the PCC mode.

6. The SIMO power converter according to claim 4, wherein for all the channels in the PSM mode, when no channel needs energy continuously more than the predetermined number of clock cycles, the SIMO power converter keeps in the PCC mode.

7. The SIMO power converter according to claim 6, wherein for a channel in the PSM mode, the error amplifier of the channel is turned off; and the EA of the channel is turned on while the channel is going back to an EA mode, in the EA mode, the energy distributing duty cycle is response to the EA output.

8. The SIMO power converter according to claim 7, wherein an energy generating period under the PCC mode is decided by a specified inductor peak current or by a constant time period.

9. The SIMO power converter according to claim 7, wherein if there is at least one channel operated at the EA mode, the SIMO power converter operates at the OPDC mode; and an energy generating duty is in response of a sum of a plurality of control voltages, wherein the control voltage is the EA output at the EA mode and the control voltage is the predetermined voltage at the PSM mode.

10. A control method for a SIMO (Single Inductor Multiple Output) power converter generating a plurality of output voltages from an input voltage, the control method including: controlling the SIMO power converter to be operated at either an OPDC (Ordered Power Distributive Control) mode or a Peak Current Control (PCC) mode according with different loading conditions; generating a plurality of duty cycles based on an inductor current of an inductor and the plurality of output voltages; and generating a plurality of switch control signals based on the duty cycles, the plurality of switch control signals for controlling a plurality of switches of the SIMO power converter.

11. The control method according to claim 10, wherein in the OPDC mode, at least one channel of a plurality of channels needs energy for every clock cycle continuously; and wherein a plurality of energy distributing duty cycles are decided by a corresponding error amplifier (EA) output of the channel and the inductor current.

12. The control method according to claim 11, wherein when the corresponding error amplifier (EA) output of the channel of the plurality of channels is lower than a predetermined voltage, the channel does not need energy for a next clock cycle and the channel enters a pulse skipping mode (PSM).

13. The control method according to claim 12, wherein when all the channels operate at the PSM mode or there are a predetermined successive cycles of zero inductor current signal detected, the SIMO power converter enters the PCC mode.

14. The control method according to claim 13, wherein in the PCC mode, when no channel needs energy and the inductor current is discharged to zero, the SIMO power converter enters a sleep mode.

15. The control method according to claim 14, wherein in the sleep mode, an oscillator and a plurality of EAs of the SIMO power converter are all turned off; and in the sleep mode, if any channel of the plurality of channels needs energy, the oscillator is enabled, and the SIMO power converter goes back to the PCC mode.

16. The control method according to claim 14, wherein for all the channels in the PSM mode, when no channel needs energy continuously more than the predetermined number of clock cycles, the SIMO power converter keeps in the PCC mode.

17. The control method according to claim 16, wherein for a channel in the PSM mode, the error amplifier of the channel is turned off; and the EA of the channel is turned on while the channel is going back to an EA mode, in the EA mode, the energy distributing duty cycle is response to the EA output.

18. The control method according to claim 17, wherein an energy generating period under the PCC mode is decided by a specified inductor peak current or by a constant time period.

19. The control method according to claim 17, wherein if there is at least one channel operated at the EA mode, the SIMO power converter operates at the OPDC mode; and an energy generating duty is in response of a sum of a plurality of control voltages, wherein the control voltage is the EA output at the EA mode and the control voltage is the predetermined voltage at the PSM mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 shows a circuit diagram of a SIMO (Single Inductor Multiple Output) power converter according to one embodiment of the application.

[0010] FIG. 2 shows a circuit diagram of the energy generating circuit according to one example of the application.

[0011] FIG. 3 shows a circuit diagram of the energy distributing circuit according to one example of the application.

[0012] FIG. 4A shows imperfect balance and FIG. 4B shows perfect balance in one embodiment of the application.

[0013] FIG. 5 shows DCM OPDC with three Channels in PSM according to one embodiment of the application.

[0014] FIG. 6 shows inductor peak current in one embodiment of the application.

[0015] FIG. 7 shows signal diagram of the SIMO power converter 100 in one embodiment of the application.

[0016] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DESCRIPTION OF THE EMBODIMENT

[0017] Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definitions of the terms are based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the field could selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure.

[0018] FIG. 1 shows a circuit diagram of a SIMO (Single Inductor Multiple Output) power converter according to one embodiment of the application. As shown in FIG. 1, the SIMO power converter 100 according to one embodiment of the application includes a power stage 110, a control circuit 120 and a logic control and gate driver 130. The power stage 110 of the SIMO power converter 100 generates a plurality of output voltages V.sub.O1, V.sub.O2, . . . , V.sub.Om (m being a positive integer) from an input voltage V.sub.IN. In the following, the SIMO power converter 100 has a plurality of channels; and a channel is defined as a signal path for generating an output voltage among the plurality of output voltages V.sub.O1, V.sub.O2, . . . , V.sub.Om. The plurality of output voltages V.sub.O1, V.sub.O2, . . . , V.sub.Om may be also referred as channel output voltages.

[0019] The power stage 110 includes an inductor L1, a plurality of switches SWP, SWN, SWR, SW1, SW2, . . . , SWm, a plurality of capacitors C10, C11, C12, . . . C1m, and a plurality of loads Load1, Load2 . . . , Loadm. The switches SWP, SWN, SWR are also referred as input switches while the switches SW1, SW2, . . . , SWm are also referred as output switches.

[0020] The inductor L1 is coupled between a first node LX1 and a second node LX2. An inductor current I.sub.L flows through the inductor L1. The inductor L1 is coupled to the switches SWP, SWN, SWR, SW1, SW2, . . . , SWm.

[0021] The switch SWP is coupled between the input voltage VIN and the first node LX1. The switch SWN is coupled between a ground terminal GND and the first node LX1. The switch SWR is coupled between the input voltage VIN and the second node LX2. The switch SW1 is coupled between the second node LX2 and the first output voltage V.sub.O1. The switch SW2 is coupled between the second node LX2 and the second output voltage V.sub.O2. The switch SWm is coupled between the second node LX2 and the m-th output voltage V.sub.Om.

[0022] The capacitor C10 is coupled between the input voltage V.sub.IN and the ground terminal GND. The plurality of capacitors C11, C12, . . . C1m, and the plurality of loads Load1, Load2 . . . , Loadm are coupled in parallel between the output voltages V.sub.O1, V.sub.O2, . . . V.sub.Om and the ground terminal GND, respectively. Still further, the power stage 110 has a current sense circuit which senses a current I.sub.L/k (k being a positive number) to the control circuit 120. The current I.sub.L/k is 1/k of the inductor current I.sub.L.

[0023] The control circuit 120 is coupled to the power stage 110. The control circuit 120 includes a plurality of error amplifiers (EA) 121_1˜121_m, a plurality of comparators 122_1˜122_m, a control unit 123, an energy generating circuit 124, a plurality of energy distributing circuits 125_1˜125_m, an oscillator 126 and a zero current detector (ZCD) 127. The current I.sub.L/k from the power stage 110 is fed into the energy generating circuit 124 for energy generating and energy distributing calculation. Also, the current I.sub.L/k from the power stage 110 is fed into the control unit 123 for peak current control. Also, the current I.sub.L/k from the power stage 110 is fed into the zero current detector 127 for zero current detection.

[0024] The plurality of error amplifiers 121_1˜121_m generate a plurality of error amplifier output voltages V.sub.EAO1˜V.sub.EAOm based on the output voltages V.sub.O1, V.sub.O2, . . . V.sub.Om and a plurality of reference voltages V.sub.R1, V.sub.R2, . . . , V.sub.Rm, respectively. The error amplifier output voltages V.sub.EAO1˜V.sub.EAOm are input into the energy generating circuit 124 and the plurality of energy distributing circuits 125_1˜125_m.

[0025] The plurality of comparators 122_1˜122_m generate a plurality of comparator output voltages V.sub.D1˜V.sub.Dm based on the output voltages V.sub.O1, V.sub.O2, . . . V.sub.Om and the plurality of reference voltages V.sub.R1, V.sub.R2, . . . , V.sub.Rm, respectively. The comparator output voltages V.sub.D1˜V.sub.Dm are input into the control unit 123.

[0026] The control unit 123 is coupled to the plurality of comparators 122_1˜122_m for receiving comparator output voltages V.sub.D1˜V.sub.Dm to perform sleep mode control function and peak current control (PCC) function. In the sleep mode control function, the control unit 123 generates a sleep mode control signal SM to the plurality of error amplifiers (EA) 121_1˜121_m and the oscillator 126; and in response to the sleep mode control signal SM from the control unit 123, the plurality of error amplifiers (EA) 121_1˜121_m and the oscillator 126 enter a sleep mode for reducing power consumption. In the peak current control function, the control unit 123 generates a plurality of duty cycles D′.sub.P, D′.sub.N, D′.sub.1, D′.sub.2, . . . , D′.sub.m based on the comparator output voltages V.sub.D1˜V.sub.Dm. For example but not limited by, in one example, the comparator output voltages V.sub.D1˜V.sub.Dm determines which output voltage(s) V.sub.O1, V.sub.O2, . . . V.sub.Om need(s) more energy; and on-time period of the duty cycles D′.sub.P, D′.sub.N, D′.sub.1, D′.sub.2, . . . , D′.sub.m from the control unit 123 may be a fixed value or determined based on the input voltage V.sub.IN, the output voltages V.sub.O1, V.sub.O2, . . . V.sub.Om, the inductance of the inductor L1 and the capacitance of the output capacitors C.sub.11, C.sub.12, . . . , C.sub.1m. Still further, in another example, generation of the duty cycles OP, D′.sub.N, D′.sub.1, D′.sub.2, . . . , D′.sub.m may be determined based on a peak inductor current on the inductor L1, wherein the peak inductor current may be a fixed value or determined based on the input voltage V.sub.IN, the output voltages V.sub.O1, V.sub.O2, . . . V.sub.Om, the inductance of the inductor L1 and the capacitance of the output capacitors C.sub.11, C.sub.12, . . . , C.sub.1m.

[0027] The energy generating circuit 124 is coupled to the plurality of error amplifiers 121_1˜121_m. The energy generating circuit 124 generates a charging duty cycle D.sub.P based on the plurality of error amplifier output voltages V.sub.EAO1˜V.sub.EAOm, wherein during the on period of the charging duty cycle D.sub.P, the inductor L1 is charged by the input voltage V.sub.IN. Further, the energy generating circuit 124 generates a discharging duty cycle D.sub.N based on the charging duty cycle D.sub.P, wherein during the on period of the discharging duty cycle D.sub.N, the inductor L1 is discharged. The charging duty cycle D.sub.P and the discharging duty cycle D.sub.N are complementary. For example but not limited by, sum of the charging duty cycle D.sub.P and the discharging duty cycle D.sub.N are equal to a clock cycle T.sub.CK (T.sub.CK=D.sub.P+D.sub.N) wherein the clock cycle T.sub.CK is a clock cycle of a clock signal generated by the oscillator 126.

[0028] The plurality of energy distributing circuits 125_1˜125_m are coupled to the plurality of error amplifiers 121_1˜121_m. The plurality of energy distributing circuits 125_1˜125_m generate a plurality of duty cycles D.sub.1˜D.sub.m (i.e. the first duty cycle D1 to the m-th duty cycle D.sub.m) based on the plurality of error amplifier output voltages V.sub.EAO1˜V.sub.EAOm of the plurality of error amplifiers 121_1˜121_m.

[0029] In the following, the duty cycles D.sub.P, D.sub.N, D.sub.1˜D.sub.m are also referred as the charging duty cycle D.sub.P, the discharge duty cycle D.sub.N, the first duty cycle to the m-th duty cycle D.sub.1˜D.sub.m of a first group; and the duty cycles D′.sub.P, D′.sub.N, D′.sub.1˜D′.sub.m are also referred as the charging duty cycle D.sub.P, the discharge duty cycle D′.sub.N, the first duty cycle to the m-th duty cycle D′.sub.1˜D′.sub.m of a second group.

[0030] The oscillator 126 generates the clock signal T.sub.CK to the energy generating circuit 124 and the logic control and gate driver 130.

[0031] The zero current detector 127 is coupled to the inductor L1 to detect the inductor current I.sub.L. When the zero current detector 127 detects that the inductor current I.sub.L reaches zero current, the zero current detector 127 outputs a zero current signal ZC.

[0032] The logic control and gate driver 130 is coupled to the power stage 110 and the control circuit 120. The logic control and gate driver 130 generates a plurality of switch control signals S.sub.P, S.sub.N, S.sub.R, S.sub.1, S.sub.2, . . . , S.sub.m based on the duty cycles D.sub.P, D.sub.N, D.sub.1˜D.sub.m, D′.sub.P, D′.sub.N, D′.sub.1˜D′.sub.m. The switch control signals S.sub.P, S.sub.N, S.sub.R, S.sub.1, S.sub.2, . . . , S.sub.m are used to control the switches SWP, SWN, SWR, SW1, SW2, . . . , SWm, respectively.

[0033] FIG. 2 shows a circuit diagram of the energy generating circuit according to one example of the application. As shown in FIG. 2, the energy generating circuit 124 according to one example of the application includes an adder 201, a multiplexer 203, a comparator 205, a phase detector 207, a charge pump and filter 209 and a capacitor C.sub.P. For simplicity, in the following, m=4 is taken as an example, but the application is not limited by this.

[0034] The adder 201 adds a plurality of voltages V.sub.C1, V.sub.C2, V.sub.C3 and V.sub.C4 and an adjustment voltage V.sub.CP_adj to generate a control voltage V.sub.CP. For example but not limited by, V.sub.CP=k.sub.1*V.sub.C1+k.sub.2*V.sub.C2+k.sub.3*V.sub.C3+k.sub.4*V.sub.C4−V.sub.CP_adj, wherein k.sub.1, k.sub.2, . . . k.sub.4 are all positive values. The voltages V.sub.C1, V.sub.C2, V.sub.C3 and V.sub.C4 are generated by the energy distributing circuits 125_1˜125_4, respectively. Still further, the voltages V.sub.C1, V.sub.C2, V.sub.C3 and V.sub.C4 are corresponding to the plurality of error amplifier output voltages V.sub.EAO1˜V.sub.EAO4.

[0035] The multiplexer 203 is controlled by the switch control signal S.sub.P. When the switch control signal S.sub.P is 0, the multiplexer 203 outputs 0V (GND); and when the switch control signal S.sub.P is 1, the multiplexer 203 outputs the control current I.sub.S1.

[0036] The comparator 205 compares the control voltage V.sub.CP with the voltage of the capacitor C.sub.P to generate the duty cycle D.sub.P.

[0037] The phase detector 207 detects phases of the clock signal T.sub.CK and the last duty cycle D.sub.4 (i.e. the last duty cycle D.sub.m). The charge pump and filter 209 generates the adjustment voltage V.sub.CP_adj based on the output of the phase detector 207.

[0038] The capacitor C.sub.P is coupled between the output of the multiplexer 203 and the ground terminal GND. The capacitor C.sub.P is charged by the output of the multiplexer 203 (or said the capacitor C.sub.P is charged by the control current Isi).

[0039] By the circuit configuration in FIG. 2, the energy generating circuit 124 generates the duty cycle D.sub.P and the adjustment voltage V.sub.CP_adj.

[0040] FIG. 3 shows a circuit diagram of the energy distributing circuit according to one example of the application. The energy distributing circuit 125_x (x=1˜m) according to one example of the application includes a comparator 301, a multiplexer 303, a multiplexer 307, a capacitor C.sub.X and a comparator 309.

[0041] The comparator 301 compares the error amplifier output voltage V.sub.EAOx of the error amplifier 121_x with a reference voltage V.sub.PSM to generate a pulse-skip mode (PSM) signal PSMx. For example but not limited by, the PSM signal PSMx is logic 0 when the error amplifier output voltage V.sub.EAOx of the error amplifier 121_x is higher than the reference voltage V.sub.PSM, and vice versa. When the PSM signal PSMx is logic 1, the corresponding channel enters the PSM mode; and when the PSM signal PSMx is logic 0, the corresponding channel is at the EA mode. When the EA output of a channel is lower than the reference voltage V.sub.PSM, this channel does not need energy for the next clock cycle and thus this channel enters the PSM mode.

[0042] The multiplexer 303 is controlled by the PSM signal PSMx from the comparator 301. The multiplexer 303 outputs among the error amplifier output voltage V.sub.EAOx of the error amplifier 121_x and the reference voltage V.sub.PSM as the (control) voltage V.sub.CX. For example but not limited by, when the PSM signal PSMx is logic 0, the multiplexer 303 outputs the error amplifier output voltage V.sub.EAOx of the error amplifier 121_x as the voltage V.sub.CX; and when the PSM signal PSMx is logic 1, the multiplexer 303 outputs the reference voltage V.sub.PSM as the voltage V.sub.CX. The voltage V.sub.CX indicates energy required by the channel.

[0043] The multiplexer 307 is controlled by the switch control signal S.sub.X. The multiplexer 307 outputs among the control current I.sub.S2 or GND. For example but not limited by, when the switch control signal S.sub.X is logic 1, the multiplexer 307 outputs the control current I.sub.S2; and when the switch control signal S.sub.X is logic 0, the multiplexer 307 outputs GND (0V). The output of the multiplexer 307 charges the capacitor C.sub.X.

[0044] The comparator 309 compares the voltage V.sub.CX with the voltage of the capacitor C.sub.X to generate the duty cycle D.sub.X. For example but not limited by, when the voltage V.sub.CX is higher than the voltage of the capacitor C.sub.X, the duty cycle D.sub.X is logic 1 (i.e. ON); and when the voltage V.sub.CX is lower than the voltage of the capacitor C.sub.X, the duty cycle D.sub.X is logic 0.

[0045] The capacitor C.sub.X is coupled between the output of the multiplexer 307 and the ground terminal GND. The capacitor C.sub.X is charged by the output of the multiplexer 307.

[0046] Still further, as shown in FIG. 3, the output D.sub.cx of the comparator 122_x is also input into the control unit 123 and the multiplexer 131_x of the logic control and gate driver 130. Based on the output D.sub.cx of the comparator 122_x and the control current Is, the control unit 123 performs peak current control function to generate the duty cycle D′.sub.x.

[0047] The multiplexer 131_x of the logic control and gate driver 130 is controlled by the PCC signal PCC to select among the duty cycle D.sub.x or the duty cycle D′.sub.x as the switch control signal S.sub.x wherein the logic control and gate driver 130 includes a plurality of multiplexer 131_1˜131_m (not shows). For example but not limited by, when the PCC signal PCC is logic 0, the multiplexer 131_x selects the duty cycle D.sub.x as the switch control signal S.sub.x; and when the PCC signal PCC is logic 1, the multiplexer 131_x selects the duty cycle D′.sub.x as the switch control signal S.sub.x.

[0048] In one embodiment of the application, the control unit 123 also performs peak current control function to generate the duty cycles D′.sub.P and D′.sub.N, and details are omitted here.

[0049] In one embodiment of the application, when all channels enter the PSM mode (that is, when the signals PSM.sub.1˜PSM.sub.m are all logic 1), the PCC signal PCC is logic 1 which indicates that the SIMO power converter 100 enters the PCC and PSM mode, otherwise, the PCC signal PCC is logic 0 which indicates that the SIMO power converter 100 is at the OPDC and EA mode.

[0050] When the PCC signal PCC is logic 0, the switch control signal S.sub.X depends on the voltage V.sub.CX (i.e. the ON-time of the switch SW.sub.X depends on the voltage V.sub.CX); and when the PCC signal PCC is logic 1, the switch control signal S.sub.X depends on the peak current control logic (i.e. the ON-time of the switch SW.sub.X depends on the peak current control logic, or said the ON-time of the switch SW.sub.X is controlled by the peak current control logic). In one embodiment of the application, the energy distribution circuits 125_1˜125_m have PSM and PCC (peak current control) functions.

[0051] FIG. 4A shows imperfect balance and FIG. 4B shows perfect balance in one embodiment of the application. As shown in FIG. 4A, during the duty cycle D.sub.P, the inductor L1 is charged; and during the duty cycle D.sub.N, the inductor L1 is discharged. Further, during the duty cycle D.sub.1, the switch SW1 is turned on to generate the output voltage V.sub.O1; during the duty cycle D.sub.2, the switch SW2 is turned on to generate the output voltage V.sub.O2; during the duty cycle D.sub.3, the switch SW3 is turned on to generate the output voltage V.sub.O3; and during the duty cycle D.sub.4, the switch SW4 is turned on to generate the output voltage V.sub.O4. However, in FIG. 4A, after end of the duty cycle D.sub.4, there is still surplus energy remained in the inductor L1. Thus, FIG. 4A shows imperfect balance between the input energy and the output energy.

[0052] To remove the surplus energy in the inductor L1 to the last output V.sub.Om (i.e. V.sub.O4), the duty cycle D.sub.P is fined tuned to be smaller. After fine tune of the duty cycle D.sub.P, perfect balance between the input energy and the output energy is achieved, as shown in FIG. 4B. How to tune the duty cycle D.sub.P to achieve perfect balance is described as follows.

[0053] FIG. 4A and FIG. 4B also show OPDC (Ordered Power Distributive Control) control scheme at Continuous-Current-Mode (CCM) mode. The oscillator 126 outputs a clock signal with period T.sub.CK. In the OPDC mode, at least one channel needs energy for every clock cycle continuously. The control circuit 120 is configured to control timing and charging current of the inductor L1 through activating one of the input switches SWP, SWN and discharging of the inductor L1 through activating one of the output switches SW1˜SWm sequentially.

[0054] In Continuous-Current-Mode (CCM) OPDC, the SIMO power converter 100 is operated at the OPDC mode with that the inductor current I.sub.L is not discharged to zero value. In Discontinuous-Current-Mode (DCM) OPDC, the SIMO power converter 100 is operated at OPDC with that the inductor current I.sub.L is discharged to zero value. Still further, in CCM OPDC with Pulse-Skip-Mode (PSM), the SIMO power converter 100 is operated at CCM OPDC with one or more channels do not need energy for every clock cycle. In DCM OPDC with PSM, the SIMO power converter 100 is operated at DCM OPDC with one or more channels do not need energy for every clock cycle.

[0055] Now how to achieve perfect balance between the input energy and the output energy by tuning the duty cycle D.sub.P in one embodiment of the application is described.

[0056] Energy E.sub.OX delivered to the output voltage V.sub.OX in the corresponding energy distributing duty cycle D.sub.X through the switch SW.sub.X is expressed as following equation (1):

E.sub.Ox=∫.sub.0.sup.D.sup.x.sup.TI.sub.LV.sub.OP.Math.dt  (1)

[0057] In the equation (1), I.sub.L refers to the inductor current and the clock period is noted by T=T.sub.CK, wherein x=1, 2, . . . , m. The following description takes m=4 for the following discussions.

[0058] In the energy distributing circuit 125_1˜125_m, the corresponding capacitor C.sub.X is charged by I.sub.S2=V.sub.OX*I.sub.L/k with the duty cycle D.sub.X. The amount of charge delivered to the capacitor C.sub.X in the time duration is calculated as the equation (2):

Q.sub.Ox=∫.sub.0.sup.D.sup.x.sup.TI.sub.S.Math.dt=∫.sub.0.sup.D.sup.x.sup.TI.sub.L/k.Math.dt=C.sub.xV.sub.Cx  (2)

[0059] In the equation (2), V.sub.CX is the output voltage of the error amplifier 121_x (when the channel does not enter PSM).

[0060] The equations (1) and (2) are combined into the equation (3):

E.sub.ox=k×C.sub.x×V.sub.cx  (3)

[0061] The energy Eox depends on the corresponding error amplifier output.

[0062] Total energy delivered to the output loads V.sub.O1˜V.sub.Om are expressed equation (5):

E.sub.OT=Σ.sub.x=1.sup.m∫.sub.0.sup.D.sup.x.sup.TI.sub.LV.sub.Ox.Math.dt

E.sub.OT=kΣ.sub.x=1.sup.mC.sub.xV.sub.Cx  (5)

[0063] In the energy generation circuit 124, the corresponding capacitor C.sub.P is charged by the current I.sub.S1, wherein I.sub.S1=V.sub.IN*I.sub.L/k with the duty cycle D.sub.P. The total energy transferred from the input voltage V.sub.IN is expressed as the following equation (6):

E.sub.IT=∫.sub.0.sup.D.sup.P.sup.TI.sub.LV.sub.IN.Math.dt=kC.sub.PV.sub.CP  (6)

[0064] In steady state, E.sub.OT=E.sub.IT, then the following equation (7) is got:

[00001]$\begin{array}{cc}{V}_{\mathrm{CP}}={.Math.}_{x=1}^{4}k\frac{C_x}{C_P}{V}_{\mathrm{Cx}}={.Math.}_{x=1}^4{k}_x{V}_{\mathrm{Cx}}=k_1{V}_{C1}+k_2{V}_{C2}+k_3{V}_{C3}+k_4{V}_{C4}& \left(7\right)\end{array}$

[0065] In the equation (7), k.sub.1, k.sub.2, . . . , k.sub.4 are all positive values.

[0066] In real circuits, the total energy transferred from the input voltage V.sub.IN by controlling the switch S.sub.P with the duty cycle D.sub.P is hard to be exactly equal to the total energy delivered to all the loads by controlling the switch S.sub.X with the duty cycle D.sub.X even the equation (7) is used to decide the duty cycle D.sub.P due to circuit nonideality and transient response.

[0067] Therefore, the duty cycle of the last switch S.sub.4 (m=4) will be decided by the equation (8) which means all the remained energy is delivered to the last output V.sub.O4.

S.sub.4=T.sub.CK−(D.sub.1+D.sub.2+D.sub.3)  (8)

[0068] To solve this issue, the control voltage V.sub.CP is modified as the equation (9):

V.sub.CP=Σ.sub.i=1.sup.4k.sub.i.Math.V.sub.Ci−V.sub.CP_adj  (9)

[0069] The energy generating circuit 124 generating the adjustment voltage V.sub.CP_adj is designed as:

[0070] (1) If T.sub.CK>D.sub.1+D.sub.2+D.sub.3+D.sub.4, then the adjustment voltage V.sub.CP_adj is adjusted a little larger to make the control voltage V.sub.CP smaller. Thus, the duty cycle D.sub.P is smaller.

[0071] (2) If T.sub.CK<D.sub.1+D.sub.2+D.sub.3+D.sub.4, then the adjustment voltage V.sub.CP_adj is adjusted a little smaller to make the control voltage V.sub.CP larger. Thus, the duty cycle D.sub.P is larger.

[0072] (3) If T.sub.CK=D.sub.1+D.sub.2+D.sub.3+D.sub.4, then the control voltage V.sub.CP is kept at the same value. Thus, the perfect balance is achieved.

[0073] Thus, in one embodiment of the application, by fine tuning the duty cycle D.sub.P, perfect balance between the input energy and the output energy is achieved and there is theoretically no cross regulation.

[0074] FIG. 5 shows DCM OPDC with three channels in PSM according to one embodiment of the application. As shown in FIG. 5, in the first clock cycle, the channels V.sub.O1 and V.sub.O2 need energy; in the second clock cycle, only the channel V.sub.O2 needs energy, and so on. Thus, in one embodiment of the application, in OPDC with PSM, the duty cycle D.sub.2 (S.sub.2) is decided by the corresponding error amplifier output V.sub.C2; and the duty cycles D.sub.1, D.sub.3 and D.sub.4 (S.sub.1, S.sub.3 and S.sub.4) are all in minimum energy control. For periods those only the output voltage (or the output channel) V.sub.O2 requires energy (for example, in the second clock cycle and in sixth clock cycle), the duty cycle D.sub.P (S.sub.P) generates energy only for the output voltage (or the output channel) V.sub.O2. For periods those the output voltages (or the output channels) V.sub.O1, V.sub.O3 or V.sub.O4 also need energy, the duty cycle D.sub.P (S.sub.P) generates energy for the output voltages (or the output channels) V.sub.O2 and V.sub.O1, V.sub.O3 or V.sub.O4. For example, in the first clock cycle, V.sub.O1 also needs energy, the duty cycle D.sub.P (S.sub.P) generates energy for the output voltages (or the output channels) V.sub.O2 and V.sub.O1. Thus, in the application, the duty cycles D.sub.P and D′.sub.P are also referred as the energy generation duty cycles; and the duty cycles D.sub.1˜D.sub.m and D′.sub.1˜D′.sub.m are also referred as the energy distribution duty cycles.

[0075] In one embodiment of the application, the ripple voltage of the output voltage may be controlled as a specified value. FIG. 6 shows inductor peak current in one embodiment of the application. Assume that output ripple voltage V.sub.O_ripple=ΔV.sub.O, then charge stored in the corresponding capacitor is presented as the following equation (10):

[00002]$\begin{array}{cc}\Delta Q=C_O\Delta V_O=\frac{1}{2}{I}_{\mathrm{PK}}\left(T_{\mathrm{ON}}+T_{\mathrm{OFF}}\right)=\frac{1}{2}{I}_{\mathrm{PK}}^{2}L\frac{V_I}{V_O\left(V_I-V_O\right)}& \left(10\right)\end{array}$

[0076] Thus, the inductor peak current I.sub.PK is expressed in the following equation (11):

[00003]$\begin{array}{cc}{I}_{\mathrm{PK}}=\sqrt{\frac{2C_O}{L}\times \frac{V_O\left(V_I-V_O\right)}{V_I}\times \Delta V_O}& \left(11\right)\end{array}$

[0077] Thus, in one embodiment of the application, when the on time is controlled by inductor peak current I.sub.PK as (11), the output ripple voltage may be also controlled as a specified value for all channels. In one embodiment of the application, all channels have the same output ripple voltage although the channels may have different output voltages.

[0078] In one embodiment of the application, the control unit 123 of the control circuit 120 of the SIMO power converter 100 has peak current control mode and sleep mode.

[0079] If a channel does not need energy for every clock cycle (i.e. when the EA output of the channel is lower than the reference voltage V.sub.PSM), then this channel enters PSM mode, under control of the control circuit 120. If all channels enter PSM mode, the SIMO power converter 100 enters Peak Current Control (PCC), under control of the control circuit 120.

[0080] The energy generating period in PCC mode is decided by the inductor current I.sub.L achieving to a specified peak current value or a constant time period. If the specified peak current value is calculated as the equation (11), the output voltage ripple can be controlled as constant value for different input and output voltages.

[0081] In PCC, when no channel needs energy and the inductor current I.sub.L is discharged to zero, the SIMO power converter 100 enters the sleep mode. In the sleep mode, the OSC 126 and the EAs 121_1˜121_m are all turned off to reduce quiescent current. In the sleep mode, if any channel needs energy, the OSC 126 is enabled, and the SIMO power converter 100 goes back to the PCC mode.

[0082] When the SIMO power converter 100 is in PCC, if any channel needs energy continuously for N clock cycles (N being larger or equal to 2 and N being a positive integer), then the SIMO power converter 100 goes back to the OPDC mode.

[0083] In one embodiment of the application, the SIMO power converter 100 has OPDC with mixed EA mode and PSM mode.

[0084] EA Mode while PSM=0

[0085] In the EA mode, the channel requires energy for every clock cycle. The duty cycles (i.e. D.sub.1˜D.sub.m) of energy distributing are decided by V.sub.CX=V.sub.EAOx. If the error amplifier output voltage V.sub.EAOx goes lower than the reference V.sub.PSM, this channel enters the PSM mode as the PSM signal PSMx goes high.

[0086] Peak Current Control (PCC) Mode

[0087] When all channels enter PSM, the SIMO power converter 100 enters Peak Current Control (PCC) mode, under control of the control circuit 120. For a SIMO power converter in the PCC mode, when any channel needs energy continuously more than N clock cycles (N is a positive integer, for example but not limited by, N≥2), the SIMO power converter goes back to OPDC mode; and on the other hand, for the SIMO power converter in the PCC mode, when no channel needs energy continuously more than N clock cycles, the channel keeps in the PCC mode.

[0088] For the SIMO power converter in the PCC mode, energy transferring of each channel is triggered by D.sub.CX which is a comparator output by comparing the output voltage V.sub.OX and the corresponding reference voltage V.sub.Rx of this channel. D.sub.CX=1 means the channel X requiring energy; and D.sub.CX=0 means the channel X having enough energy.

[0089] While the SIMO power converter 100 is still in OPDC, the duty cycles of energy distributing are decided by V.sub.CX=V.sub.PSM. If the SIMO power converter 100 is in PCC, the on-time of energy generating duty cycle (i.e. D.sub.P) is decided by a constant time period. This constant time period is defined as a time period that the inductor current achieving a specified peak current value or others.

[0090] If the on-time of the duty cycle or the peak current value is larger, then the output voltage has larger ripple and the output switches have lower switching frequency, which result lower switching loss.

[0091] For the SIMO power converter in the PCC mode, the error amplifiers of all channels are turned off due to all channels are controlled by the comparators instead of by the error amplifiers. In this case, the error amplifiers (EAs) will be turned on again while all channels are going back to EA Mode.

[0092] FIG. 7 shows signal diagram of the SIMO power converter 100 in one embodiment of the application. As shown in FIG. 7, before the timing T1, the SIMO power converter 100 is at OPDC and EA mode. At the timing T1, the output voltage V.sub.Cx (i.e. V.sub.EAOx) of the error amplifier 121_x is lower than the reference voltage V.sub.PSM, then the PSMx signal of this channel goes logic high. Also, it is judged that whether all channels enter the PSM mode (i.e. it is judged whether all PSMx signals of all channels go logic high). If all channels enter the PSM mode, then the SIMO power converter 100 enters the PCC and PSM mode at the timing T2. When the SIMO power converter 100 is operated in the PCC and PSM mode, if no channel needs energy and the inductor current is discharged to zero, the SIMO enters the sleep mode. In the sleep mode, the control unit 123 of the control circuit 120 outputs the sleep mode control signal SM to the oscillator 126 and the EAs 121_1˜121_m to turn off the oscillator 126 and the EAs 121_1˜121_m.

[0093] During the timing T3, the inductor current I.sub.L keeps above the zero current (i.e. during the timing T3, the ZC signal keeps low) for continuously more than (or equal than) N clock cycles. Thus, it is determined that at least one of the channels needs energy continuously more than (or equal than) N clock cycles and thus the channel(s) goes back to the EA mode to turn on the corresponding EA 121_x of this channel.

[0094] At the timing T4, the SIMO power converter 100 goes back to the OPDC and EA mode to provide the required energy to the channel(s) in the EA mode. I.sub.RX refers to the load current on the load Loadx.

[0095] In one embodiment of the application, the SIMO DC-DC converter combines OPDC and PCC control. Also, the energy generating period (duty cycle D.sub.P) under PCC control mode is decided by a specified inductor peak current or a constant time period. Also, when the energy distributing circuit operates at the EA mode, the energy distributing duty cycles D.sub.1˜D.sub.m under the EA mode is decided by the EA output and the sensed inductor current of the corresponding channel; and when the EA output of a channel is lower than a predetermined voltage level (V.sub.PSM), this channel does not need energy for the next clock cycle and thus enters a PSM mode.

[0096] For a channel in the PSM mode, energy distributing of this channel is triggered by a comparator output of the comparator 301, which compares EA output with the predetermined voltage level (V.sub.PSM).

[0097] In case of the comparator (301) comparing the EA voltage output and reference voltage of this channel, the EA may be turned off at the PSM mode.

[0098] In the PCC mode, if any channel requires energy continuously for N clock cycle where for example but not limited by, N is ≥2, the SIMO power converter goes back to the OPDC mode.

[0099] If there is at least one channel operated at EA mode, the SIMO operates at the OPDC; and the energy generating duty (D.sub.P) is in response of a sum of all control voltages (V.sub.C1˜V.sub.Cm) (as shown in FIG. 2). The control voltage is the corresponding error amplifier output (V.sub.EAOx) at the EA mode and the control voltage is the predetermined voltage (V.sub.PSM) at the PSM mode.

[0100] When all channels operate at the PSM mode (all PSMx are 1) or there are a predetermined successive cycles of zero inductor current signal (zero current signal from the ZCD 127) detected, the SIMO power converter enters the PCC mode. In PCC mode, if no channel needs energy and the inductor current discharged to zero, the SIMO enters the sleep mode. In the sleep mode, the OSC and all the EAs are turned off to reduce quiescent current. In the sleep mode, if any channel needs energy, the OSC is enabled, and the SIMO enters the PCC mode. In the PCC mode, if any channel enters to the EA mode, the SIMO enters the OPDC mode to sequentially provide energy to the EA-mode channel(s).

[0101] As described above, in one embodiment of the application, the oscillators and the EAs are turned off when the SIMO power converter is operated in PCC and PSM mode. Thus, in one embodiment of the application, the SIMO power converter has good efficiency at light load.

[0102] The application gains some of the limited space in the space-constrained electronic products back by using the single-inductor multiple-output (SIMO) power converter architecture. The SIMO architecture, along with the regulator's low quiescent current, enables to extend battery life for space-constrained electronic products.

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.