Semiconductor device and driving method thereof
09640106 ยท 2017-05-02
Assignee
Inventors
Cpc classification
G09G2310/0251
PHYSICS
G09G2310/0262
PHYSICS
G09G2300/0809
PHYSICS
G09G3/3233
PHYSICS
G09G2320/0223
PHYSICS
G09G2310/0275
PHYSICS
G09G2300/0842
PHYSICS
G09G3/325
PHYSICS
International classification
G09G3/3233
PHYSICS
G09G3/325
PHYSICS
Abstract
The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current is inputted to perform the set operation. A predetermined potential can be obtained rapidly as the precharge operation is performed before the set operation. The predetermined potential is approximately equal to a potential after completing the set operation. Therefore, the set operation can be rapidly performed and a write operation of a signal current can be rapidly performed. By using two transistors, a gate width W can be long or a gate length L can be short in the precharge operation or the gate width W can be short and the gate length L can be long in the set operation.
Claims
1. A semiconductor device comprising: a load; a first current source; a second current source; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a capacitor; and a power source line, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the power source line, wherein a gate of the first transistor is directly connected to one of a source and a drain of the sixth transistor, wherein a gate of the second transistor is directly connected to the other of the source and the drain of the sixth transistor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the load, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor is electrically connected to the first current source, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fifth transistor is electrically connected to the second current source, wherein one of electrodes of the capacitor is electrically connected to a gate of the first transistor, wherein the power source line is separated from the first current source by the first transistor, and wherein the first transistor and the second transistor are n-type transistors.
2. The semiconductor device according to claim 1, wherein the load is a display element.
3. The semiconductor device according to claim 1, wherein the load is an EL element.
4. The semiconductor device according to claim 1, wherein the load is a signal line.
5. The semiconductor device according to claim 1, wherein at least one of the first current source and the second current source is a constant current source.
6. The semiconductor device according to claim 1 further comprising a sixth transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor.
7. The semiconductor device according to claim 6, wherein the other of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the first transistor.
8. The semiconductor device according to claim 1, wherein the other of electrodes of the capacitor is electrically connected to the other of the source and the drain of the second transistor.
9. A semiconductor device comprising: a load; a first current source; a second current source; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and a capacitor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein a gate of the first transistor is directly connected to one of a source and a drain of the seventh transistor, wherein a gate of the second transistor is directly connected to the other of the source and the drain of the seventh transistor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the load, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fourth transistor is electrically connected to the first current source, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor and the other of the source and the drain of the fifth transistor is electrically connected to the second current source, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, wherein one of electrodes of the capacitor is electrically connected to the gate of the first transistor, and wherein the first transistor and the second transistor are n-type transistors.
10. The semiconductor device according to claim 9, wherein the load is a display element.
11. The semiconductor device according to claim 9, wherein the load is an EL element.
12. The semiconductor device according to claim 9, wherein the load is a signal line.
13. The semiconductor device according to claim 9, wherein at least one of the first current source and the second current source is a constant current source.
14. The semiconductor device according to claim 9 further comprising a seventh transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor.
15. The semiconductor device according to claim 14, wherein the other of the source and the drain of the seventh transistor is electrically connected to the other of the source and the drain of the first transistor.
16. The semiconductor device according to claim 9, wherein the other of electrodes of the capacitor is electrically connected to the other of the source and the drain of the second transistor.
17. A semiconductor device comprising: a load; a first current source; a second current source; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and a capacitor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the load, wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the fourth transistor is electrically connected to the first current source, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the fifth transistor is electrically connected to the second current source, wherein one of a source and a drain of the sixth transistor is directly connected to a gate of the second transistor and one of a source and a drain of the seventh transistor, wherein the other of the source and the drain of the seventh transistor is directly connected to a gate of the first transistor, wherein one of electrodes of the capacitor is electrically connected to the gate of the first transistor, and wherein the first transistor and the second transistor are n-type transistors.
18. The semiconductor device according to claim 17, wherein the load is a display element.
19. The semiconductor device according to claim 17, wherein the load is an EL element.
20. The semiconductor device according to claim 17, wherein the load is a signal line.
21. The semiconductor device according to claim 17, wherein at least one of the first current source and the second current source is a constant current source.
22. The semiconductor device according to claim 17 further comprising an eighth transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor.
23. The semiconductor device according to claim 22, wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor.
24. The semiconductor device according to claim 17, wherein the other of electrodes of the capacitor is electrically connected to the other of the source and the drain of the second transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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BEST MODE FOR CARRYING OUT THE INVENTION
(80) Although the present invention will be described by way of example with reference to the accompanying drawings, it is to be understood that various changes and modifications will be apparent to those skilled in the art. Therefore, unless such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.
(81) [Embodiment Mode 1]
(82) The invention can be applied not only to a pixel having a light emitting element such as an EL element, but to various analog circuits having a current source. First, in this embodiment mode, a basic principle of the invention is described.
(83) First,
(84) A gate terminal of the current source transistor 101 is connected to one terminal of a capacitor 104. The other terminal of the capacitor 104 is connected to a wiring 111. Therefore, it is possible to hold a potential of the gate terminal of the current source transistor 101. Further, the gate terminal and a drain terminal of the current source transistor 101 are connected to each other via a switch 105 and the capacitor 104 can be controlled to hold a charge by ON/OFF of the switch 105. The current source transistor 101 and a wiring 112 are connected to each other via a basic current source 108 and a switch 106. In parallel with the aforementioned, the current source transistor 101 and a wiring 116 are connected to a second basic current source 115 via a switch 114. Similarly, in parallel with the aforementioned, the current source transistor 101 and a wiring 113 are connected to each other via a load 109 and a switch 107.
(85) Further, the switching transistor 102 is connected to a means for switching to operate as a current source (or a part of it) or to operate not to flow a current between a source and drain thereof (or to operate as a switch) according to the circumstance. Here, the case where the switching transistor 102 operates as a current source (or a part of it) is referred to as a current source operation. Moreover, the case where the switching transistor 102 operates not to flow a current between the source and drain thereof (or the case of operating as a switch) or the case of operating with a small source-drain voltage is referred to as a short-circuit operation.
(86) In order to perform the current source operation and the short-circuit operation to the switching transistor 102, various configurations can be employed.
(87) In this embodiment mode,
(88) By using a circuit having such a configuration as
(89) The operation of
(90) Next, the switches 105 and 106 are turned ON and the switches 103, 107, and 114 are turned OFF as shown in
(91) When the current flowing between the source and drain of the multi-gate transistor and the current Ib1 of the basic current source 108 become equal, a current stops flowing to the capacitor 104. That is, a steady state is obtained. A potential of the gate terminal at that time is accumulated in the capacitor 104. That is, a voltage required to flow the current Ib1 between the source and drain of the multi-gate transistor (current source transistor 101 and the switching transistor 102) is applied to the gate terminal. The aforementioned operation corresponds to the set operation. At that time, the switching transistor 102 performs the current source operation.
(92) Note that a charge accumulated in the capacitor 104, that is a potential of the gate terminal of the current source transistor 101 is set to be approximately equal voltage in the precharge operation and the set operation by appropriately setting the current Ib1 of the basic current source 108, the current Ib2 of the second basic current source 115, and transistor size (gate width, gate length and the like) of the current source transistor 101 and the switching transistor 102.
(93) Then, in the case where the current Ib2 of the second basic current source 115 has a larger current value than the current Ib1 of the basic current source 108, the capacitor 104 can be charged rapidly by the precharge operation and the steady state can be obtained. After that, even when the current Ib1 of the basic current source 108 is small in the set operation, the steady state can be obtained rapidly. This is because the capacitor 104 is almost charged by the precharge operation.
(94) Next, the switches 103, 105, 106, and 114 are turned OFF and the switch 107 is turned ON as shown in
(95) In this manner, by controlling ON/OFF of the switch 103, a current flowing in the precharge operation can be large, which enables the steady state to be obtained rapidly. That is to say, an effect of a load which is parasitic on a wiring through which a current flows (wiring resistance, intersection capacitance and the like) is lessened and the steady state can be obtained rapidly. At that time, almost the same state is already obtained as that in the set operation. Therefore, the steady state can be rapidly obtained in the set operation after the precharge operation.
(96) Therefore, for example, provided that the load 109 is an EL element, a signal can be written rapidly when writing a signal in the case where the EL element emits light in a low gray scale, that is the case where a current value is small in the set operation.
(97) Next, a change of a current and a voltage in the aforementioned operation is shown in
(98) An operation as shown in
(99) In
(100) Now, a condition whereby the voltage accumulated in the capacitor 104, that is the potential of the gate terminal of the current source transistor 101 becomes approximately equal in the precharge operation and the set operation is described. First, it is assumed that a gate width of the current source transistor 101 is Wa, a gate length thereof is La, and a gate width of the switching transistor 102 is Wb, and a gate length thereof is Lb. Note that Wa=Wb is satisfied here for simplicity. It is assumed that the current flowing in the set operation (the current Ib of the basic current source 108 in
(101) Generally, a current flowing between a source and drain of a transistor is in proportion to a ratio of a channel width and a channel length: W/L. Therefore, a ratio of a gate width and a gate length: Wa/La in the precharge operation and a ratio of a gate width and a gate length: Wa/(La+Lb) in the set operation are considered. Then, the current Ib1 of the basic current source 108 times A equals to the current Ib2 of the second basic current source 115, therefore, each value may be set so that Wa/(La+Lb) times A equals to Wa/La. Accordingly, provided that current characteristics of the current source transistor 101 and the switching transistor 102 are approximately the same, a potential of the gate terminal of the current source transistor 101 becomes approximately equal to the potential in the time T2b.
(102) In
(103) Note that in
(104) Further, in
(105) Note that the load 109 may be anything. It may be an element such as a resistor, a transistor, an EL element, or a current source circuit formed by a transistor, a capacitor, a switch and the like. It may be a signal line or a signal line and a pixel connected to it. The pixel may include any kind of display element such as an EL element or an element used in an FED.
(106) Note that the capacitor 104 can be substituted by gate capacitance of the current source transistor 101, the switching transistor 102 and the like. In that case, the capacitor 104 can be omitted.
(107) Note that the wiring 110 and the wiring 111 are supplied with a power supply on the high potential side Vdd, however, the invention is not limited to this. Each wring may have the same potential or a different potential. The wiring 111 is only required to be capable of storing a charge of the capacitor 104. Further, the wiring 110 or the wiring 111 is not required to keep the same potential constantly. They may have different potentials between the set operation and the output operation as long as they operate normally.
(108) Note that the wiring 113, the wiring 112, and the wiring 116 are supplied with a power supply on the low potential side Vss, however, the invention is not limited to this. Each wring may have the same potential or a different potential. The wiring 112, the wiring 113, and the wiring 116 are not required to keep the same potentials constantly. They may have different potentials between the set operation and the output operation as long as they operate normally.
(109) Note that the capacitor 104 is connected to the gate terminal of the current source transistor 101 and the wiring 111, however, the invention is not limited to this. It is most desirable that the capacitor 104 be connected to the gate terminal and the source terminal of the current source transistor 101. This is because the operation of a transistor is not easily influenced by other effects (an effect of a voltage drop and the like due to a wiring resistance and the like) as long as a voltage is maintained between the gate terminal and the source terminal since the operation of the transistor is determined by a gate-source voltage. Provided that the capacitor 104 is disposed between the gate terminal of the current source transistor 101 and another wiring, a potential of the gate terminal of the current source transistor 101 may change depending on the level of voltage drop of that another wiring.
(110) Note that the current source transistor 101 and the switching transistor 102 operate as a multi-gate transistor in the current source operation, therefore, these transistors preferably have the same polarity (have the same conductivity).
(111) Note that the current source transistor 101 and the switching transistor 102 operate as a multi-gate transistor in the current source operation, however, a gate width W of each transistor may be either the same or different. Similarly, a gate length L may be either the same or different. However, the gate width W is preferably the same since the gate width W can be considered to be the same as a typical multi-gate transistor. As the gate length L of the switching transistor 102 becomes longer, a current flowing in the set operation and the output operation becomes smaller. Therefore, an appropriate design may be carried out according to the circumstance.
(112) Such switches as 103, 105, 106, 107, and 114 may be any switch such as an electrical switch or a mechanical switch. It may be anything as far as it can control a current flow. It may be a transistor, a diode, or a logic circuit configured with them. Therefore, in the case of applying a transistor as a switch, a polarity (conductivity) thereof is not particularly limited because it operates just as a switch. However, when an off-current is preferred to be small, a transistor of a polarity with a small off-current is favorably used. For example, a transistor which provides an LDD region and the like have a small off-current. Further, it is desirable that an n-channel type transistor be employed when a potential of a source terminal of the transistor as a switch is closer to the power supply on the low potential side (Vss, Vgnd, 0V and the like), and a p-channel type transistor be employed when the potential of the source terminal is closer to the power supply on the high potential side (Vdd and the like). This helps the switch operate efficiently as an absolute value of a gate-source voltage of the transistor can be increased. It is to be noted that a CMOS type switch can also be applied by using both n-channel type and p-channel type transistors.
(113) Note that
(114) For example, such switches as 103, 105, 106, 107, and 114 may be disposed anywhere as long as it can control ON/OFF of a target current. Specifically, the switch 107 which controls a current flowing to the load 109 is only required to be disposed to be in series to the load 109. Similarly, the switches 106 and 114 which control a current flowing to the basic current source 108 and the second basic current source 115 are only required to be disposed in series to the basic current source 108. Further, the switch 103 which controls a current flowing to the switching transistor 102 is only required to be disposed in parallel to the switching transistor 102. The switch 105 is only required to be disposed so as to control a charge in the capacitor 104.
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(116) Next,
(117) Next,
(118) Here, the circuit in
(119) In
(120) Based on the aforementioned, the arrangement of the current source transistor 101 and the switching transistor 102 may be designed according to circumstances. For example, in the case where an absolute value of a gate-source voltage of the multi-gate transistor (the current source transistor 101 and the switching transistor 102) is preferably small when the precharge operation changes to the set operation, the configuration shown in
(121) As an example, there is a case where the current of the basic current source 108 in the set operation is small. This is because there is a case where time until a steady state is obtained can be shortened in the case of
(122) In
(123) Note that the current source transistor 101 and the switching transistor 102 are p-channel type transistors in
(124) Further,
(125) There are a current source transistor 2001 which constantly operates as a current source (or a part of it) and a switching transistor 2002 of which operation changes according to the circumstance. The current source transistor 2001, the switching transistor 2002, and the wiring 110 are connected in series. A gate terminal of the current source transistor 2001 is connected to one of the terminals of a capacitor 2004. The other terminal 2006 of the capacitor 2004 is connected to a source terminal of the switching transistor 2002 (the current source transistor 2001). Therefore, a gate-source voltage of the current source transistor 2001 can be held. Further, the gate terminal and a drain terminal of the current source transistor 2001 are connected via a switch 2005. The capacitor 2004 can be controlled to hold a charge by ON/OFF of the switch 2005.
(126) An operation of
(127) Next, the switches 2005 and 106 are turned ON and the switches 2003, 107, and 114 are turned OFF. Then, the current source transistor 2001 and the switching transistor 2002 operate as a multi-gate transistor. Then, when a steady state is obtained, a current stops flowing to the capacitor 2004. At that time, a gate-source voltage of the multi-gate transistor is accumulated in the capacitor 2004. That is, a voltage required to flow the current Ib1 between the source and drain of the multi-gate transistor is applied between the gate and source thereof. The aforementioned operation corresponds to the set operation. At that time, the switching transistor 2002 performs the current source operation.
(128) Next, the switch 107 is turned ON and the switches 2003, 2005, 106, and 114 are turned OFF. Then, a current flows to the load 109. The aforementioned operation corresponds to the output operation. At that time, the switching transistor 2002 performs the current source operation.
(129) Note that a potential of the terminal 2006 of the capacitor 2004 is different between the set operation and the output operation in many cases. However, voltages of both ends of the capacitor 2004 (potential difference) does not change, therefore, a gate-source voltage of a transistor does not change and a desired current flows to the load 109.
(130) In this case also, it is needless to say that the switches may be disposed anywhere as long as they are connected as shown in
(131) Note that
(132) In the case of
(133) For example, the precharge operation as shown in
(134) Alternatively, another precharge operation may be performed in combination.
(135) For example, by employing a configuration shown in
(136) Note that a transistor used in the precharge operation and a transistor used in the set operation are preferably the same in their characteristics. For example, it is preferable that the current source transistor 101 and the switching transistor 102 have the same current characteristics in the case of
(137) In this manner, by changing an arrangement and the number of switches, polarity of each transistor, the number and arrangement of the current source transistor, the number and arrangement of the switching transistor, a potential of each wiring, a combination with another precharge method, a direction of current flow and the like, various circuits can be employed in the configuration as well as the circuit of
(138) [Embodiment Mode 2]
(139) In Embodiment Mode 1, the configuration shown in
(140) Note that the same part as Embodiment Mode 1 is not described anymore in the following description.
(141) First, a second configuration to realize the current source operation and the short-circuit operation to the switching transistor 102 is shown in
(142) The current source circuit shown in
(143) In
(144) Next, an operation of a current source circuit shown in
(145) Next, the switches 2801, 107, and 114 are turned OFF and the switches 105, 106, and 2802 are turned ON as shown in
(146) Next, the switches 2801, 105, 106, and 114 are turned OFF and the switches 107 and 2802 are turned ON as shown in
(147) Note that the potential of the wiring 2803 is not limited to Vss. It is only required to be a value which can turn ON the switching transistor 102 sufficiently.
(148) Note that the current source circuit shown in
(149) For example, by changing an arrangement and the number of switches, polarity of each transistor, the number and arrangement of the current source transistor 101, the number and arrangement of the basic current source, the number and arrangement of the switching transistor, a potential of each wiring, a combination with another precharge method, a direction of current flow and the like as in Embodiment Mode 1, various circuits can be employed in the configuration. Further, by combining each change also, the invention can be configured by using various circuits.
(150) For example, each of the switches may be disposed anywhere as long as they are connected as shown in
(151)
(152) Further,
(153) There are a current source transistor 4101 which always operates as a current source (or a part of it) and a switching transistor 4102 of which operation changes according to the circumstance. The current source transistor 4101, the switching transistor 4102, and the wiring 110 are connected in series. The gate terminal of the current source transistor 4101 is connected to one of the terminals of a capacitor 4104. The other terminal 4106 of the capacitor 4104 is connected to the source terminal of the switching transistor 4102 (the current source transistor 4101). Therefore, a gate-source voltage of the current source transistor 4101 can be held. Further, the gate terminal and the drain terminal of the current source transistor 4101 are connected via a switch 4105. The capacitor 4104 can be controlled to hold a charge by ON/OFF of the switch 4105.
(154) It is needless to say in this case also that the switches may be disposed anywhere as long as an operation of each of them can be normally performed in the precharge operation, the set operation, and the output operation.
(155) Note that a wiring 3603 is supplied with Vdd2 which is higher than Vdd. The invention is not limited to this, however, a potential as high as possible is preferably supplied in order that a current drive capacity of the switching transistor 4102 becomes as large as possible in the short-circuit operation.
(156) In this manner, by changing an arrangement and the number of switches, polarity of each transistor, the number and arrangement of the current source transistor, the number and arrangement of the basic current source, the number and arrangement of the switching transistor, a potential of each wiring, a combination with another precharge method, a direction of current flow and the like, various circuits can be employed in the configuration as well as the circuit of
(157) The contents described in this embodiment mode corresponds to Embodiment Mode 1 of which contents is partially changed. Therefore, the contents described in Embodiment Mode 1 can be applied to this embodiment mode as well.
(158) [Embodiment Mode 3]
(159) In this embodiment mode, a configuration example is described in which transistors are connected in parallel to change the summed value of currents flowing to each transistor, thereby performing the precharge operation and the set operation.
(160) Note that the same part as Embodiment Modes 1 and 2 are not described anymore in the following description.
(161) First, a configuration example of the case in which transistors are connected in parallel to perform the precharge operation and the set operation is described with reference to
(162) There are a set transistor 3702 which operates in a state that a current flows at least in the set operation, and a charge transistor 3701 which operates in a state that a current flows in the precharge operation. The set transistor 3702 and the charge transistor 3701 are connected in parallel. The gate terminal of the set transistor 3702 is connected to one terminal of a capacitor 3704. The gate terminal of the charge transistor 3701 is connected to one terminal of the capacitor 3704 as well. The other terminal of the capacitor 3704 is connected to a wiring 3708. Therefore, a potential of the gate terminal of the set transistor 3702 can be held. Further, a terminal 3710 and the drain terminal of the set transistor 3702 are connected via a switch 3703. Moreover, the terminal 3710 and the drain terminal of the charge transistor 3701 are connected via a switch 3706. Further, the terminal 3710 and the gate terminal of the set transistor 3702 are connected via a switch 3705. The capacitor 3704 can be controlled to hold a charge by ON/OFF of the switch 3705. Furthermore, the terminal 3710 and the wiring 112 are connected via the basic current source 108 and the switch 106. In parallel to the aforementioned, the terminal 3710 and the wiring 116 are connected via the second basic current source 115 and the switch 114. Similarly, in parallel to the aforementioned, the terminal 3710 and the wiring 113 are connected via the load 109 and the switch 107.
(163) By using the circuit having the configuration as shown in
(164) An operation of
(165) Next, the switches 3705, 3703, and 106 are turned ON and the switches 3706, 107, and 114 are turned OFF as shown in
(166) At this time, by appropriately setting the current Ib1 of the basic current source 108, the current Ib2 of the second basic current source 115, and a transistor size (gate width W, gate length L and the like) of the set transistor 3702 and the charge transistor 3701, a charge accumulated in the capacitor 3704, that is a potential of the gate terminal of the set transistor 3702 (or the charge transistor 3701) is controlled to be approximately equal in the precharge operation and the set operation. Then, in the case where the current Ib2 of the second basic current source 115 has a larger value than the current Ib1 of the basic current source 108, the capacitor 3704 can be charged in the precharge operation and a steady state can be obtained rapidly. After that, in the set operation, the steady state can be obtained rapidly even when the current Ib1 of the basic current source 108 is small in the set operation. This is because the capacitor 3704 is almost charged in the precharge operation.
(167) Next, the switches 3705, 3706, 106, and 114 are turned OFF and the switches 107 and 3703 are turned ON as shown in
(168) In this manner, by controlling ON/OFF of the switches 3703 and 3706, a current flowing in the precharge operation can be large, which can achieve the steady state rapidly. That is, the steady state can be rapidly obtained by lessening the effect of a load which is parasitic on a wiring through which a current flows (wiring resistance, intersection capacitance and the like). At that time, a state which is approximately close to the steady state in the set operation is already obtained, Therefore, the steady state can be rapidly obtained in the set operation after the precharge operation.
(169) Therefore, in the case where the load 109 is an EL element, a signal can be written rapidly when the EL element is to emit light in a low gray scale.
(170) Now, a condition for a voltage accumulated in the capacitor 3704 to be approximately equal in the precharge operation and the set operation is described. First, it is assumed that a gate width of the charge transistor 3701 is Wa, a gate length thereof is La, and a gate width of the set transistor 3702 is Wb, the gate length thereof is Lb. Then, a current flowing in the set operation (the current Ib1 of the basic current source 108 in
(171) Generally, a current flowing between a source and drain of a transistor is in proportion to a ratio of a channel width W and a channel length L: W/L. Therefore, a ratio of the gate width and the gate length Wa/La in the precharge operation and a ratio of the gate width and gate length Wb/Lb in the set operation are considered. The current Ib1 of the basic current source 108 times A equals to the current Ib2 of the second basic current source 115. Therefore, each value may be set so that Wb/Lb times A equals to Wa/La. Thus, a voltage of the capacitor 3704 (potentials of gate terminals of the charge transistor 3701 and the set transistor 3702) in the time T2a becomes approximately equal to a potential in the time T2b in
(172) Note that the capacitor 3704 can be substituted by a gate capacitance of the charge transistor 3701, the set transistor 3702, and the like. In that case, the capacitor 3704 can be omitted. Note that in the precharge operation, the switches 3706, 3705, and 114 are turned ON and the switches 107, 106, and 3703 are turned OFF and a current does not flow to the set transistor 3702 in
(173) In the precharge operation, the switch 114 is turned ON and the switches 107 and 106 are turned OFF and a current of the second basic current source 115 flows and the current of the basic current source 108 does not flow in
(174) Note that a wiring 3707, a wiring 3708, and a wiring 3709 are supplied with a power source on the high potential side Vdd, however, the invention is not limited to this. Each wiring may have the same potential or a different potential. The wiring 3708 is only required to be capable of storing a charge of the capacitor 3704. Further, the wiring 3707, the wiring 3709, or the wiring 3708 is not required to constantly maintain the same potential. The potential may change between the set operation and the output operation as long as a normal operation can be obtained.
(175) Note that the capacitor 3704 is connected to gate terminals of the charge transistor 3701 and the set transistor 3702 and the wiring 3708, however, the invention is not limited to this. It is most preferable that the capacitor 3704 be connected to the gate terminal and a source terminal of the set transistor 3702. This is because the operation of a transistor is not easily influenced by other effects (an effect of a voltage drop and the like due to a wiring resistance and the like) as long as a voltage is maintained between the gate terminal and the source terminal since the operation of the transistor is determined by a gate-source voltage. Provided that the capacitor 3704 is disposed between the gate terminals of the charge transistor 3701 and the set transistor 3702 and another wiring, a potential of the gate terminals of the charge transistor 3701 and the set transistor 3702 may change depending on the level of voltage drop of that another wiring.
(176) Note that the charge transistor 3701 and the set transistor 3702 are required to have approximately the same potentials in the precharge operation and the set operation, therefore, these transistors preferably have the same polarity (have the same conductivity type).
(177) Note that the gate widths W of the charge transistor 3701 and the set transistor 3702 may be the same or different. Similarly, the gate length L may be the same or different. The gate length L of the set transistor 3702 being longer, a current flowing in the set operation and the output operation becomes smaller. Further, even when a source-drain voltage in a saturation region changes, a current value hardly changes. That is, a kink effect can be small. Similarly, the gate width W of the set transistor 3702 being shorter, a current flowing in the set operation and the output operation becomes smaller. Therefore, an appropriate design may be employed according to the circumstance.
(178) Note that the description is made with reference to
(179) For example, each of the switches may be disposed anywhere as long as they are connected as shown in
(180) Further,
(181)
(182) Note that in this case also switches may be disposed anywhere as long as each of them can be operated normally in the precharge operation, the set operation, and the output operation or as long as they are connected as shown in
(183) In this manner, this embodiment mode can be configured by using various circuits as well as the circuit of
(184) In the case of
(185) For example, the precharge operation as shown in
(186) Alternatively, another precharge operation may be performed in combination.
(187) Note that a transistor used in the precharge operation and a transistor used in the set operation preferably have the same characteristics as much as possible. For example, in the case of
(188) The contents described in this embodiment mode corresponds to Embodiment Modes 1 and 2 of which contents are partially changed. Therefore, the contents described in Embodiment Modes 1 and 2 can be applied to this embodiment mode as well. The contents described in Embodiment Modes 1 and 2 can be implemented in combination with the contents described in this embodiment mode as well.
(189)
(190) It is needless to say that the contents described in Embodiment Modes 1 to 3 can be applied to the configuration of
(191) [Embodiment Mode 4]
(192) In this embodiment mode, the circuits described in Embodiment Modes 1 to 3 which are partially changed are described.
(193) Here, the case of changing the circuit of
(194) First,
(195) An operation of the circuit of
(196) Note that the current source transistor 101, the switching transistor 102, and the multi transistor 6101 operate as a multi-gate transistor, therefore, these transistors preferably have the same polarity (have the same conductivity).
(197) In the output operation, the current source transistor 101, the switching transistor 102, and the multi transistor 6101 operate as a multi-gate transistor, however, the gate width W of each transistor may be the same or different. Similarly, the gate length L of each may be the same or different as well. However, the gate width W is preferably the same since the gate width W can be considered to be the same as a typical multi-gate transistor. The gate lengths L of the switching transistor 102 and the multi transistor 6101 being longer, a current flowing to the load 109 becomes smaller. Further, even when a source-drain voltage changes in a saturation region, a current value hardly changes. That is, a kink effect can be small. Therefore, an appropriate design may be employed according to the circumstance.
(198) Next,
(199) An operation of the circuit of
(200) Note that as the set transistor 3702 and the multi transistor 6201 operate as a multi-gate transistor in the output operation, these transistors preferably have the same polarity (have the same conductivity).
(201) In this manner, the current source circuits shown in
(202) The contents described in this embodiment mode corresponds to Embodiment Modes 1 to 3 of which contents are partially changed. Therefore, the contents described in this embodiment mode can be applied to Embodiment Modes 1 to 3 as well.
(203) [Embodiment Mode 5]
(204) In this embodiment mode, configurations and operations of a display device, a signal line driver circuit and the like are described. The circuit of the invention can be applied to a portion of the signal line driver circuit or to a pixel.
(205) As shown in
(206) Note that a plurality of the gate line driver circuits 6302 and the signal line driver circuits 6310 may be disposed.
(207) A configuration of the signal line driver circuit 6310 can be divided into a plurality of portions. Briefly, it can be divided into a shift register 6303, a first latch circuit (LAT 1) 6304, a second latch circuit (LAT 2) 6305, and a digital-analog converter circuit 6306. The digital-analog converter circuit 6306 includes a function to convert a voltage into a current and may include a function to provide a gamma correction as well. That is, the digital-analog converter circuit 6306 includes a circuit for outputting a current (video signal) to a pixel, namely a current source circuit to which the invention can be applied.
(208) Furthermore, the pixel includes a display element such as an EL element. The display element includes a circuit for outputting a current (video signal), namely a current source circuit to which the invention can be applied.
(209) An operation of the signal line driver circuit 6310 is briefly described. The shift register 6303 is configured by using a plurality of columns of flip-flop circuits (FFs) and the like and inputted with a clock signal (S-CLK), a start pulse (SP), and a clock inversion signal (S-CLKb). Sampling pulses are sequentially outputted in accordance with these signals.
(210) The sampling pulses outputted from the shift register 6303 are inputted to the first latch circuit (LAT 1) 6304. The first latch circuit (LAT 1) 6304 is inputted with a video signal from the video signal line 6308 and holds a video signal in each column in accordance with a timing at which the sampling pulses are inputted. In the case where the digital-analog converter circuit 6306 is disposed, a video signal has a digital value. Further, the video signal in this stage is often a voltage.
(211) However, provided that the first latch circuit 6304 and the second latch circuit 6305 are capable of storing analog values, the digital-analog converter circuit 6306 can often be omitted. In that case, the video signal is often a current as well. Provided that data outputted to the pixel arrangement 6301 has a binary value, namely a digital value, the digital-analog converter circuit 6306 can often be omitted.
(212) When video signals are held up to the final column in the first latch circuit (LAT 1) 6304, a latch pulse is inputted from a latch control line 6309 in a horizontal retrace period and the video signals held in the first latch circuit (LAT 1) 6304 are transferred to the second latch circuit (LAT 2) 6305 all at once. After that, the video signals held in the second latch circuit (LAT 2) 6305 are inputted to the digital-analog converter circuit 6306 one row at a time. Then, the signals outputted from the digital-analog converter circuit 6306 are inputted to the pixel arrangement 6301.
(213) While the video signals held in the second latch circuit (LAT 2) 6305 are inputted to the digital-analog converter circuit 6306 and then to the pixels 6301, sampling pulses are outputted again in the shift register 6303. That is, two operations are simultaneously performed. Accordingly, a line sequential drive can be performed. After this, the aforementioned operation is repeated.
(214) Note that the current source circuit in the digital-analog converter circuit 6306 performs the set operation and the output operation, a circuit for flowing a current to the current source circuit is required. In that case, a reference current source circuit 6314 is provided.
(215) Note that the signal line driver circuit or a portion of it does not exist on the same substrate as the pixel arrangement 6301 but formed by using, for example, an external IC chip in some cases.
(216) The IC chip may be mounted on a glass substrate by connecting by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate by using TAB (Tape Auto Bonding) or a printed substrate. Note that configurations of the signal line driver circuit and the like are not limited to
(217) For example, in the case where the first latch circuit 6304 and the second latch circuit 6305 are capable of storing analog values, a video signal (analog current) may be inputted from the reference current source circuit 6314 to the first latch circuit (LAT 1) 6304 as shown in
(218) [Embodiment Mode 6]
(219) Next, a specific configuration of the signal line driver circuit 6310 described in Embodiment Mode 5 is described.
(220) First,
(221) Note that a current source of the reference current source circuit 6314 corresponds to the basic current source circuit 6507 in
(222) Further, as an example of the case of applying the invention to the signal line driver circuit,
(223) Note that only one current source circuit is shown in
(224) In the case of performing the set operation to the current source circuit, a timing thereof is required to be controlled. In that case, a dedicated driver circuit (shift register and the like) may be disposed for controlling the set operation. Alternatively, the set operation to the current source circuit may be controlled by using a signal outputted from the shift register for controlling the LAT 1 circuit. That is, the LAT 1 circuit and the current source circuit may be controlled by one shift register. In that case, the signal outputted from the shift register for controlling the LAT 1 circuit may be directly inputted to the current source circuit or the current source circuit may be controlled via a circuit for controlling a separation of a control of the LAT 1 circuit and a control of the current source circuit. Alternatively, a signal outputted from the LAT 2 circuit may be used to control the set operation to the current source circuit. A signal outputted from the LAT 2 circuit is normally a video signal, therefore, the current source circuit may be controlled via a circuit for controlling a separation of the case of using as a video signal and the case of controlling the current source circuit. A circuit configuration, an operation of the circuit and the like for controlling the set operation and the output operation in this manner are described in International Publication WO03/038793, International Publication WO03/038794, and International Publication WO03/038795, of which contents can be applied to the invention.
(225) In the case of outputting an analog current to the load 1909 (for example, a switch, a signal line, a pixel connected to a signal line and the like), a digital-analog conversion is required to be performed. Therefore, a configuration shown in
(226) Note that
(227) Next, the case of
(228) In the case where the second latch circuit (LAT 2) 6305 is not disposed, the load 1909 in
(229) Further, it can be considered that a current source circuit disposed in the first latch circuit 6304 corresponds to the basic current source circuit 6507 in
(230) Furthermore, the reference current source circuit 6314 shown in
(231) It can also be considered that a light emitting element disposed in a pixel corresponds to the load 1909 in
(232) In this manner, the invention can be applied to various portions.
(233) Note that a digital video signal (current value) corresponding to each bit may be inputted to the first latch circuit 6304. By adding a digital video signal current corresponding to each bit after that, the digital value can be converted into an analog value. In that case, the invention can be more preferably applied to the case of inputting a signal having a small digit number. This is because a current value of a signal becomes small in the case of a signal having a small digit number. The current value of the signal can be large by applying the invention. Therefore, a write speed of a signal can be improved.
(234) Note that a configuration of
(235) In this manner, by applying the invention to the signal line driver circuit, the set operation can be performed rapidly even with a small current value to be inputted to the signal line driver circuit. Provided that the set operation cannot be performed sufficiently, an accurate current cannot be outputted to a signal line. In that case, the pixel cannot perform an accurate display. Therefore, by applying the invention, an image defect can be prevented.
(236) Note that the contents described in this embodiment mode correspond to the one utilizing the contents described in Embodiment Modes 1 to 5. Therefore, the contents described in Embodiment Modes 1 to 5 can be applied to this embodiment mode as well.
(237) [Embodiment Mode 7]
(238) In Embodiment Mode 6, a specific configuration of the signal line driver circuit 6310 is described. In this embodiment mode, a specific configuration of the case of applying the invention to pixels arranged in array in the pixel arrangement 6301 is described.
(239) First,
(240) Each switch (transistor in
(241)
(242)
(243)
(244)
(245) In this manner, by sharing a circuit formed of the circuit 7812 between pixels, the circuit 7812 is not required to be disposed in each pixel. Therefore, the number of transistors in each pixel can be reduced. As a result, an aperture ratio and the yield in the manufacturing process can be improved.
(246) It is preferable that the circuit 7812 be disposed outside (periphery) of the pixel arrangement like the circuit 7812A and the circuit 7812B. This is because it is inappropriate to dispose the circuit 7812 in the pixel arrangement since pixels are disposed at regular intervals in the pixel arrangement. Therefore, it is preferable to connect between the pixel arrangement and a current source (the basic current source 108, the second basic current source 115 and the like) like the circuit 7812A, or connect at an end of the wiring 6807 like the circuit 7812B. It is more preferable to connect at the end of the wiring 6807 like the circuit 7812B since a current flows through the whole wiring 6807.
(247) Note that sharing the circuit 7812 is not limited in a pixel portion as shown in
(248) Further,
(249) In
(250) A configuration to be applied to a pixel is not limited to the configurations shown in
(251) For example, a polarity (conductivity) of the transistors in
(252) In
(253) Note that in the EL element, light may emit from either the anode side or the cathode side. Note that in
(254) For example, each gate line can be shared by controlling a polarity and operation of a transistor which operates as a switch. By controlling a polarity of each transistor in the circuit of
(255) In
(256) In
(257) In this manner, a pixel can employ various configurations.
(258) In the case of displaying an image by using these pixels, a gray scale can be displayed by using various methods.
(259) For example, an analog video signal (analog current) being inputted from the signal line 6807 to the pixel, a current corresponding to the video signal is supplied to a display element to display a gray scale.
(260) Alternatively, a digital video signal (digital current) being inputted from the signal line 6807 to the pixel, a current corresponding to the video signal is supplied to the display element to display two-level gray scale. In this case, however, a multi-level gray scale is often to be displayed by combining a time gray scale method and an area gray scale method.
(261) For example, when applying the time gray scale method and forcibly making the display element not to emit light, a current is not to be supplied to the display element. Therefore, for example, the transistor 107 is to be turned OFF. Otherwise, by controlling a charge in the capacitors 104 and 3704, a current is not to flow to the display element as a result. In order to realize the aforementioned, a switch and the like may be provided additionally.
(262) In the case where the number of gate lines is to be reduced as shown in
(263) A detailed description on the time gray scale method is omitted here, however, the methods described in Japanese Patent Application No. 2001-5426 and Japanese Patent Application No. 2000-86968 can be referred to.
(264) Further, a digital video signal (digital voltage) being inputted from a signal line to a pixel, a current is controlled to be supplied to a display element or not in accordance with the video signal, thereby a two-level gray scale may be displayed. Accordingly, in this case also, a multi-level gray scale is often to be displayed as well by combining the time gray scale method, the area gray scale method and the like.
(265) Furthermore, by flowing a current from another current source to the basic current source 108 or the second basic current source 115 to perform the precharge operation and the set operation, a current may flow from the basic current source 108 and the second basic current source 115 to the current source circuit 7301 as a load.
(266)
(267) Detailed descriptions on the circuits shown in
(268) Note that the configuration is not limited to the circuits shown in
(269) In this manner, by applying the invention to a pixel, the set operation can be performed rapidly even with a small current value to be inputted to the pixel. Provided that the set operation cannot be performed sufficiently, an image cannot be displayed accurately. Therefore, by applying the invention, an image defect can be prevented.
(270) Note that the contents described in this embodiment mode corresponds to the one which utilizes the contents described in Embodiment Modes 1 to 6. Therefore, the contents described in Embodiment Modes 1 to 6 can be applied to this embodiment mode as well. [Embodiment Mode 8]
(271) Electronic apparatuses using the invention include a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio reproducing device (car audio, audio component system and the like), a notebook type personal computer, a game machine, a portable information terminal (mobile computer, portable phone, portable game machine, electronic book or the like), an image reproducing device provided with a recording medium (specifically, a device which reproduces a recording medium such as a Digital Versatile Disc (DVD) and has a display to display the image) and the like. Specific examples of those electronic apparatuses are shown in
(272)
(273)
(274)
(275)
(276)
(277)
(278)
(279)
(280) Provided that a light emission luminance of a light emitting material becomes high in the future, the light including outputted image data can be expanded and projected by using a lens and the like to be used for a front or rear type projector.
(281) Furthermore, the aforementioned electronic apparatuses are becoming to be more used for displaying information distributed through a telecommunication path such as Internet, a CATV (cable television system), and in particular for displaying moving picture information. The display device is suitable for displaying moving pictures since the light emitting material can exhibit high response speed.
(282) It is preferable to display data with as small light emitting portion as possible because the light emitting device consumes power in the light emitting portion. Therefore, in the case of using the light emitting device in the display portions of the portable information terminal, in particular a portable phone or an audio reproducing device which mainly displays text data, it is preferable to drive so that the text data is formed by a light emitting portion with a non-light emitting portion as a background.
(283) As described above, the application range of the invention is so wide that the invention can be used in various fields of electronic apparatuses. The electronic apparatuses described in this embodiment can use any configuration of the semiconductor device described in Embodiment Modes 1 to 6.