Electronic device for a radiofrequency signal reception chain, comprising a low-noise transimpedance amplifier stage

Abstract

An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

Claims

1. A transimpedance amplifier circuit, comprising an amplifier end stage, a preamplifier stage coupled between a transimpedance amplifier input and an input of the amplifier end stage, said preamplifier stage comprising: first bipolar transistors; and an active load; and a self-biased common-mode control stage configured to bias the preamplifier stage.

2. The transimpedance amplifier circuit of claim 1, wherein the active load of the preamplifier stage comprises: a pair of load transistors, and wherein an output of the self-biased common-mode control stage is connected to control terminals of the pair of load transistors.

3. The transimpedance amplifier circuit of claim 1, wherein the amplifier end stage comprises a circuit module connected between two outputs of the amplifier end stage and having a node, and wherein the self-biased common-mode control stage comprises a differential pair of bipolar transistors, wherein a base of one of the bipolar transistors is configured to receive a common-mode voltage, and wherein a base of another of the bipolar transistors is connected to said node of the circuit module.

4. The transimpedance amplifier circuit of claim 3, wherein collectors of the differential pair of bipolar transistors are connected to a pair of load transistors connected as a current mirror.

5. The transimpedance amplifier circuit of claim 1, wherein the preamplifier stage comprises a differential pair of bipolar transistors, wherein bases of the bipolar transistors are configured to differential signals of the transimpedance amplifier input.

6. The transimpedance amplifier circuit of claim 1, further comprising a feedback resistor coupled between an output of the amplifier end stage and the transimpedance amplifier input.

7. The transimpedance amplifier circuit of claim 1, wherein the amplifier end stage comprises: a first amplifier having an input coupled to a first output of the preamplifier stage and having a first output; a second amplifier having an input coupled to a second output of the preamplifier stage and having a second output; and a circuit module connected between the first and second outputs.

8. The transimpedance amplifier circuit of claim 7, wherein the circuit module has an intermediate node between the first and second outputs, and wherein a first input of the self-biased common-mode control stage is coupled to the intermediate node and a second input of the self-biased common-mode control stage is coupled to receive a common mode reference voltage.

9. The transimpedance amplifier circuit of claim 7, wherein the first output of the preamplifier stage is at a first interconnection node between the first bipolar transistors and the active load and wherein the second output of the preamplifier stage is at a second interconnection node between the first bipolar transistors and the active load.

10. A transimpedance amplifier circuit, comprising: a first amplifier end stage having a first input; a second amplifier end stage having a second input; a resistive divider circuit coupled between a first output of the first amplifier end stage and a second output of the second amplifier end stage, the resistive divider circuit having an intermediate node between the first and second outputs; and a common-mode control circuit comprising a differential amplifier having a first input configured to receive a common-mode voltage and a second input coupled to the intermediate node of the resistive divider circuit, wherein the differential amplifier includes an output coupled to control biasing of the first and second amplifier end stages.

11. The transimpedance amplifier circuit of claim 10, further comprising a preamplifier stage having differential signal inputs and differential signal outputs, wherein the differential signal outputs are coupled, respectively, to the first and second inputs of the first and second amplifier end stages.

12. The transimpedance amplifier circuit of claim 10, wherein the preamplifier stage comprises: a differential amplifier circuit; an active load circuit coupled to the differential amplifier circuit and wherein a control terminal of the active load is coupled to receive a bias control signal output by the common-mode control circuit.

13. A transimpedance amplifier circuit, comprising: an amplifier end stage having an input and output, and a preamplifier stage coupled between an amplifier input and the input of the amplifier end stage and comprising first bipolar transistors as well as an active load, and a self-biased common-mode control stage configured to bias the preamplifier stage.

14. The transimpedance amplifier circuit of claim 13, wherein the active load of the preamplifier stage comprises first PMOS transistors and an output of the self-biased common-mode control stage is connected to control terminals of the first PMOS transistors.

15. The transimpedance amplifier circuit of claim 13, wherein the amplifier end stage comprises a circuit module connected between two outputs of the amplifier end stage and having a node, and the self-biased common-mode control stage comprises a differential pair of second bipolar transistors, a base of one of the second bipolar transistors configured to receive a common-mode voltage, and a base of the other second bipolar transistor being connected to said node of the circuit module so that a voltage at said node is controller to be equal to half a sum of the voltages present at the two outputs of the amplifier end stage.

16. The transimpedance amplifier circuit of claim 15, wherein collectors of the differential pair of second bipolar transistors are connected to two PMOS transistors connected as a current mirror.

17. The transimpedance amplifier circuit of claim 13, wherein the amplifier end stage comprises two class AB amplifiers, wherein control terminals of the first bipolar transistors are respectively connected to the amplifier input and collectors of the first bipolar transistors are respectively connected to inputs of the two class AB amplifiers.

18. A transimpedance amplifier circuit, comprising: a first amplifier end stage having an input coupled to a first amplifier input; a second amplifier end stage having an input coupled to a second amplifier input; a resistive divider circuit coupled between a first output of the first amplifier end stage and a second output of the second amplifier end stage, the resistive divided circuit having an output node; a common-mode control circuit comprising a differential amplifier having a first input configured to receive a common-mode voltage and a second input coupled to the output node of the resistive divider circuit, the differential amplifier having an output coupled to control biasing of the first and second amplifier end stages.

19. The transimpedance amplifier circuit of claim 18, further comprising a preamplifier stage coupled between the first and second current outputs of the frequency transposition stage and the inputs of the first and second amplifier end stages.

20. The transimpedance amplifier circuit of claim 19, wherein the preamplifier stage comprises a differential amplifier circuit with an active load circuit coupled to receive a bias control signal output by the common-mode control circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and characteristics of the invention will become apparent on studying the detailed description of entirely non-limiting embodiments and the appended drawings, in which:

(2) FIG. 1 is a schematic representation of a radiofrequency signal reception chain;

(3) FIG. 2 is a circuit diagram of a frequency transposition stage; and

(4) FIG. 3 is a circuit diagram for a transimpedance amplifier.

DETAILED DESCRIPTION

(5) FIG. 1 schematically represents a radiofrequency signal reception chain. In this chain, an antenna 1 receives a signal. This signal is prefiltered by a bandpass filter 2 then amplified by a low-noise amplifier 3 (known by those skilled in the art under the acronym LNA). The RF signal obtained in this way is sent to the input of a device 4 and a device 5, each comprising a mixer 20 associated with a transimpedance amplifier 21. The RF signal is respectively mixed with the signal generated by a local oscillator (LO) 6, and with the same signal phase-shifted through 90 by a phase shifter 7, so as to obtain two frequency shifted (transposed) signals in phase quadrature on the two channels I and Q. Although the invention may be applied to any type of reception chain, in particular of the type with a non-zero intermediate frequency, the chain is in this case of the zero intermediate frequency (ZIF) type, the transposed signals being directly in the baseband, that is to say the frequency of which lies around zero. The baseband signals at the output of the devices 4 and 5 are subsequently processed in conventional modules 8 and 9 having in particular equalization, amplification and lowpass and highpass filtering stages, then are sent to the input of analog/digital converters (ADC) 10 and 11.

(6) The differential architecture of the device 4 will now be described in more detail with reference to FIGS. 2 and 3, it being understood that this architecture is similar to that of the device 5.

(7) In FIG. 2, reference 20 denotes such a frequency transposition stage with current output.

(8) In the example of FIG. 2, the frequency transposition stage is a Gilbert cell, although the invention is not limited to this type of stage. Thus, it would also be possible to use a current switching device, for example, in particular a mixer with field-effect transistors (FET transistors), for example in the case of production in submicron MOS technology, such as a 28 nm technology on a substrate of the fully depleted silicon on insulator (FDSOI) type, or any type of frequency transposition stage structure with current output.

(9) The Gilbert cell of FIG. 2 comprises three differential pairs of bipolar transistors of the NPN type: QC.sub.1/QC.sub.2, QC.sub.3/QC.sub.4 and QC.sub.5/QC.sub.6, as well as input terminals RF INPUT and LO INPUT on which the radiofrequency signal RF and the signal generated by the local oscillator are respectively received, these terminals being respectively connected to the base electrodes of the transistors QC.sub.5 and QC.sub.6, and to the base electrodes of the transistors QC.sub.1, QC.sub.2, QC.sub.3 and QC.sub.4.

(10) The collector of the transistor QC.sub.1 is connected to the collector of the transistor QC.sub.3, to the current output terminal In, as well as to the drain of a PMOS transistor MC.sub.2 connected as a current mirror with a PMOS transistor MC.sub.1, the drain of which is connected to an input terminal Irefn for the reference current.

(11) Symmetrically, the collector of the transistor QC.sub.4 is connected to the collector of the transistor QC.sub.2, to the current output terminal Ip, and to the drain of a PMOS transistor MC.sub.3 connected as a current mirror with a PMOS transistor MC.sub.4, the drain of which is connected to an input terminal Irefp for the reference current. The sources of the PMOS transistors are for their part connected to a supply terminal VDD.

(12) The current mirrors formed by the transistors MC.sub.1, MC.sub.2 and MC.sub.3, MC.sub.4 make it possible to set the bias current flowing through MC2 and MC3.

(13) The negative current output terminal In and the positive current output terminal Ip are coupled to the input terminals of a transimpedance amplifier stage 21 which will convert the dynamic current at the output of the frequency transposition stage into voltage.

(14) FIG. 3 illustrates a transimpedance amplifier according to one embodiment.

(15) The transimpedance amplifier 21 comprises an amplifier end stage 42 comprising two class AB amplifiers 43 and 44, as well as a resistive load module 45 connected between the outputs OUT1 and OUT2 of these amplifiers and having a node VM.

(16) Two feedback resistors 60 and 60 are respectively connected between the outputs OUT2, OUT1 and the negative In and positive Ip current output terminals.

(17) The amplifiers 43 and 44 comprise a plurality of MOS transistors, and their output is a rail-to-rail output, that is to say the output voltage of these amplifiers can reach values close to the supply values.

(18) The amplifier 44, with a structure similar to that of the amplifier 43, will now be described in more detail. The references of the elements of the amplifier 43 are suffixed by a prime designation (for example, I.sub.OUT) relative to the references of the identical elements of the amplifier 44 (for example, I.sub.OUT).

(19) The AB amplifier per se comprises the MOS transistors M.sub.1 and M.sub.2 in PUSH-PULL configuration.

(20) It will be recalled here that an amplifier of the class AB type is a compromise between class A and class B. The neutral point of the class AB amplifier lies between that of a class A amplifier and that of a class B amplifier.

(21) The transistors M.sub.3, M.sub.4 and the current sources I.sub.3 and I.sub.4 form a biasing stage of the amplifier M.sub.1, M.sub.2.

(22) The transistors M.sub.5, M.sub.7 and the current source I.sub.7, as well as the transistors M.sub.6, M.sub.8 and the current source I.sub.8, make it possible to bias the biasing stage.

(23) The voltage swing at the output OUT2 varies between two values lying at a few tens of millivolts from each supply rail, for example but without limitation from 0.25 V to 2.25 V for a supply voltage VDD of 2.5 volts.

(24) The voltage VSS is ground.

(25) The gates of the transistors M.sub.1 and M.sub.1 form the inputs E2 and E1 of this end stage 42.

(26) The advantage of class AB amplifiers is that they have low consumption. However, the gain of such amplifiers is low.

(27) In order to have a higher gain, a preamplifier stage 41 is coupled between the output In, Ip of the frequency transposition stage 20 and the input E1, E2 of the amplifier end stage 42.

(28) The preamplifier stage 41 comprises a differential pair of bipolar transistors Q.sub.1 and Q.sub.2, the bases of which are respectively connected to the current outputs Ip and In of the frequency transposition stage, and the collectors of which are respectively connected to the inputs of the amplifiers 43 and 44.

(29) The use of bipolar transistors makes it possible to have a low noise level.

(30) The voltage preamplifier stage 41 furthermore comprises an active load 46 connected to the collectors of the bipolar transistors Q.sub.1 and Q.sub.2, and in this case comprising two PMOS transistors M.sub.9 and M.sub.10 in order to increase the gain.

(31) The gates of these PMOS transistors are connected via their gates (node VG) to the output of a self-biased common-mode control stage 40 configured in order to bias the preamplifier stage 41.

(32) This common-mode control stage 40 itself also comprises a differential pair of bipolar transistors Q.sub.3 and Q.sub.4.

(33) The base of the transistor Q.sub.4 is connected to a terminal MC which receives a common-mode voltage, that is to say a voltage equal to the average of the supply voltages, here equal to VDD and VSS. In this example, this common-mode voltage is equal to 1.25 V.

(34) The base of the transistor Q.sub.3 is for its part connected to the node VM of the module 45 of the amplifier end stage. A common-mode control loop is thus produced, so that the voltage at the node VM is equal to the average of the voltages present at the output terminals OUT1 and OUT2 of the end stage. The two output voltages thus oscillate in phase opposition around the common-mode voltage VDD/2.

(35) Lastly, the collectors of the bipolar transistors Q.sub.3 and Q.sub.4 are connected to the drains of the two PMOS transistors M.sub.11 and M.sub.12, which are connected as a current mirror (so as to self-bias this stage 40) and the gates of which are connected via the node VG to those of the PMOS transistors M.sub.9 and M.sub.10 forming the active load 46 of the preamplifier stage 41.

(36) A transimpedance amplifier having a low noise level and a high gain, and having low consumption as well as a rail-to-rail output, is thus obtained.

(37) Finally, a mixer with improved performance in terms of dynamic range is therefore obtained.

(38) Thus, by way of example, for an RF signal with a RADAR frequency equal to 77 GHz, with the aid of 143 ohm feedback resistors a gain of 43 dB is obtained, which for a dynamic current of 7 mA coming from the frequency transposition stage gives a voltage swing of 2 volts peak-to-peak for a supply of 2.5 volts, a dynamic consumption of the order of 8 mA and an idle consumption of 3 mA, and a noise of less than 17 nV/Hz.

(39) The invention is not limited to the embodiments which have just been described; rather, it encompasses all variants.

(40) Thus, although the reception chain described above has an architecture of the ZIF type, as indicated above it is possible to have a chain with a plurality of frequency transposition stages, so as to carry out successive transpositions with intermediate frequencies in order to arrive in the baseband, and a transimpedance amplifier stage such as the stage 21 after each frequency transposition stage.