Light emitting diode, method of fabricating the same and LED module having the same

Abstract

Disclosed are a light emitting diode (LED), an LED module including the same, and a method of fabricating the same. The light emitting diode includes a first conductive-type semiconductor layer; a second conductive-type semiconductor layer; an active layer interposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer; a first electrode pad region electrically connected to the first conductive-type semiconductor layer; a second electrode pad region electrically connected to the second conductive-type semiconductor layer; and a spark gap formed between a first leading end electrically connected to the first electrode pad region and a second leading end electrically connected to the second electrode pad region. The spark gap can achieve electrostatic discharge protection of the light emitting diode.

Claims

1. A light emitting diode comprising: a first conductive-type semiconductor layer; a second conductive-type semiconductor layer; an active layer interposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer; a current spreading layer electrically connected to the first conductive-type semiconductor layer and having a first leading end; an anti-diffusion reinforcing layer electrically connected to the second conductive-type semiconductor layer and having a second leading end; and a spark gap formed between the first leading end of the current spreading layer and the second leading end of the anti-diffusion reinforcing layer.

2. The light emitting diode of claim 1, wherein the light emitting diode includes a mesa disposed on the first conductive-type semiconductor layer, the mesa comprising the active layer and the second conductive-type semiconductor layer, and the first electrode pad region is electrically connected to the first conductive-type semiconductor layer at a side of the mesa.

3. The light emitting diode of claim 2, further comprising: a reflective electrode structure disposed on the mesa; an upper insulation layer covers the current spreading layer, and wherein the current spreading layer covers the mesa and the first conductive-type semiconductor layer, and having an opening exposing the reflective electrode structure, the current spreading layer being electrically connected to the first conductive type semiconductor layer while being insulated from the reflective electrode structure and the mesa, and wherein the upper insulation layer covers the current spreading layer.

4. The light emitting diode of claim 3, wherein the anti-diffusion reinforcing layer is disposed on the reflective electrode structure in the opening of the current spreading layer.

5. The light emitting diode of claim 4, wherein the anti-diffusion reinforcing layer is formed of the same material as that of the current spreading layer.

6. The light emitting diode of claim 4, wherein the upper insulation layer has a first opening that exposes the current spreading layer to define the first electrode pad region, and a second opening that exposes the anti-diffusion reinforcing layer to define the second electrode pad region.

7. The light emitting diode of claim 3, further comprising: a lower insulation layer disposed between the mesa and the current spreading layer and insulating the current spreading layer from the mesa, the lower insulation layer having an opening placed in an upper region of the mesa and exposing the reflective electrode structure.

8. The light emitting diode of claim 1, wherein the spark gap is disposed between the first electrode pad region and the second electrode pad region.

9. The light emitting diode of claim 1, wherein the first leading end and the second leading end have a semi-circular or angled shape and face each other.

10. The light emitting diode module of claim 2, further comprising: a reflective electrode structure formed over the mesa; and a lower insulation layer formed to cover the reflective electrode structure.

11. The light emitting diode module of claim 2, further comprising: an upper insulation layer formed to cover at least portions of the mesa and have an opening exposing the spark gap.

12. The light emitting diode module of claim 2, wherein the mesa has a slanted side surface.

13. The light emitting diode module of claim 1, further comprising an upper insulation layer covering the second conductive-type semiconductor layer and having an opening exposing the spark gap.

14. A light emitting diode comprising: a first conductive-type semiconductor layer; a second conductive-type semiconductor layer; an active layer interposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer; a first electrode pad region electrically connected to the first conductive-type semiconductor layer; a second electrode pad region electrically connected to the second conductive-type semiconductor layer; a spark gap formed between a first leading end electrically connected to the first electrode pad region and a second leading end electrically connected to the second electrode pad region; and an upper insulation layer covering the second conductive-type semiconductor layer, the upper insulation layer having an opening exposing the spark gap, wherein the light emitting diode includes a mesa disposed on the first conductive-type semiconductor layer, the mesa comprising the active layer and the second conductive-type semiconductor layer, and the first electrode pad region is electrically connected to the first conductive-type semiconductor layer at a side of the mesa, wherein the light emitting diode further includes a reflective electrode structure disposed on the mesa and a current spreading layer covering the mesa and the first conductive-type semiconductor layer, and having an opening exposing the reflective electrode structure, the current spreading layer being electrically connected to the first conductive-type semiconductor layer while being insulated from the reflective electrode structure and the mesa, wherein the upper insulation layer covers the current spreading layer and the first leading end is a portion of the current spreading layer, wherein the light emitting diode further includes an anti-diffusion reinforcing layer disposed on the reflective electrode structure in the opening of the current spreading layer, wherein the second leading end is a portion of the anti-diffusion reinforcing layer.

15. The light emitting diode of claim 14, wherein the anti-diffusion reinforcing layer is formed of the same material as that of the current spreading layer.

16. The light emitting diode of claim 14, wherein the upper insulation layer has a first opening that exposes the current spreading layer to define the first electrode pad region, and a second opening that exposes the anti-diffusion reinforcing layer to define the second electrode pad region.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic sectional view of an exemplary LED module in accordance with an embodiment of the disclosed technology.

(2) FIG. 2(a) to FIG. 10 are views illustrating an exemplary method of fabricating a light emitting diode in accordance with an embodiment of the disclosed technology, and in each of FIG. 2 to FIG. 9, (a) is a plan view, (b) is a cross-sectional view taken along line A-A, and (c) is a cross-sectional view taken along line B-B.

(3) FIG. 11(a) to FIG. 14(c) are views illustrating an exemplary method of fabricating a light emitting diode in accordance with an embodiment of the disclosed technology, and in each of FIG. 11 to FIG. 14, (a) is a plan view, (b) is a cross-sectional view taken along line A-A, and (c) is a cross-sectional view taken along line B-B.

DETAILED DESCRIPTION

(4) In the related art, the light emitting diode employs linear extension legs which have high resistance, which results in imposing some limit on current spreading. Moreover, since the reflective electrode is placed only on the P-type semiconductor layer, a substantial amount of light is absorbed by the electrode pads and extension legs while not being reflected by the reflective electrode and thus, substantial light loss is caused. When used in a final product, the light emitting diode is provided by an LED module. The LED module generally includes a printed circuit board and an LED package mounted on the printed circuit board, in which the light emitting diode is mounted in chip form within the LED package. A typical LED chip is packaged after being mounted on a sub-mount, a lead frame or a lead electrode by silver pastes or AuSn solders. Then, the LED package is mounted on the printed circuit board by solder pastes. As a result, pads on the LED chip are distant from the solder pastes, and bonded to the printed circuit board by a relatively stable bonding material such as silver pastes, AuSn, and the like.

(5) Recently, various attempts have been made to fabricate an LED module by directly bonding electrode pads of a light emitting diode to a printed circuit board using solder pastes. For example, an LED module can be fabricated by directly mounting an LED chip on a printed circuit board instead of packaging the LED chip. Otherwise, an LED module can be fabricated by mounting a so-called wafer level LED package on a printed circuit board. In these LED modules, since the electrode pads directly adjoin the solder pastes, metal elements such as tin (Sn) diffuse from the solder pastes into the light emitting diode through the pads and cause short circuit in the light emitting diode and device failure.

(6) GaN-based compound semiconductors are formed by epitaxial growth on a sapphire substrate, the crystal structure and lattice parameter of which are similar to those of the semiconductors, in order to reduce crystal defects. However, the epitaxial layers grown on the sapphire substrate contain many crystal defects such as V-pits, threading dislocations, and the like. When high voltage static electricity is applied to the epitaxial layers, current is concentrated at crystal defects in the epitaxial layers, causing diode breakdown. Thus, with respect to electrostatic discharge or electrical fast transient (EFT), which is a spark generated in a switch, and lightning surge in air, securing reliability of LEDs becomes important.

(7) Generally, in packaging of a light emitting diode, a Zener diode is mounted together with the light emitting diode to prevent electrostatic discharge. However, the Zener diode is expensive and a process of mounting the Zener diode increases the number of processes for packaging the light emitting diode and manufacturing costs. Moreover, since the Zener diode is placed near the light emitting diode in the LED package, the LED package has deteriorated luminous efficacy due to absorption of light by the Zener diode and deteriorated LED package yield.

(8) Hereinafter, exemplary embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings. It should be understood that the following embodiments are provided as some examples of the disclosed technology to facilitate understanding of the disclosed technology. Thus, it should be understood that the disclosed technology is not limited to the following embodiments and may be embodied in different ways. In addition, in the drawings, the width, length and thickness of components may be exaggerated for convenience. Further, it should be noted that the drawings are not to precise scale. Like components will be denoted by like reference numerals throughout the specification.

(9) FIG. 1 is a schematic sectional view of an LED module in accordance with one embodiment of the disclosed technology.

(10) Referring to FIG. 1, an LED module according to an exemplary embodiment of the disclosed technology includes a printed circuit board 51 having pads 53a and 53b and a light emitting diode 100 bonded to the printed circuit board 51 via solder pastes 55.

(11) The printed circuit board has a printed circuit thereon, and any substrate capable of providing an LED module can be used as the printed circuit board without limitation.

(12) Conventionally, a light emitting diode is mounted on a substrate having a lead frame or lead electrodes formed thereon, and a light emitting diode package including such a light emitting diode is mounted on a printed circuit board. According to some implementations, the light emitting diode 100 is directly mounted on the printed circuit board 51 via the solder pastes 55.

(13) The light emitting diode 100 may include a flip-chip type light emitting diode and be mounted upside down on the printed circuit board. To this end, the light emitting diode 100 has a first electrode pad region 43a and a second electrode pad region 43b. The first and second electrode pad regions 43a and 43b may be formed in a recess shape on one surface of the light emitting diode 100.

(14) On the other hand, a lower surface of the light emitting diode 100, for example, a surface of the light emitting diode opposite the first and second electrode pad regions 43a and 43b, may be covered with a wavelength conversion layer 45. The wavelength conversion layer 45 may cover not only the lower surface of the light emitting diode 100 but also side surfaces of the light emitting diode 100.

(15) In FIG. 1, the light emitting diode is schematically shown for convenience of description. The structure and respective components of the light emitting diode will be more clearly understood in the following description of a method of fabricating the light emitting diode. Furthermore, it should be noted that light emitting diodes according to embodiments of the disclosed technology are not limited to the structure in which the light emitting diode is directly mounted on the printed circuit board.

(16) FIG. 2(a) to FIG. 10 are views illustrating a method of fabricating a light emitting diode in accordance with an exemplary embodiment of the disclosed technology. In each feature, (a) is a plan view, (b) is a cross-sectional view taken along line A-A, and (c) is a cross-sectional view taken along line B-B.

(17) First, referring to FIGS. 2(a) to 2(c), a first conductive-type semiconductor layer 23, an active layer 25 and a second conductive-type semiconductor layer 27 are grown on a substrate 21. The substrate 100 enables the growth of a GaN-based semiconductor layer, and may include, for example, a sapphire substrate, a silicon carbide substrate, a GaN substrate, or a spinel substrate, and the like. In some implementations, the substrate may be or include a patterned substrate such as a patterned sapphire substrate.

(18) For example, the first conductive-type semiconductor layer may include an n-type gallium nitride-based layer and the second conductive-type semiconductor layer 27 may include a p-type gallium nitride-based layer. In addition, the active layer 25 may have a single quantum well structure or a multi-quantum well structure, and may include well layers and barrier layers. In addition, the composition of the well layers may be determined according to the wavelength of light and may include, for example, AlGaN, GaN or InGaN.

(19) On the other hand, a pre-oxidation layer 29 may be formed on the second conductive-type semiconductor layer 27. The pre-oxidation layer 29 may be formed of or include, for example, SiO.sub.2 by chemical vapor deposition.

(20) Then, a photoresist pattern 30 is formed. The photoresist pattern 30 is patterned to have openings 30a. As shown in FIG. 2(a) and FIG. 2(b), the openings 30a are formed such that an inlet of each opening has a narrower width than a bottom of the opening. The photoresist pattern 30 having the openings 30a of this structure can be easily formed using a negative type photoresist.

(21) Referring to FIGS. 3(a) to 3(c), the pre-oxidation layer 29 is etched using the photoresist pattern 30 as an etching mask. The pre-oxidation layer 29 may be etched by wet etching. As a result, the pre-oxidation layer 29 in the openings 30a of the photoresist pattern 30 is etched to form openings 29a of the pre-oxidation layer 29, which expose the second conductive-type semiconductor layer 27. The bottom portions of the openings 29a are generally similar or greater than the bottom portions of the openings 30a of the photoresist pattern 30.

(22) Referring to FIG. 4, a reflective electrode structure 35 is formed by a lift-off technology. The reflective electrode structure 35 may include a reflective metal section 31, a capping metal section 32 and an anti-oxidation metal section 33. The reflective metal section 31 includes a reflective layer, and a stress relief layer may be further formed between the reflective metal section 31 and the capping metal section 32. The stress relief layer relieves stress due to difference in coefficient of thermal expansion between the reflective metal section 31 and the capping metal section 32.

(23) The reflective metal section 31 may be formed of or include, for example, Ni/Ag/Ni/Au, and may have an overall thickness of about 1600 . As shown, the reflective metal section 31 is formed to have a slanted side surface, for example, such that the bottom of the reflective metal section has a relatively wide area. Such a reflective metal section 31 may be formed by e-beam evaporation.

(24) The capping metal section 32 covers upper and side surfaces of the reflective metal section 31 to protect the reflective metal section 31. The capping metal section 32 may be formed by sputtering or by e-beam evaporation, for example, planetary e-beam evaporation, in which vacuum deposition is performed while rotating the substrate 21 in a slanted state. The capping metal section 32 may include Ni, Pt, Ti, or Cr, and may be formed by depositing, for example, about five pairs of Ni/Pt layers or about five pairs of Ni/Ti layers. Alternatively, the capping metal section 32 may include TiW, W, or Mo.

(25) A material for the stress relief layer may be selected in various ways depending upon metal components of the reflective layer and the capping metal section 32. For example, when the reflective layer is composed of or includes Al or Al-alloys and the capping metal section 32 is composed of or includes W, TiW or Mo, the stress relief layer may be or include a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. In addition, when the reflective layer is composed of or includes Al or Al-alloys and the capping metal section 32 is composed of or includes Cr, Pt, Rh, Pd or Ni, the stress relief layer may be or include a single layer of Ag or Cu, or a composite layer of Ni, Au, Cu or Ag.

(26) In addition, when the reflective layer is composed of or includes Ag or Ag-alloys and the capping metal section 32 is composed of or includes W, TiW or Mo, the stress relief layer may be or include a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au. Further, when the reflective layer is composed of or includes Ag or Ag-alloys and the capping metal section 32 is composed of or includes Cr or Ni, the stress relief layer may be or include a single layer of Cu, Cr, Rh, Pd, TiW or Ti, or a composite layer of Ni, Au or Cu.

(27) Further, the anti-oxidation metal section 33 includes Au in order to prevent oxidation of the capping metal section 32, and may be formed of or include, for example, Au/Ni or Au/Ti. Since Ti secures adhesion of an oxide layer such as SiO.sub.2, in some implementations, Ti can be used. The anti-oxidation metal section 33 may also be formed by sputtering or by e-beam evaporation, for example, planetary e-beam evaporation, in which vacuum deposition is performed while rotating the substrate 21 in a slanted state.

(28) The photoresist pattern 30 is removed after deposition of the reflective electrode structure 35, whereby the reflective electrode structure 35 remains on the second conductive-type semiconductor layer 27, as shown in FIG. 4.

(29) The reflective electrode structure 35 may include branches 35b and a connecting portion 35a, as shown in FIG. 4. The branches 35b may have an elongated shape and be parallel to each other. The connecting portion 35a connects the branches 35b to each other. However, it should be understood that the reflective electrode structure 35 is not limited to a particular shape and may be modified into various shapes.

(30) Referring to FIG. 5, a mesa M is formed on the first conductive-type semiconductor layer 21. The mesa M includes the active layer 25 and the second conductive-type semiconductor layer 27. The active layer 25 is placed between the first conductive-type semiconductor layer 23 and the second conductive-type semiconductor layer 27. The reflective electrode structure 35 is placed on the mesa M.

(31) The mesa M is formed by patterning the second conductive-type semiconductor layer 27 and the active layer 25 so as to expose the first conductive-type semiconductor layer 23. The mesa M may be formed to have a slanted side surface by photoresist reflow technology or the like. The slanted profile of the side surface of the mesa M enhances extraction efficiency of light generated in the active layer 25.

(32) As shown, the mesa M may include elongated branches Mb extending parallel to each other in one direction and a connection portion Ma connecting the branches to each other. With such configuration of the mesa, the light emitting diode can permit uniform spreading of electric current in the first conductive-type semiconductor layer 23. Here, it should be understood that the mesa M is not limited to a particular shape and may be modified into various shapes. On the other hand, the reflective electrode structure 35 covers most of the upper surface of the mesa M and generally has the same shape as the shape of the mesa M in plan view.

(33) While the second conductive-type semiconductor layer 27 and the active layer 25 are subjected to etching, the pre-oxidation layer 29 remaining on these layers is also partially removed by etching. On the other hand, although the pre-oxidation layer 29 can remain near an edge of the reflective electrode structure 35 on each of the mesa M, the remaining pre-oxidation layer 29 can also be removed by wet etching and the like. Alternatively, the pre-oxidation layer 29 may be removed before formation of the mesa M.

(34) Referring to FIG. 6, after the mesa M is formed, a lower insulation layer 37 is formed to cover the mesa M and the first conductive-type semiconductor layer. The lower insulation layer 37 may be formed of or include an oxide layer such as SiO.sub.2 and the like, a nitride layer such as SiNx and the like, or an insulation layer of MgF.sub.2 by chemical vapor deposition (CVD) and the like. The lower insulation layer 37 may be a single layer or multiple layers. In addition, the lower insulation layer 37 may be or include a distributed Bragg reflector (DBR) in which low refractive index material layers and high refractive index material layers are alternately stacked one above another. For example, an insulating reflective layer having high reflectivity may be formed by stacking dielectric layers such as SiO.sub.2/TiO.sub.2, or SiO.sub.2/Nb.sub.2O.sub.5, and the like.

(35) Then, a chip isolation region 23h is formed by laser scribing to divide the lower insulation layer 37 and the first conductive-type semiconductor layer 23 into chip units. Grooves may be formed on the upper surface of the substrate 21 by laser scribing. As a result, the substrate 21 is exposed near an edge of the first conductive-type semiconductor layer 23.

(36) Since the first conductive-type semiconductor layer 23 is divided into chip units by laser scribing, it is possible to omit a separate photomask for an isolation process. However, it should be understood that the disclosed technology is not limited to the isolation process using laser scribing. For example, the first conductive-type semiconductor layer 23 may be divided into chip units before or after formation of the lower insulation layer 37 using a typical photolithography and etching technique.

(37) As shown in FIG. 6, the mesa M may be formed to be placed only inside an upper region of the first conductive-type semiconductor layer 23. For example, the mesa M may be placed in an island shape on the upper region of the first conductive-type semiconductor layer 23.

(38) Next, referring to FIG. 7, the lower insulation layer 37 is subjected to patterning to form openings 37a and 37b in predetermined regions to allow electrical connection to the first conductive-type semiconductor layer 23 and the second conductive-type semiconductor layer 27. For example, the lower insulation layer 37 may have openings 37b which expose the first conductive-type semiconductor layer 23, and openings 37a which expose the reflective electrode structure 35.

(39) The openings 37a are placed only in upper regions of the mesas M, for example, on the connecting portions of the mesas M. The openings 37b may be placed in regions between the branches Mb of the mesas M and near the edge of the substrate 21, and may have an elongated shape extending along the branches Mb of the mesas M.

(40) Referring to FIG. 8, a current spreading layer 39 is formed on the lower insulation layer 37. The current spreading layer 39 covers the mesa M and the first conductive-type semiconductor layer 23. In addition, the current spreading layer 39 has an opening 39a placed in the upper region of the mesa M and exposing the reflective electrode structure 35. The current spreading layer 39 may form ohmic contact with the first conductive-type semiconductor layer 23 through the opening 37b of the lower insulation layer 37. The current spreading layer 39 is insulated from the mesa M and the reflective electrodes 35 by the lower insulation layer 37.

(41) The opening 39a of the current spreading layer 39 has a greater area than the opening 37a of the lower insulation layer 37 to prevent the current spreading layer 39 from being connected to the reflective electrode structures 35. Thus, the opening 39a has sidewalls placed on the lower insulation layer 37.

(42) The current spreading layer 39 is formed on an overall upper region of the substrate 21 excluding the openings 39a. Thus, electric current can be easily dispersed through the current spreading layer 39.

(43) The current spreading layer 39 may include an ohmic contact layer, a reflective metal layer, an anti-diffusion layer, and an anti-oxidation layer. The current spreading layer can form ohmic contact with the first conductive-type semiconductor layer through the ohmic contact layer. For example, the ohmic contact layer may be formed of or include Ti, Cr, or Ni, and the like. The reflective metal layer increases reflectivity of the light emitting diode by reflecting incident light entering the current spreading layer. The reflective metal layer may be formed of or include Al. In addition, the anti-diffusion layer protects the reflective metal layer by preventing diffusion of metal elements. For example, the anti-diffusion layer can prevent diffusion of metal elements such as Sn within a solder paste. The anti-diffusion layer may be composed of or include Cr, Ti, Ni, Mo, TiW, or W or combinations thereof. The anti-diffusion layer may be a single layer including Mo, TiW or W. Alternatively, the anti-diffusion layer may include a pair of Cr, Ti or Ni layers. For example, the anti-diffusion layer may include at least two pairs of Ti/Ni or Ti/Cr layers. The anti-oxidation layer is formed to prevent oxidation of the anti-diffusion layer and may include Au.

(44) The current spreading layer may have a reflectivity of 65% to 75%. Accordingly, the light emitting diode according to this embodiment can provide optical reflection by the current spreading layer in addition to optical reflection by the reflective electrode structure, whereby light traveling through the sidewall of the mesa and the first conductive-type semiconductor layer can be reflected.

(45) The current spreading layer may further include a bonding layer placed on the anti-oxidation layer. The bonding layer may include Ti, Cr, Ni or Ta. The bonding layer is used to enhance bonding strength between the current spreading layer and the upper insulation layer, and may be omitted.

(46) For example, the current spreading layer 39 may have a multi-layer structure including Cr/Al/Ni/Ti/Ni/Ti/Au/Ti.

(47) While the current spreading layer 39 is formed, an anti-diffusion reinforcing layer 40 is formed on the reflective electrode structure 35. The anti-diffusion reinforcing layer 40 and the current spreading layer 39 may be formed of or include the same material by the same process. The anti-diffusion reinforcing layer 40 is separated from the current spreading layer 39. The anti-diffusion reinforcing layer 40 is placed within the opening 39a of the current spreading layer 39.

(48) The anti-diffusion reinforcing layer 40 has a leading end 40a extending therefrom, and the current spreading layer 39 has a leading end 39b facing the leading end 40a. The leading end 40a may be placed on the lower insulation layer 37 outside the opening 37a of the lower insulation layer 37. However, it should be understood that the disclosed technology is not limited thereto. Alternatively, the opening 37a of the lower insulation layer 37 may have a similar shape to the shape of the leading end 40a, and the leading end 40a may be placed within the opening 40a of the lower insulation layer 37.

(49) The leading end 39a of the current spreading layer 39 is placed on the lower insulation layer 37 and is separated from the leading end 40a. The leading end 39b and the leading end 40a define a spark gap therebetween. As a result, these leading ends 39b and 40a may be placed closer than other portions or may have an angled shape in order to allow generation of an electric spark between the leading ends 39b and 40a when high voltage static electricity is applied to a gap between the current spreading layer 39 and the anti-diffusion reinforcing layer 40. For example, as shown in FIG. 8, the leading ends 39b and 40a may have a semi-circular shape or an angled shape and may be disposed to face each other.

(50) Referring to FIG. 9, an upper insulation layer 41 is formed on the current spreading layer 39. The upper insulation layer 41 has an opening 41a which exposes the current spreading layer 39 to define a first electrode pad region 43a, and an opening 41b which exposes the reflective electrode structure 35 to define a second electrode pad region 43a. The opening 41a may have an elongated shape perpendicular to the branches Mb of the mesa M. The opening 41b of the upper insulation layer 41 has a narrower area than the opening 39a of the current spreading layer 39 and thus the upper insulation layer 41 can cover the sidewall of the opening 39a.

(51) When the anti-diffusion reinforcing layer 40 is formed on the reflective electrode structure 35, the opening 41b exposes the anti-diffusion reinforcing layer 40. In this case, the reflective electrode structure 35 can be concealed or sealed by the upper insulation layer 41 and the anti-diffusion reinforcing layer 40. Furthermore, the upper insulation layer 41 has an opening 41c which exposes at least part of the leading end 39b and the leading end 40a. With this configuration, the spark gap between the leading end 39b and the leading end 40a is exposed, thereby allowing generation of electrostatic discharge by an electrical spark through air.

(52) Further, the upper insulation layer 41 may be formed on the chip isolation region 23h to cover the side surface of the first conductive-type semiconductor layer 23. With this configuration, it is possible to prevent penetration of moisture and the like through upper and lower interfaces of the first conductive-type semiconductor layer.

(53) The upper insulation layer 41 may be formed of or include a silicon nitride layer to prevent diffusion of metal elements from solder pastes, and may have a thickness of 1 m to 2 m. When the thickness of the upper insulation layer is less than 1 m, it is difficult to prevent diffusion of metal the elements from the solder pastes.

(54) Optionally, an anti-Sn diffusion plating layer (not shown) may be additionally formed on the first electrode pad region 43a and the second electrode pad region 43b by electroless plating such as ENIG (electroless nickel immersion gold) and the like.

(55) The first electrode pad region 43a is electrically connected to the first conductive-type semiconductor layer 23 through the current spreading layer 39, and the second electrode pad region 43b is electrically connected to the second conductive-type semiconductor layer 27 through the anti-diffusion reinforcing layer 40 and the reflective electrode structure 35.

(56) The first electrode pad region 43a and the second electrode pad region 43b are used to mount the light emitting diode on a printed circuit board and the like via solder pastes. Thus, in order to prevent short circuit between the first electrode pad region 43a and the second electrode pad region 43b by the solder pastes, electrode pads may be separated by a distance of about 300 m or more from each other.

(57) Then, the substrate 21 may be removed to have a small thickness by partially grinding and/or lapping a lower surface of the substrate 21. Then, the substrate 21 is divided into individual chip units, thereby providing divided light emitting diode chips. Here, the substrate 21 may be divided at the chip isolation region 23h formed by laser scribing and thus there is no need for additional laser scribing for division of chips.

(58) The substrate 21 may be removed from the light emitting diode chips before or after being divided into individual light emitting diode chip units.

(59) Referring to FIG. 10, a wavelength conversion layer 45 is formed on the light emitting diodes separated from each other. The wavelength conversion layer 45 may be formed by coating a phosphor-containing resin onto the light emitting diodes using a printing technique, or by coating the substrate 21 with phosphor powder using an aerosol apparatus. For example, aerosol deposition can form a thin phosphor layer with a uniform thickness on the light emitting diodes, thereby improving color uniformity of light emitted from the light emitting diodes. As a result, the light emitting diodes according to the embodiments of the disclosed technology are completed and may be bonded to the corresponding pads 53a, 53b of the printed circuit board 51 by solder pastes, as shown in FIG. 1.

(60) In this embodiment, the first and second electrode pad regions 43a and 43b exposed by the upper insulation layer 41 are directly mounted on the printed circuit board. However, it should be understood that the disclosed technology is not limited thereto. Alternatively, additional electrode patterns are formed on the electrode pad regions 43a and 43b to form further enlarged pad regions. In this case, however, an additional photomask for formation of the electrode patterns may be used.

(61) FIG. 11(a) to FIG. 14(c) are views illustrating a method of fabricating a light emitting diode in accordance with another embodiment of the disclosed technology, and in each figure, (a) is a plan view, (b) is a cross-sectional view taken along line A-A, and (c) is a cross-sectional view taken along line B-B.

(62) In the embodiments described above, the mesa M is formed after the reflective electrode structure 35 is formed. In the present implementations, the mesa M is formed before the reflective electrode structure 35 is formed.

(63) First, referring to FIG. 11, as described with reference to FIG. 2, a first conductive-type semiconductor layer 23, an active layer 25 and a second conductive-type semiconductor layer 27 are formed on a substrate 21. Then, the mesa M is formed by a patterning process. The mesa M is similar to that described above in FIG. 5, and a detailed description thereof will be omitted.

(64) Referring to FIG. 12, a pre-oxidation layer 29 is formed to cover the first conductive-type semiconductor layer 23 and the mesa M. The pre-oxidation layer 29 may be formed of or include the same material by the same process as those described with reference to FIG. 2. A photoresist pattern 30 having openings 30a is formed on the pre-oxidation layer 29. The openings 30a of the photoresist pattern 30 are placed in an upper region of the mesa M. The photoresist pattern 30 is the same as that described with reference to FIG. 2 except that the photoresist pattern 30 is formed on the substrate 21 having the mesa M formed thereon, and a detailed description thereof will be omitted.

(65) Referring to FIG. 13, the pre-oxidation layer 29 is subjected to etching through the photoresist pattern 30 used as an etching mask, so that openings 29a are formed to expose the second conductive-type semiconductor layer 27 therethrough.

(66) Referring to FIG. 14, as described in detail with reference to FIG. 4, the reflective electrode structure 35 is formed on each mesas M by a lift-off technique. Then, light emitting diodes can be fabricated through similar processes to the processes described above with reference to FIG. 6 to FIG. 11.

(67) According to this embodiment, since the mesa M is formed prior to the reflective electrode structure 35, the pre-oxidation layer 29 can remain on side surfaces of the mesas M and in regions between the mesas M. Then, the pre-oxidation layer 29 is covered by the lower insulation layer 39 and is subjected to patterning together with the lower insulation layer 39.

(68) Although various embodiments have been described above, it should be understood that other implementations are also possible. In addition, some features of a certain embodiment may also be applied to other embodiments in the same or similar ways without departing from the spirit and scope of the disclosed technology.