METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

Abstract

A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

Claims

1. A semiconductor structure, comprising: a carrier substrate; a patterned silicon nitride layer over the carrier substrate, the patterned silicon nitride layer configured to define a passive device of the semiconductor structure; dished silicon oxide pockets disposed laterally between pattern features of the patterned silicon nitride layer, the dished silicon oxide pockets having a dishing height; and a layer of conformal oxide on or over the patterned silicon nitride layer and the dished silicon oxide pockets, the layer of conformal oxide conforming to the patterned silicon nitride layer and defining a bonding interface for bonding with an active device, the layer of conformal oxide from the patterned silicon nitride layer to the bonding interface being a thin layer above the patterned silicon nitride and the dished silicon oxide pockets with a thickness less than 300 nm.

2. The semiconductor structure of claim 1, wherein the dished silicon oxide pockets comprise volumes of planarized conformal oxide material.

3. The semiconductor structure of claim 2, wherein the volumes of planarized conformal oxide material of the dished silicon oxide pockets do not extend vertically beyond the silicon nitride patterned layer.

4. The semiconductor structure of claim 3, wherein an upper surface of the planarized conformal oxide material of the dished silicon oxide pockets is recessed relative to a surface of the silicon nitride patterned layer.

5. The semiconductor structure of claim 1, wherein the layer of conformal oxide is formed by re-oxidizing the dished silicon nitride patterned layer.

6. The semiconductor structure of claim 1, further comprising a layer of semiconductor material bonded to the layer of conformal oxide.

7. The semiconductor structure of claim 6, wherein the layer of semiconductor material comprises a patterned layer including at least one region forming at least a portion of at least one active device.

8. The semiconductor structure of claim 6, wherein the layer of semiconductor material comprises a layer of silicon.

9. A photonic device comprising a semiconductor structure according to claim 1.

10. A semiconductor structure, comprising: a patterned silicon nitride layer over a carrier substrate, the patterned silicon nitride layer forming a passive device; dished silicon oxide pockets disposed laterally between pattern features of the patterned silicon nitride layer, the dished silicon oxide pockets having a dishing height; and a layer of a conformal oxide on or over the patterned silicon nitride layer and the dished silicon oxide pockets defining a bonding interface for bonding with an active device; wherein the layer of conformal oxide from the patterned silicon nitride layer to the bonding interface is a thin layer above the patterned silicon nitride and the dished silicon oxide pockets with a final thickness less than about 50 nm, and the final thickness of the layer of conformal oxide has a uniformity higher than about 20%.

11. The semiconductor structure of claim 10, wherein the final thickness is less than about 5 nm.

12. The semiconductor structure of claim 10, wherein the dished silicon oxide pockets comprise volumes of planarized conformal oxide material.

13. The semiconductor structure of claim 12, wherein the volumes of planarized conformal oxide material of the dished silicon oxide pockets do not extend vertically beyond the silicon nitride patterned layer.

14. The semiconductor structure of claim 13, wherein an upper surface of the planarized conformal oxide material of the dished silicon oxide pockets is recessed relative to a surface of the silicon nitride patterned layer.

15. The semiconductor structure of claim 10, wherein the layer of conformal oxide is formed by re-oxidizing the dished silicon nitride patterned layer.

16. The semiconductor structure of claim 10, further comprising a layer of semiconductor material bonded to the layer of conformal oxide.

17. The semiconductor structure of claim 16, wherein the layer of semiconductor material comprises a patterned layer including at least one region forming at least a portion of at least one active device.

18. The semiconductor structure of claim 16, wherein the layer of semiconductor material comprises a layer of silicon.

19. A photonic device comprising a semiconductor structure according to claim 10.

20. The semiconductor structure of claim 1, wherein the bonding interface includes a surface roughness of below about 5 Å rms.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The method disclosed herein is explained in more detail hereafter using advantageous exemplary embodiments in conjunction with the accompanying figures, wherein:

[0032] FIG. 1 schematically illustrates steps of a method for manufacturing a semiconductor structure according to a first exemplary embodiment of the present disclosure;

[0033] FIG. 2 schematically illustrates a silicon nitride patterned structure manufactured according to a second exemplary embodiment of the present disclosure;

[0034] FIG. 3 schematically illustrates a step of providing a donor substrate in view of carrying out a layer transfer onto any one of the structures provided in the embodiments illustrated in FIGS. 1 and 2; and

[0035] FIG. 4 schematically illustrates steps of transferring a layer from the donor substrate illustrated in FIG. 3 onto any one of the structures provided in the embodiments illustrated in FIGS. 1 and 2, in a third exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

[0036] In the following description of exemplary embodiments of the present disclosure, the same reference signs can be used to designate the same features throughout the different embodiments. Furthermore, in some embodiments, the description of features described in previous embodiments may be omitted.

[0037] Steps of a method for manufacturing a semiconductor structure according to the present disclosure will now be described in a first exemplary embodiment with reference to FIG. 1.

[0038] As illustrated in step (A) of FIG. 1, a silicon nitride patterned layer 102 is provided on or over a carrier substrate 101, which form together a silicon nitride patterned structure 100. Silicon nitride (SiN), which is a preferred material for photonic applications, can be used but other nitride-based materials or semiconductor materials could also be suitable depending on the applications.

[0039] The silicon nitride (SiN) patterned layer 102 of the first embodiment can be provided as a passive photonic structure. Thus, the SiN patterned layer 102 can comprise patterns, or the like, which may have been formed using, for instance, one or more etching steps with corresponding masks. Other embodiments could relate to patterns present in the gate stack of a transistor, or the like. One or more annealing steps can be used at this point or later, as appropriate, for strengthening the SiN patterned layer 102 depending on the desired applications.

[0040] Further, in the first embodiment, the carrier substrate 101 is a silicon wafer, but other materials could be used in different embodiments also depending on the intended applications. The assembly between the carrier substrate 101 and the SiN patterned layer 102 can be realized, for instance, using an intermediate oxide layer, e.g., SiO.sub.2 or the like (not illustrated), an adhesive layer, or other appropriate well-known methods.

[0041] As illustrated in step (B) of FIG. 1, in a subsequent step, a first layer of a conformal oxide 103 is provided on the SiN patterned layer 102, in particular, directly thereon, and such that it fully covers the SiN patterned layer 102, preferably over the entire diameter of the underlying Si wafer 101. In this embodiment, the first layer of conformal oxide 103 is stopped at a height of about 1.5 times the thickness of the SiN patterned layer 102. Thus, as also illustrated, the conformal oxide is also provided in-between the (STI) patterns of the SiN patterned layer 102. Because of the patterns of the SiN patterned layer 102, the first layer of conformal oxide 103 display corresponding surface irregularities and/or roughness.

[0042] In the first embodiment, a conformal oxide can be silicon dioxide (SiO.sub.2), such that the first layer of conformal oxide 103 can also be referred to as the first SiO.sub.2 layer 103 or simply the SiO.sub.2 layer 103 hereafter, and the first SiO.sub.2 layer 103 is provided on the SiN patterned layer 102 by chemical vapor deposition (CVD), in particular, high-density plasma chemical vapor deposition (HDP CVD), although other known methods and/or oxides may be used in other embodiments.

[0043] As illustrated in step (C) of FIG. 1, in a subsequent step, the SiO.sub.2 layer 103 is planarized to a predetermined thickness above the SiN patterned layer 102, thereby forming a planarizing SiO.sub.2 layer 103′. In the first embodiment, the planarizing SiO.sub.2 layer 103′ is formed using a step of chemical-mechanical planarization (CMP). In variants of this embodiment or in other embodiments of the inventive method, well-known planarizing methods other than CMP could be used, and/or the height of the planarizing SiO.sub.2 layer 103′ above the SiN patterned layer 102 could be about 100 nm or even less.

[0044] As mentioned above, at this point, the planarizing SiO.sub.2 layer 103′ hardly meets the very strict requirements regarding the thickness uniformity that are needed for photonic applications.

[0045] Thus, as illustrated in step (D) of FIG. 1, according to the present disclosure, after realizing the planarizing SiO.sub.2 layer 103′, a step of clearing the SiN patterned layer 102, in other words, the removal of the planarizing SiO.sub.2 layer 103′ on top of the SiN patterned layer 102, is carried out in order to improve the planarity of the exposed surface of the resulting structure 110 that, if desired, can subsequently be bonded, for instance, to an active photonic structure in a layer transfer process to achieve the co-integration of both passive and active structures in the same device.

[0046] In the first embodiment, the clearing of the SiN patterned layer 102 is achieved by a selective CMP of the planarizing SiO.sub.2 layer 103′, which is stopped essentially on top of the (STI) patterns of the SiN patterned layer 102, while leaving the patterns and, therefore, the SiN patterned layer 102 essentially unaffected by the selective CMP, and leaving only dished SiO.sub.2 pockets 103″ in-between the patterns of the SiN patterned layer 102, resulting in a dished silicon nitride (SiN) patterned layer 102′. In the first embodiment, this is possible by appropriately choosing the composition of the slurry to be used for the selective CMP.

[0047] In this respect, in the first embodiment, a ceria-based slurry is preferred. In particular, ceria-based slurries are preferred, which allow reaching high oxide to nitride selectivity ratios, while improving the surface roughness of the exposed surface on top of the structure 110. Thus, in the first embodiment, the slurry to be used for the selective CMP is chosen with a composition comprising one of: about 0.5 wt. % CeO.sub.2, about 0.5 wt. % CeO.sub.2 and about 0.1 wt. % picolinic acid, CeO.sub.2 and surfactant, or CeO.sub.2 and resin abrasive, which all result in a preferential removal of the oxide with minimal polishing of the silicon nitride, while also meeting the requirements of STI patterns. Indeed, in variants of the first embodiment, depending on which ceria-based slurry is used, it is possible to reach an oxide to nitride selectivity of: about 3.4 when using the slurry having a composition comprising about 0.5 wt. % CeO.sub.2; as high as about 76.6 when the slurry has the composition comprising about 0.5 wt. % CeO.sub.2 and about 0.1 wt. % picolinic acid; about 47.1 when using a slurry having a composition comprising CeO.sub.2 and surfactant; or even as high as about 124.6 when the slurry has a composition comprising CeO.sub.2 and resin abrasive.

[0048] Thus, the planarity of the exposed surface on top of the dished SiN patterned layer 102′ in the resulting structure 110 illustrated in step (D) of FIG. 1 is significantly improved in comparison to that of the structure resulting from step (C). Accordingly, if the structure 110 is co-integrated with an active photonic structure, it will result in a photonic device with improved properties compared to a photonic device manufactured using known methods.

[0049] Then, as illustrated in step (E) of FIG. 1, the first embodiment further comprises a subsequent step of providing, in particular, depositing or re-depositing, a second layer of an oxide 104, in particular, a conformal oxide, on top of the exposed surface formed by the dished SiN patterned layer 102′ with the dished SiO.sub.2 pockets 103″ in-between the patterns. In the first embodiment, the second layer of conformal oxide 104 is a layer of SiO.sub.2, but the skilled reader will appreciate that other conformal oxides may be used. Thus, in the following, the second layer of conformal oxide 104 can also be referred to as the second SiO.sub.2 layer 104 or simply the SiO.sub.2 layer 104.

[0050] Further, in the first embodiment, the second SiO.sub.2 layer 104 can be a thin layer having a thickness of less than about 50 nm, preferably less than about 20 nm, or even more preferably less than about 5 nm. The surface roughness observed for the second SiO.sub.2 layer 104 is below about 5 Å rms, such that the thickness uniformity meets the very strict requirements of photonic applications. In other words, it is possible to ensure adequate bonding of the resulting semiconductor structure 120 to a donor semiconductor structure in view of a layer transfer.

[0051] A second exemplary embodiment of the inventive method for manufacturing a semiconductor structure will now be described with reference to FIG. 2, wherein the semiconductor structure 120 resulting from the first embodiment or an analog semiconductor structure resulting from any variant of the first embodiment is prepared in view of manufacturing a co-integrated photonic device with both active and passive structures. As will become obvious hereafter, the second embodiment can be seen as a variant of the first embodiment.

[0052] As mentioned above, the step of clearing the SiN patterned layer 102 described in reference to step (D) of FIG. 1 leads to the dished SiO.sub.2 pockets 103″ in-between patterns in the dished SiN patterned layer 102′. In fact, depending on the structure of the patterns of the SiN patterned layer 102, the dishing step can also comprise an over-polishing step for the wafer edge. Further, with a ceria-based slurry having a very high oxide to nitride selectivity, it would be possible to stop the selective CMP at a desired dishing height of the dished SiN patterned layer 102′.

[0053] Furthermore, in the second embodiment, in a step that would be subsequent to step (E) illustrated in FIG. 1, a planarizing oxide layer 104′ of a conformal oxide, for instance, also SiO.sub.2, or any other suitable oxide, can be provided on top of the exposed surface formed by the dished SiN patterned layer 102′ with the dished SiO.sub.2 pockets 103″ in-between the patterns, thereby forming semiconductor structure 130. In fact, the method steps of clearing the SiN patterned layer 102 and of subsequently providing a second layer of a conformal oxide 104′, which is a conformal planarizing oxide layer, can be repeated. In particular, it is preferable that the new planarizing oxide layer 104′ is provided with a thickness of about 1.5 times the dishing height in the step of dishing. This step can be advantageous when the dishing height in the step of dishing is too high to ensure the proper bonding to a donor semiconductor structure in a layer transfer process.

[0054] Then, in a variant of the second embodiments, the second layer of conformal oxide 104 of the first embodiment could be deposited directly on top of the exposed surface formed by the dished SiN patterned layer 102′ and the dished SiO.sub.2 pockets 103″ in-between the patterns, or on top of the planarizing oxide 104′ of the structure 130. Further, in other variants, it would also be possible to further repeat the steps of clearing and providing a planarizing oxide layer 104′ to further improve the uniformity.

[0055] FIG. 2 essentially illustrates that the structure 130 obtained in the second embodiment is very similar to the structure 120 obtained in the first embodiment. Since the repeated steps of clearing the SiN patterned layer 102 and providing another conformal oxide 104, here resulting in the planarizing oxide layer 104′, are repeated, the thickness uniformity is improved even more than in the first embodiment. Thus, the dishing is not shown in FIG. 2 on purpose in order to schematically emphasize even more the improvement of uniformity obtained by the present disclosure.

[0056] A third exemplary embodiment of the inventive method for manufacturing a semiconductor structure will now be described with reference to FIGS. 3 and 4, wherein any of the structures 120, 130 resulting from any of the first or second embodiments or analog structures resulting from any variant thereof will be used in a layer transfer process, in particular, for a co-integration with an active photonic structure.

[0057] As illustrated in FIG. 3, in the third embodiment, a donor substrate 201 is provided in view of a layer transfer onto one of the structures 120, 130 obtained by one of the previous embodiments. Accordingly, a detachable semiconductor layer 202 is provided in or on the donor substrate 201. In the third embodiment, a layer transfer using the SMART CUT® technology is carried out. Thus, in the third embodiment, the detachable semiconductor layer 202 is provided by creating a weakened (splitting) layer (represented by the dashed line in FIG. 3) by ion implantation at a predetermined depth in the donor substrate 201. In variants of the third embodiment, other technologies could be used for the layer transfer, and the detachable semiconductor layer 202 could be attached in a detachable manner to the donor substrate 201, for instance, with a weak or non-permanent adhesive, or using an oxide layer, or the like.

[0058] In the third embodiment, the donor substrate is a Si bulk wafer, and the detachable semiconductor layer 202 is a Si layer. In other embodiments, the donor substrate could be a silicon wafer, a silicon-on-insulator wafer, or the like, and the detachable semiconductor layer could be a layer of a silicon-based material, or another semiconductor material.

[0059] As illustrated in step (A) of FIG. 4, the donor Si wafer 201 is bonded to one of the structures 120, 130 obtained by one of the previous embodiments (dotted lines emphasize the dished SiO.sub.2 pockets 103″). In particular, a free bonding surface of the detachable Si layer 202 to be transferred is bonded to the free bonding surface formed by one of: the second SiO.sub.2 layer 104 for the structure 120 obtained by the first embodiment or variants thereof; or the planarizing SiO.sub.2 layer 104′ for the structure 130 obtained by the second embodiment or variants thereof.

[0060] In some variants, instead of or in addition to providing the thin second SiO.sub.2 layer 104 as described above in the first or second embodiments, a layer of a conformal oxide can be provided on the free (bonding) surface of the detachable Si layer 202 that will be transferred onto the structure 120, 130 in the layer transfer process. In further variants, it would also be possible to re-oxidize the dished SiN patterned layer 102′ and/or the bonding surface of the detachable Si layer 202. In other words, in variants of this aspect of the inventive method, a bonding oxide layer can be provided on the receiver silicon nitride patterned structure, on the detachable layer of the donor substrate, or on both, depending on the desired strength of the bonding.

[0061] In some variants, the detachable semiconductor layer 202 can be of silicon and the bonding layer on the detachable semiconductor layer 202 can be obtained by thermal oxidation of the detachable semiconductor layer 202. This is advantageous because thermal oxidation leads to much higher uniformity, such as, for instance, oxide deposition.

[0062] Thus, in variants of the third embodiment, the combined thickness of the last deposited layer of conformal oxide, namely the second SiO.sub.2 layer 104 when following variants of the first embodiment or the last deposited planarizing SiO.sub.2 layer 104′ when following variants of the second embodiment, above the dished SiN patterned layer 102′ and of the bonding layer can preferably be in the range from about 50 nm to about 300 nm, while respecting a high uniformity at the bonding interface. A very low thickness of deposited oxide on the dished SiN patterned layer 102′ can be combined with a certain thickness of a thermal oxide used for the bonding layer to ensure such uniformity at the bonding interface, thereby providing high bonding strength. For photonic devices, this leads to a substantially perfect coupling between the SiN waveguides and the active devices in the detachable semiconductor layer 202.

[0063] Then, as illustrated in step (B) of FIG. 4, the remainder or handle portion of the donor Si wafer 201 is detached, in particular, following a heat treatment in a layer transfer by SMART CUT® technology, such that the detachable Si layer 202 is now transferred onto the dished SiN patterned layer 102′ with the second SiO.sub.2 layer 104 (or 104′) with improved planarity and thickness uniformity, forming the co-integrated semiconductor structure 140. Further surface treatment steps (grinding, etching, planarization, polishing, etc.) can then be carried out on the transferred Si layer 202 depending on the intended use of the semiconductor structure 140.

[0064] In variants of the third embodiment, instead of transferring the layer by a splitting technology such as the SMART CUT® technology, it would also be possible to remove the remainder or handle portion of the donor substrate, for instance, by grinding with or without CMP planarization steps, or any other known suitable method.

[0065] Further, the Si layer 202 can be patterned, in particular, into an active device, for instance, using one or more etching and masking steps. The patterning of the Si layer 202, as well as optional strengthening annealing steps, can be carried out before and/or after the layer transfer. In any case, the skilled reader will appreciate that the inventive method facilitates the co-integration of passive and active structures.

[0066] As a consequence, when the silicon nitride patterned layer, here the SiN patterned layer 102, forms a passive device, in particular, a passive photonic structure, and the transferred layer, here the Si layer 202, forms an active device, in particular, an active photonic structure, the resulting co-integrated semiconductor structure 140 can be used for photonic applications. For instance, electrical connections could be added in further method steps in order to realize a photonic circuit. Given the advantages resulting of the inventive manufacturing method, a photonic device such as the semiconductor structure 140 or using the same will have improved properties with respect to an analog device manufactured by known methods. In particular, the bonding strength and the coupling between the passive and the active structures is improved in comparison to the prior art.

[0067] Finally, the skilled reader will appreciate that the embodiments described above are merely illustrative of the concepts underlying the present disclosure, and that further embodiments may deviate from the examples given above without, however, deviating from the scope of the present disclosure. In particular, the various embodiments of the present disclosure described above and/or their variants can also be combined with each other to form further embodiments still within the scope of the present disclosure.