CIRCUIT BOARD AND ELECTRONIC DEVICE

Abstract

Provided is a circuit board which includes a semiconductor substrate, a Zener diode, and a first vertical conductor and a second vertical conductor which configure a paired current path, wherein in the Zener diode, an N-type semiconductor region and a P-type semiconductor region being composed of the semiconductor substrate, with a PN junction extending in the thickness direction of the semiconductor substrate; and the first vertical conductor and the second vertical conductor penetrating the semiconductor substrate in the thickness direction, the first vertical conductor being brought into contact with the N-type semiconductor region, and the second vertical conductor being brought into contact with the P-type semiconductor region.

Claims

1. A circuit board comprising: a semiconductor substrate, a Zener diode including a PN junction comprising an N-type semiconductor region and a P-type semiconductor region in the semiconductor substrate, and a first vertical conductor and a second vertical conductor each formed in the semiconductor substrate and configure to form a paired current path, the first and second vertical conductors penetrating the semiconductor substrate in a thickness direction, the N-type semiconductor region and the P-type semiconductor region being formed from the one surface of the semiconductor substrate to another surface of the semiconductor substrate and configured to surround the first vertical conductor and the second vertical conductor, the PN junction extending in the thickness direction of the semiconductor substrate and being formed in a three-dimensional structure surrounding either the first vertical conductor or the second vertical conductor, one of the N-type semiconductor region and the P-type semiconductor region, which surrounds one of the first and second vertical conductors, is formed in a columnar shape so as to extend in the thickness direction of the semiconductor substrate, and one of the first and second vertical conductors being brought into contact with the N-type semiconductor region of the PN junction in the semiconductor substrate, and the other of the first and second vertical conductors being brought into contact with the P-type semiconductor region of the PN junction in the semiconductor substrate.

2. The circuit board according to claim 1, wherein the first vertical conductor and the second vertical conductor penetrate the N-type semiconductor region or the P-type semiconductor region.

3. An electronic device comprising: the circuit board of claim 1; and a semiconductor device, the semiconductor device being mounted on the circuit board, and electrically connected to respective ends of the first and second vertical conductors.

4. An electronic device comprising: the circuit board of claim 2; and a semiconductor device, the semiconductor device being mounted on the circuit board, and electrically connected to respective ends of the first and second vertical conductors.

5. The circuit board according to claim 1, further comprising: an insulating layer surrounding the PN junction and the first and second vertical conductors and penetrating the semiconductor substrate in the thickness direction, the insulating layer electrically insulating an inner area of the semiconductor substrate surrounded by the insulating layer from an outside area of the insulating layer.

6. The circuit board according to claim 5, further comprising: at least a pair of third and fourth vertical conductors penetrating the semiconductor substrate in the thickness direction; and additional insulating layers penetrating the semiconductor substrate in the thickness direction, and respectively surrounding each of the third and fourth vertical conductors.

7. The circuit board according to claim 5, wherein the insulating layer is ring-shaped in plan view.

8. The circuit board according to claim 6, wherein each of the insulating layers is ring-shaped in plan view.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a cross-sectional view illustrating a part of a circuit board according to this invention.

[0025] FIG. 2 is a circuit diagram of the circuit board illustrated in FIG. 1.

[0026] FIG. 3 is a partial cross-sectional view of an electronic device using the circuit board illustrated in FIG. 1 and FIG. 2.

[0027] FIG. 4 is a circuit diagram of the electronic device illustrated in FIG. 3.

[0028] FIG. 5 is a partial cross-sectional view of another embodiment of the circuit board according to this invention.

[0029] FIG. 6 is a partial plan view illustrating still another embodiment of the circuit board according to this invention.

[0030] FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 6.

[0031] FIG. 8 is a partial plan view illustrating still another embodiment of the circuit board according to this invention.

[0032] FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. 8.

[0033] FIG. 10 is a drawing illustrating another embodiment of the electronic device according to this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In FIG. 1 to FIG. 10, all identical constituents are given the same or similar reference signs. First, referring to FIG. 1 and FIG. 2, the circuit board according to this invention includes a semiconductor substrate 1, a Zener diode ZD (see FIG. 2), and a first vertical conductor 31 and a second vertical conductor 32 which configure a paired current path. On both surfaces of the semiconductor substrate 1, aligned normal to the direction of the thickness thereof, there are formed insulating films 51, 52. Each of the insulating films 51, 52 is preferably a stacked film of a SiO.sub.2 film and a SiN film. With this configuration, the obtainable insulating film structure will have large adhesion strength and good electric insulation property.

[0035] The semiconductor substrate 1 has a shape of flat plate, and is a wafer, or a chip cut out from the wafer. The semiconductor substrate 1 may be composed of silicon (Si), germanium (Ge) or the like, or may be composed of a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC) or the like. Among them, silicon substrate is preferable. The silicon substrate is costless, has a long-term operation experience as the semiconductor substrate 1, and is highly reliable. There is, however, no intention to exclude any other semiconductor substrates including compound semiconductor substrate and so forth.

[0036] In the Zener diode ZD, a P-type semiconductor region 111 and an N-type semiconductor region 112 are composed of the semiconductor substrate 1. A PN junction 113 thereof extends in the thickness direction of the semiconductor substrate 1. A technique of forming the N-type semiconductor region 112 and the P-type semiconductor region 111 in the semiconductor substrate 1, made of a silicon substrate, is well known. For example, doping of pentavalent phosphorus or arsenic into tetravalent silicon will produce the N-type semiconductor region 112, whereas doping of trivalent boron will produce the P-type semiconductor region 111. The N-type semiconductor region 112 and the P-type semiconductor region 111 are respectively composed of high concentration N-type semiconductor and high concentration P-type semiconductor, with high doses of the impurities exemplified above. In this embodiment, the N-type semiconductor region 112 has an arbitrary columnar shape having a circular, polygonal or other cross-sections, and the P-type semiconductor region 111 spreads around it.

[0037] The first vertical conductor 31 and the second vertical conductor 32 which configure the paired current path penetrate the semiconductor substrate 1 in the thickness direction. More specifically, the first vertical conductor 31 is brought into contact with the N-type semiconductor region 112, meanwhile the second vertical conductor 32 is brought into contact with the P-type semiconductor region 111. While the first vertical conductor 31 and the second vertical conductor 32 may be formed by plating, they are more preferably formed by a molten metal filling method by which a molten metal is poured into holes formed in the semiconductor substrate 1, or, by a metal/alloy dispersion filling method by which a metal/alloy dispersion system composed of a metal/alloy fine powder dispersed in a dispersion medium is poured, since these methods can significantly reduce the cost. When the molten metal filling method or the metal/alloy dispersion filling method is employed, the differential pressure filling may be carried out, in such a way that the semiconductor substrate 1 is placed in a vacuum chamber, the chamber is evacuated to reduce the pressure, a conductor material is allowed to flow so as to fill the holes, and the inner pressure of the vacuum chamber is increased again.

[0038] In this embodiment, the semiconductor substrate 1 is a high concentration P-type semiconductor substrate, and the high concentration N-type semiconductor region 112 having a columnar form is provided so as to extend through the P-type semiconductor substrate 1 in the thickness direction. Of the first vertical conductor 31 and the second vertical conductor 32, the first vertical conductor 31 passes through the N-type semiconductor region 112, meanwhile the second vertical conductor 32 passes through the high concentration P-type semiconductor substrate 1. This structure appears as a simple TSV structure having the first vertical conductor 31 and the second vertical conductor 32 allowed to penetrate the silicon substrate 1 in the thickness direction, and can therefore maximize advantages of the TSV structure.

[0039] In the Zener diode ZD, the N-type semiconductor region 112 and the P-type semiconductor region 111 are composed of the semiconductor substrate 1. Accordingly, the Zener diode ZD may be formed by a typical semiconductor process, such as a process of doping an impurity into the semiconductor substrate 1 composed of a silicon substrate. Therefore, it becomes possible to obtain a thin circuit board having the Zener diode formed in the semiconductor substrate per se, unlike the case where the Zener diode ZD is mounted on the surface of the semiconductor substrate 1.

[0040] In the Zener diode ZD in this invention, the PN junction 113 extends in the thickness direction of the semiconductor substrate 1. To the thus-configured Zener diode ZD, the first vertical conductor 31 and second vertical conductor 32, which penetrate the semiconductor substrate 1 in the thickness direction, are provided so that the first vertical conductor 31 comes into contact with the N-type semiconductor region 112, and that the second vertical conductor 32 comes into contact with the P-type semiconductor region 111. In this way, there is obtained a circuit board in which the Zener diode ZD composed of the semiconductor substrate 1 is connected between the first vertical conductor 31 and the second vertical conductor 32 which configure the paired current path.

[0041] More specifically, the first vertical conductor 31 and the second vertical conductor 32 penetrate the N-type semiconductor region 112 or P-type semiconductor region 111. With such configuration, the PN junction 113 will have a three-dimensional structure having the X-dimension and Y-dimension defined around the first vertical conductor 31 and second vertical conductor 32, assuming the XY plane on the surface of the semiconductor substrate 1, and the Z-dimension defined in the thickness direction of the semiconductor substrate 1. This three-dimensional structure successfully protects the PN junction from damage or breakdown due to spike noise or impulse noise, induced by static electricity or thunder stroke.

[0042] The circuit board of this invention is combined, as illustrated in FIG. 3, with a semiconductor device to configure an electronic device. The semiconductor device 9 is mounted on the circuit board, and is electrically connected to one ends of the first vertical conductor 31 and the second vertical conductor 32. FIG. 3 and FIG. 4 illustrate an exemplary case where a light emitting diode 9 is used as the semiconductor device 9. An anode terminal 91 of the light emitting diode 9 is connected to a power terminal 721 of the first vertical conductor 31 which serves as the cathode of the Zener diode ZD, meanwhile a cathode terminal 92 of the light emitting diode 9 is connected to a ground terminal 722 of the second vertical conductor 32. Source voltage Vcc is applied to a power terminal 711 of the first vertical conductor 31, which resides opposite the power terminal 721. The source voltage Vcc is made constant by a voltage stabilizing function of the Zener diode ZD, and the constant voltage is applied to the light emitting diode 9.

[0043] When a noise largely exceeding the breakdown voltage of the Zener diode ZD, such as spike noise or impulse noise, were applied between the first vertical conductor 31 and the second vertical conductor 32, the Zener diode turns ON.

[0044] Accordingly, even if spike noise or impulse noise should come in, only a voltage equivalent to the breakdown voltage of the Zener diode ZD is applied to the light emitting device 9 (semiconductor device), so that the light emitting diode 9 will successfully be protected from the spike noise or impulse noise.

[0045] FIG. 5 illustrates another embodiment of the circuit board according to this invention. In this embodiment, unlike the circuit boards illustrated in FIG. 1 to FIG. 4, the semiconductor substrate 1 is an N-type silicon substrate, and the P-type semiconductor region 111 having a columnar form is provided so as to extend through the N-type semiconductor substrate in the thickness direction. Of the first vertical conductor 31 and the second vertical conductor 32 which configure the paired current path, the first vertical conductor 31 passes through the N-type semiconductor substrate 112, meanwhile the second vertical conductor 32 passes through the P-type semiconductor region 111. Also this structure appears as a simple TSV structure having the first vertical conductor 31 and the second vertical conductor 32 allowed to penetrate the silicon substrate in the thickness direction, and can therefore maximize advantages of the TSV structure.

[0046] FIG. 6 and FIG. 7 illustrate still another embodiment of the circuit board according to this invention. This embodiment contains a plurality of pairs of vertical conductors (Q11, Q12) to (Q31, Q32), each containing the paired first vertical conductor 31 and second vertical conductor 32, wherein the individual pairs are arranged so as to be spaced from each other in plane on the semiconductor substrate. The individual pairs (Q11, Q12) to (Q31, Q32) are configured so that the first vertical conductor 31, the second vertical conductor 32, the N-type semiconductor region 112 and the P-type semiconductor region 111 are respectively surrounded by ring-patterned insulating layers 531 to 552. In this way, among the individual pairs (Q11, Q12) to (Q31, Q32), mutual interference of the first vertical conductor 31, the second vertical conductor 32, the N-type semiconductor region 112 and the P-type semiconductor region 111 are avoidable. Same as the insulating films 51, 52, each of the insulating layers 531 to 552 may be a stacked film of a SiO.sub.2 film and a SiN film, or may be a cured product of an insulating paste which contains a Si particle and a liquid organic Si compound, filled and then cured in grooves, holes or the like formed in the semiconductor substrate 1 in the thickness direction.

[0047] FIG. 8 and FIG. 9 illustrate even another embodiment of the circuit board according to this invention. This embodiment contains a plurality of pairs of vertical conductors (Q11 to Q32), each containing the paired first vertical conductor 31 and second vertical conductor 32, wherein the individual pairs are arranged so as to be spaced from each other in plane on the semiconductor substrate. Of the individual pairs (Q11 to Q32), each of the pairs (Q11, Q21, Q31) is configured so that the first vertical conductor 31, the second vertical conductor 32, the N-type semiconductor region 112 and the P-type semiconductor region 111 are surrounded by ring-patterned insulating layers 531, 541, 551.

[0048] Meanwhile, in each of the pairs (Q12, Q22, Q32), the first vertical conductor 31 is surrounded by an insulating layer 113, and the second vertical conductor 32 is surrounded by an insulating layer 114.

[0049] Same as the insulating films 51, 52, each of the insulating layers 113, 114 may be a stacked film of a SiO.sub.2 film and a SiN film, or may be a cured product of an insulating paste which contains a Si particle and a liquid organic Si compound, filled and then cured in grooves, holes or the like formed in the semiconductor substrate 1 in the thickness direction.

[0050] Each of the circuit boards illustrated in FIG. 6 to FIG. 9 may be used typically as a constituent of a three-dimensionally stacked electronic device illustrated in FIG. 10. The three-dimensionally stacked electronic device illustrated in FIG. 10 is configured so that, on an interposer 13 having a ball grid 15, a stack 17 of a plurality of semiconductor chips 171 to 175 is mounted. Quantity of the semiconductor chips 171 to 175 is arbitrary. The circuit board according to this invention is applicable not only to the interposer 13, but also to the semiconductor chips 171 to 175. The semiconductor chips 171 to 175 include a wide variety of electronic parts which are labile to spike noise or impulse noise, as a result of incorporation of semiconductor elements such as system LSI, memory LSI, logic circuit, memory circuit, sensor module or photoelectric module.

[0051] As described previously, according to this invention, there is provided a circuit board which is well adapted to TSV devices strongly oriented to thinning and high-density mounting, and an electronic device using the same.

[0052] This invention has been described above in detail with reference to, but not limited to, preferred embodiments. It is, however, obvious that those skilled in the art could devise various modifications of the invention based on the technical concepts underlying the invention and teachings disclosed herein.