Digital down converter with equalization

Abstract

A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

Claims

1. A digital down converter comprising: A. an analog to digital converter (ADC) having: an ADC signal input for receiving an applied analog signal characterized by a carrier frequency F.sub.c, an ADC sampling clock input for receiving an applied ADC sampling clock signal characterized by a sampling rate F.sub.s, and an ADC output, wherein the ADC is responsive to the applied analog signal and the ADC sampling clock signal to provide at the ADC output, an ADC digital signal representative of the applied analog signal, wherein the ADC is a composite ADC including a plurality P of interleaved sub-ADCs, and wherein each sub-ADC is characterized by an associated amplitude response and an associated phase response, B. a bus receiver having an input configured to receive the ADC digital signal at the sampling rate F.sub.s, and including an M-line bus output characterized by an operating clock frequency F.sub.o, where M=F.sub.s/F.sub.o, C. a mixers unit having an input connected to the respective M lines of the bus output, and configured to receive M cosine signals at frequency F.sub.c, and M sine signals at frequency F.sub.c, wherein the mixers unit is configured to multiply (i) the signals on the respective M lines of the bus output by the M cosine signals, and apply resultant cosine output signals 1.sub.c, . . . , M.sub.c to a first M of the 2M outputs, and (ii) the signals on the respective M lines of the bus output by the M sine signals, and apply resultant sine output signals 1.sub.s, . . . , M.sub.s to a second M of the 2M outputs, D. a first samples distributor and a second samples distributor, each of the samples distributors having M inputs and K outputs, wherein: (i) the number K of distributor outputs equals the ratio of the sample rate of baseband signals B to the operating clock frequency F.sub.o, (ii) each of the K outputs is an L-lines bus clocked at frequency F.sub.o, (iii) the M inputs of the first samples distributor are configured to receive from the mixer unit the respective cosine output sample signals 1.sub.c, . . . , M.sub.c, to transform those samples signals into words B.sub.1c, . . . , B.sub.Kc with the length of L samples each, and to apply said words B.sub.1c, . . . , B.sub.Kc at the respective K first samples distributor outputs, (iv) the M inputs of the second samples distributor are configured to receive from the mixer unit the respective sine output samples signals 1.sub.s, . . . , M.sub.s, to transform those sample signal into words B.sub.1s, . . . , B.sub.Ks with the length of L samples each, and to apply said words B.sub.1s, . . . , B.sub.Ks at the respective K second samples distributor outputs, E. K processing units operating in parallel, (i) wherein each of the processing units has an input I and an input Q, (ii) wherein for each processing unit, input I is connected to a corresponding output of the first samples distributor, and input Q is connected to a corresponding output of the second samples distributor, (iii) whereby pairs of samples applied to the input I and to the input Q form a complex valued sample for calculation of a convolution with the coefficients stored in the coefficients memory of the processing unit.

2. A digital down converter in accordance with the claim 1, wherein each of the processing units comprises: an arithmetic unit II having an input and an output, an arithmetic unit IQ having an input and an output, an arithmetic unit QI having an input and an output, an arithmetic unit QQ having an input and an output, a subtractor having a first input, a second input and an output, and an adder having a first input, a second input and an output, wherein: a. the inputs of arithmetic unit II and arithmetic unit IQ are joined together and configured to receive an input I from the processing unit; b. the inputs of arithmetic unit QI and arithmetic unit QQ are joined together and configured to receive an input Q from the processing unit; c. the subtractor is responsive to a value representative of a sample applied to its first input and a value representative of a sample applied to its second input, and to apply a resulting difference signal at its output; d. the output of the arithmetic unit II is connected to the first input of the subtractor, and the output of the arithmetic unit QI is connected to the second input of the subtractor; e. the output of the arithmetic unit IQ is connected to the first input of the adder, and the output of the arithmetic unit QI is connected to second input of the adder, whereby the adder produces at its output, a sum of the samples coming to its inputs; f. the output of the subtractor provides an output I of the processing unit and the output of the adder provides an output Q of the processing unit.

3. A digital down converter in accordance with claim 2, wherein each arithmetic unit comprises: i. L multipliers, wherein each multiplier has two inputs and an output and generates at its output, a product of signals at the two inputs, ii. an adder having L inputs and one output, wherein the adder generates at its output, a signal representative of sum of signals at the L inputs, iii. a convolution coefficients memory having L outputs, and adapted for storing plurality of L-convolution coefficient values and selectively applying the L convolution coefficient values to the L outputs, wherein one input of each multiplier is configured to receive a corresponding input of the arithmetic unit, the other input of each multiplier is configured to receive an associated one of the convolution coefficient values from the convolution coefficient memory, and the outputs of the L multipliers are applied to the respective inputs of the adder.

4. A digital down converter in accordance with claim 3, wherein the convolution coefficients stored in the coefficients memory include P sets, each set comprising L convolution coefficients, and wherein the number P is equal to the number of the sub-ADCs in the composite ADC.

5. A digital down converter with equalization of claim 4, wherein the convolution coefficients comprise a family of solutions of a set of linear equations systems $\underset{k=0}{\overset{L-1}{.Math.}}C\left(p,k\right).Math.H_p\left(F\right).Math.\exp (j.Math.2.Math.\left(F_m-F_c\right)/F_s.Math.\left(L/2-k\right)=T\left(F_m\right),$ where C(p,k) is a set of convolution coefficients, p is the number of a convolution coefficient set, and k is the number of a convolution coefficient in the set, H.sub.p(F) is a complex frequency response of a sub-ADC with the number p in the composite ADC, and F.sub.m is one of L frequencies where a frequency response of the down converter coincides with a target frequency response T(F).

6. A digital down converter in accordance with claim 5, wherein a target frequency response T(F) includes a frequency response of a low pass filter suppressing out of band components.

7. A digital down converter in accordance with claim 6, wherein a target frequency response T(F) includes a frequency response of a low pass filter that meets Nyquist ISI criterion.

8. A digital down converter comprising: A. an analog to digital converter (ADC) having: an ADC signal input for receiving an applied analog signal characterized by a carrier frequency F.sub.c, an ADC sampling clock input for receiving an applied ADC sampling clock signal characterized by a sampling rate F.sub.s, and an ADC output, wherein the ADC is responsive to the applied analog signal and the ADC sampling clock signal to provide at the ADC output, an ADC digital signal representative of the applied analog signal, wherein the ADC is a composite ADC including a plurality P of interleaved sub-ADCs, and wherein each sub-ADC is characterized by an associated amplitude response and an associated phase response, B. a bus receiver having an input configured to receive the ADC digital signal at the sampling rate F.sub.s, and including an M-lines bus output characterized by an operating clock frequency F.sub.o, where M=F.sub.s/F.sub.o, C. a samples distributor having M inputs and K outputs, wherein: (i) the number K of distributor outputs equals the ratio of the sample rate of baseband signals B to the operating clock frequency F.sub.o, (ii) each of the K outputs is an L-lines bus clocked at frequency F.sub.o, (iii) the M inputs of the samples distributor are configured to receive the output signals from the M-lines bus of the bus receiver, to transform those samples signals into words B.sub.1, . . . , B.sub.K with the length of L samples each, and to apply said words B.sub.1, . . . , B.sub.K at the respective K samples distributor outputs, D. K processing units operating in parallel, wherein each processing unit includes an input and an output, wherein the inputs of the K processing units are connected to respective outputs of the samples distributor, wherein each processing unit configured to calculate a convolution of L input samples with L coefficients stored in the coefficients memory.

9. A digital down converter in accordance with claim 8, wherein each of the processing units comprises: an arithmetic unit II having an input and an output, an arithmetic unit IQ having an input and an output, an arithmetic unit QI having an input and an output, an arithmetic unit QQ having an input and an output, a subtractor having a first input, a second input and an output, and an adder having a first input, a second input and an output, and wherein: a. the inputs of arithmetic unit II, arithmetic unit IQ, arithmetic unit QI and arithmetic unit QQ are joined together and configured to receive an input from the processing unit; b. the subtractor is responsive to a value representative of a sample applied to its first input and a value representative of a sample applied to its second input, and to apply a resulting difference signal at its output; c. the output of the arithmetic unit II is connected to the first input of the subtractor, and the output of the arithmetic unit QI is connected to the second input of the subtractor; d. the output of the arithmetic unit IQ is connected to the first input of the adder, and the output of the arithmetic unit QI is connected to second input of the adder, whereby the adder produces at its output, a sum of the samples coming to its input, and e. the output of the subtractor provides an output I of the processing unit and the output of the adder provides an output Q of the processing unit.

10. A digital down converter in accordance with claim 9, wherein the convolution coefficients are products of C(p,k) and exp(j.Math.2.Math.F.sub.c/F.sub.s.Math.n), where n is a number of a sample, quantities C(p,k) comprise a family of solutions of the foregoing set of linear equations, p is the number of a convolution coefficient set, and k is the number of a convolution coefficient in the set.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a conventional block diagram of a digital down converter with equalization

PRIOR ART

(2) FIG. 2 shows an improved block diagram of a digital down converter with equalization (prior art).

(3) FIG. 3 shows a block diagram of the first embodiment of the present invention, and FIG. 3A shows a block diagram of an exemplary composite ADC of that embodiment.

(4) FIG. 4 shows a block diagram of an exemplary processing unit of the first embodiment of the present invention.

(5) FIG. 5 shows a block diagram of an exemplary arithmetic unit of a processing unit of FIG. 4.

(6) FIG. 6 shows a block diagram of a digital down converter with equalization according another exemplary embodiment of the present invention.

(7) FIG. 7 shows a block diagram of an exemplary processing unit of the embodiment of FIG. 7.

(8) FIGS. 8A and 8B show constellation diagrams for a signal at the output of a down converter without equalization and with equalization of the invention.

DETAILED DESCRIPTION

(9) A block diagram of a first embodiment of a digital down converter 10 is shown in FIG. 3. The block diagram of FIG. 3 comprises a high speed composite ADC 31, connected by a bus receiver 41 to a mixers unit 42, two samples distributors 43 and K processing units 34 configured to operate in parallel. As described above, in a form, composite ADCs consist of a number of interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude and phase frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, the appearance of spurious frequency components. FIG. 3A shows a block diagram of the exemplary high speed composite ADC 31, including P sub-ADCs: sub-ADC #1, sub-ADC #2, . . . . , sub-ADC #p. In FIG. 3A, an ADC input 30 receives an input analog signal, with a carrier frequency F.sub.c, which is applied to the inputs of sub-ADC #1, sub-ADC #2, . . . , sub-ADC #p. An ADC sampling clock input of ADC 31 receives an ADC sampling clock signal at sampling frequency F.sub.s. The ADC sampling clock signal is split by a clock timing sequencer into separate sequential clock signals, each of which is applied to a respective one of the P sub-ADCs to effect the interleaved operation of the sub-ADCs. The sub-ADCs are responsive to the applied analog signal and the ADC sequential clock signals to provide at an ADC output bus 32, an ADC signal representative of the applied analog signal.

(10) An analog input signal on input line 30 is converted by ADC 31 into a high speed digital signal with a sampling rate F.sub.s. The data from the ADC 31 are transmitted to the following units through bus 32, which preferably is a certain type, for example, LVDC or Serializer/Deserializer (SerDes), although other types can be used. The bus receiver 41 divides the input data stream into M=F.sub.s/F.sub.o lines, each line having data frequency F.sub.o, equal to the operation frequency of the apparatus.

(11) The lines from bus receiver 41 are applied to the inputs of the mixers unit 42. At mixers unit 42, the sample with a number n, which arrived over one of the lines, is multiplied by cos (2.Math.F.sub.c/F.sub.s.Math.n) and simultaneously by sin (2.Math.F.sub.c/F.sub.s.Math.n). The two products are placed at the corresponding outputs 1.sub.c, . . . , M.sub.c and 1.sub.s, . . . , M.sub.s, of the mixers unit 42, wherein the number of outputs is 2.Math.M.

(12) The outputs of the mixers unit 42 are connected to the inputs of a pair of samples distributors 43 by cosine lines 1.sub.c, . . . , M.sub.c and sine lines 1.sub.s, . . . , M.sub.s. During a period of the frequency F.sub.o, each of the samples distributors 43 receives M samples. A buffer register, incorporated in the samples distributor 43, delays each input sample by one period of the frequency F.sub.o. In that way, a second set of M samples is created. The incoming samples and the delayed samples together form a set of 2M samples, wherein those samples are numbered in accordance with the order of appearance in the input signal.

(13) The number of outputs, K, of each of the samples distributor 43, equals the ratio B/F.sub.o, where B is the sampling rate of the baseband signals at the outputs of the down converter. The ratio of the ADC sampling rate Fs to the sampling rate of the baseband signals at the outputs of the down converter B is called the decimation factor DF.

(14) The samples distributor 43 produces at the output with the number i (0i<K) a word W.sub.i according to a rule: W.sub.i={S.sub.i.Math.DF, S.sub.i.Math.DF+1, . . . , S.sub.i.Math.DF+L1}, where S.sub.m is a sample with the number m from the set of 2M samples. In the samples distributor 43, which is connected to the mixers unit 42 by the cosine lines, the produced word W.sub.i is placed on a bus labeled B.sub.ic, whereas in the samples distributor 43, which is connected to the mixers unit 42 by the sine lines, the produced word W.sub.i is placed on a bus labeled B.sub.is. The number of samples in a word W.sub.i equals L, therefore the number of lines in each output bus of the samples distributors 43 equals L also.

(15) The output bus of the samples distributor 43 with a number i, is connected to one of K processing units 34 with the same number. The bus B.sub.ic leads to an I input of the processing unit 34 with the number i and the bus B.sub.is leads to a Q input of the processing unit 34 with the number i.

(16) The processing unit 34 with the number i processes the two words received from the samples distributors 43 and produces at its two outputs, samples I.sub.i and Q.sub.i of resulting baseband signals. The set of samples I.sub.i, 0i<K forms the output I of the down converter, and the set of samples Q.sub.i, 0i<K forms the output Q of the down converter.

(17) The samples that come to I and Q inputs of the processing unit 34 may be considered as a real and imaginary parts of a complex sample Z.sub.n, where n is the number of the sample in the initial signal produced by ADC 31. The processing unit 34 calculates the outputs samples I.sub.i and Q.sub.i as a convolution of the samples Z.sub.n with prepared-in-advance complex coefficients C.sub.p,k, which control the operation of the down converter, according to:

(18) $\mathrm{Ii}+j.Math.\mathrm{Qi}=\underset{k=0}{\overset{L-1}{.Math.}}{C}_{p,k}.Math.Z_{i+L/2-k},$
where p is the number of sub-ADC that produced the middle sample of the word W.sub.i, and k is the number of coefficient in the set of L coefficients.

(19) As can be readily appreciated, due to the arrangement of the samples distributor 35 described above, each of the processing units 34 receives at its input a set of L samples, these samples constituting a piece of the digital signal produced by ADC 31. The pieces that come to the inputs of the different K processing units 34 are spaced in the digital signal by an interval equal to the decimation factor DF. For this reason, the samples rate at the outputs of the down converter is F.sub.o.Math.K=B, which equals the rate of processed pieces succession in the digital signal.

(20) All processing units are the same, and the distinction lies in the sets of samples coming to the inputs and in the sets of coefficients loaded in them. A block diagram of a processing unit is shown in FIG. 4. This block diagram contains four arithmetic units II 52, IQ 53, QI 54 and QQ 55. The inputs of the arithmetic units II and IQ are connected together and connected to the input I of the processing unit. The inputs of the arithmetic units QI and QQ are connected together and connected to the input Q of the processing unit. A subtractor 56 forms output I of the processing unit as a difference between the output of the arithmetic units II 52 and the output of the arithmetic units QI 54. An adder 57 forms output Q of the processing unit as a sum of the output of the arithmetic units IQ 53 and the output of the arithmetic units QQ 55.

(21) The equalization of the sub-ADCs misalignment in a composite ADC requires the use of P sets of coefficients C.sub.p,k, a set containing L coefficients. The number p of a set (0p<P) equals the number of sub-ADC that produced processed sample.

(22) The block diagram of the processing unit is a conventional block diagram of a complex filter. The operation of a processing unit is controlled by an assembly of sets of complex coefficients {C.sub.p,k} that are loaded into it. The real parts of the of complex coefficients D.sub.p,k=Re(C.sub.p,k) are loaded into the direct branches of the processing unitinto the arithmetic units 52 and 55. The imaginary parts of the of complex coefficients E.sub.p,k=Im(C.sub.p,k) are loaded into the cross branches of the processing unitinto the arithmetic units 53 and 54.

(23) A block diagram of an exemplary arithmetic unit 34 is shown in the FIG. 5. A set of L samples arrives at the inputs 0, 1, . . . , L1 of the arithmetic unit. Each sample passes to an input of a corresponding multiplier 61, the second input of which is connected to the coefficients memory 60. The multiplier produces at its output, a product of the sample and the corresponding coefficient. The outputs of all multipliers are connected to the inputs of an adder 62 that calculates the sum of products that have come from the multipliers. In that way, a convolution of the input set of L samples with the coefficients, coming from the coefficients memory, is formed and placed at the output of the arithmetic unit.

(24) To analyze the operation of the down converter, consider that a complex exponential s.sub.0(n)=exp(j.Math.2.Math.F/F.sub.s.Math.n) is applied to the input of the ADC 31 (where n is the number of a current sample). The sample with the number n is processed by an sub-ADC with the number p=n mod(P), where P is the number of sub-ADCs in the composite ADC. If the complex frequency response of the sub-ADC with the number p is H.sub.p(F), then the output of ADC is s.sub.1(n)=H.sub.p(F).Math.exp(j.Math.2.Math.F/F.sub.s.Math.n). The multipliers in the mixers unit 34 produce two products: s.sub.1(n).Math.cos(2.Math.F.sub.c/F.sub.s.Math.n) and s.sub.1(n).Math.sin (2.Math.F.sub.c/F.sub.s.Math.n). This operation is equivalent to multiplication of the samples s.sub.1(n) by a complex exponential exp(j.Math.2.Math.Fc/F.sub.s.Math.n) and generation of a product exp(j.Math.2.Math.(FFc)/F.sub.s.Math.n). The samples distributors 43 assemble these products into words with the length L and send them to the processing units 34. The processing units 34 forms a convolution of received words with the coefficients C(p,k), so that the sample Z(n) at the output of the down converter equals

(25) $Z\left(n\right)=I+j.Math.Q=\exp \left(j.Math.2.Math.F.Math.n\right).Math.\underset{k=0}{\overset{L-1}{.Math.}}C\left(p,k\right).Math.H_p\left(F\right).Math.\exp (j.Math.2.Math.\left(F-\mathrm{Fc}\right)/F_s.Math.\left(L/2-k\right)$
and the frequency response FR(F) of the down converter equals

(26) $\mathrm{FR}\left(F\right)=\underset{k=0}{\overset{L-1}{.Math.}}C\left(p,k\right).Math.H_p\left(F\right).Math.\exp (j.Math.2.Math.\left(F-\mathrm{Fc}\right)/F_s.Math.\left(L/2-k\right).$

(27) The calculations of the coefficients C(p, k) are based on the requirement that the frequency response FR(F) of the down converter equals a target response T[F], this requirement leading to a following equation for determination of the control coefficients.

(28) $\underset{k=0}{\overset{L-1}{.Math.}}C\left(p,k\right).Math.H_p\left(F\right).Math.\exp (j.Math.2.Math.\left(F-\mathrm{Fc}\right)/F_s.Math.\left(L/2-k\right)=T\left(F\right).$

(29) Since the number of the control coefficients equals L, it is possible to ensure that the previous equation is true at L frequencies F.sub.m, 0m<L. It brings us to P systems of L linear equations each with the control coefficients as unknowns:

(30) $\underset{k=0}{\overset{L-1}{.Math.}}C\left(p,k\right).Math.H_p\left(F_m\right).Math.\exp (j.Math.2.Math.\left(F_m-\mathrm{Fc}\right)/F_s.Math.\left(L/2-k\right)=T\left(F_m\right).$

(31) The solution of the received set of P system of linear equations determines the P sets, containing each of the L control coefficients. The L control coefficients are loaded into the coefficients memory of the processing units 34 and ensure that the joint operation of ADC 31, mixers unit 42, samples distributors 43 and K processing units 34 perform a transformation of the input analog signal into I/Q baseband signals, which is completely equivalent to the transformation performed by a conventional down converter of the FIG. 1. The coefficients that are loaded into the coefficients memory of the arithmetic units II 52 and QQ 55 equal D.sub.pk=Re(C(p,k)), and the coefficients that are loaded into the coefficients memory of the arithmetic units IQ53 and QI 54 equal E.sub.pk=Im(C(p,k)).

(32) In some cases, a different design of a down converter is preferable, which may lead to further reduction of required number of multipliers. A block diagram of a corresponding exemplary embodiment of the present invention is shown in FIG. 6. This block diagram is similar to the block diagram of FIG. 3 except that the mixers unit and one of samples distributors are omitted. The frequency translation which has been performed by the mixers, is carried out now by the processing units 34 with modified control coefficients.

(33) In this exemplary embodiment of the present invention, the processing unit 34 is described by the block diagram of FIG. 7. The general view of the block diagram is the same as in FIG. 4, but the inputs of all arithmetic units 82-85 are united and used as a single input of the respective arithmetic units. The modification of the control coefficients consists of multiplication C.sub.pk by exp(2.Math.F.sub.o/F.sub.s.Math.n). It means that in the arithmetic unit II 82, coefficients are loaded which equal the D.sub.pk multiplied by cos (2.Math.F.sub.o/F.sub.s.Math.n). In the arithmetic unit IQ 83 coefficients are loaded, which equal E.sub.pk multiplied by cos (2.Math.F.sub.o/F.sub.s.Math.n). In the arithmetic unit QI 84 coefficients are loaded, which equal the E.sub.pk multiplied by sin (2.Math.F.sub.o/F.sub.s.Math.n). In the arithmetic unit QQ 85 coefficients are loaded, which equal D.sub.pk multiplied by sin(2.Math.F.sub.o/F.sub.s.Math.n).

(34) The above described method of digital down conversion with equalization, was verified using a computer simulation. In that simulation, a 16-level quadrature modulated signal was generated with sample rate 2 Gs/s. That, signal was transmitted through a square-root raised cosine filter, up-converted with a 10 GHz carrier frequency and applied to a composite ADC having 40 sub-ADCs. The 40 sub-ADC model was used to simulate ADC distortions at high frequency. The signal produced by the ADC, was down-converted using equalizer coefficients calculated with a square-root raised cosine target filter according to the present invention. The quality of the demodulated down-converted signal was estimated using an error vector magnitude (EVM) method. FIG. 8A shows a constellation diagram with the equalization turned off. In this case, error vector magnitude (EVM) exceeds 9.5%. That high EVM value is caused by spurious components which appeared because of the misalignment of the sub-ADCs, together with the distortions of the amplitude and group delay frequency responses. When the equalizer of this invention was enabled, EVM value improved to about 1.15%. (FIG. 8B).

(35) In summary, the forms of the invention illustrated in both FIG. 3 and FIG. 6, as well as other form of the invention, enable significant improvements in terms of reduction of computational burden for digital down conversion with equalization, compared to the down conversion systems of the prior art.

(36) In the form of the invention illustrated in FIG. 3, (i) the mixers unit 42 includes 2M multipliers used in the down conversion effected by mixers unit 42, and (ii) the arithmetic units 51, 52, 53 and 54 of each of the processing units 34 also include L multipliers used with the convolution control coefficients stored in the coefficient memory 60 of each of the arithmetic units. The down conversion effected by the mixers unit 42, together with the multiplication of the down converted samples with the stored convolution control coefficients, provides a transformation of an input analog signal into I/Q baseband signals which is mathematically equivalent to conventional down conversion with equalization, but the computational burden posed by the multipliers in the form of FIG. 3 is significantly less than that of systems of the prior art.

(37) In the form of the invention illustrated in FIG. 6, the configuration enables a significant improvement in computational burden compared with the form illustrated in FIG. 3. In particular, there is no element in the form of FIG. 6 corresponding directly to the mixers unit 42 of the form of FIG. 3, and thus there is an immediate reduction in the number of multipliers.

(38) In the form of FIG. 6, the arithmetic units 82-85 of each of the processing units 34, are similar to those in the form of FIG. 3, in that they include L multipliers used with the control coefficients stored in the coefficient memory 60 of each of the arithmetic units. However, in contrast to the convolution control coefficients stored in memory 60 of the form of FIG. 3, the coefficient memory 60 of the arithmetic units 82-85 of each of the processing units 34 stores a set of mixer/convolution control coefficients, which when multiplied with applied L sample values, effect both the down conversion and convolution of the sample signals. Those multiplications thereby provide a transformation of an input analog signal into I/Q baseband signals which is also mathematically equivalent to conventional down conversion with equalization, but the computational burden posed by the multipliers in the form of FIG. 6 is significantly less than that of systems of the form of FIG. 3, which in turn is significantly less than that of systems of the prior art.

(39) Although the foregoing description of the embodiment of the present invention contains some details for purposes of clarity of understanding, the invention is not limited to the detail provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.