Low temperature ohmic contacts for III-N power devices

Abstract

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

Claims

1. A method for manufacturing an Au-free ohmic contact for a III-N device comprising: providing a semiconductor substrate and thereon a buffer layer, a channel layer, a barrier layer, and a passivation layer, wherein a two-dimensional electron gas (2DEG) layer is formed at an interface between the channel layer and the barrier layer; forming a recess at least extending through the passivation layer; forming a silicon layer at least at and in contact with a bottom of the recess; forming an Au-free metal stack in the recess after forming the silicon layer, wherein the metal stack includes a Ti/Al bi-layer, with a Ti layer overlying and in contact with the silicon layer, and an Al layer overlying and in contact with the Ti layer, wherein a thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1, and wherein the silicon layer forms a eutectic melt with the Ti/Al bi-layer; and after forming the Au-free metal stack, performing an anneal thereby forming the Au-free ohmic contact.

2. The method of claim 1, wherein the recess further extends into the barrier layer.

3. The method of claim 2, wherein the recess further extends into the channel layer.

4. The method of claim 1, wherein a thickness range of the silicon layer is from above 0 to 50 nm.

5. The method of claim 1, wherein the thickness ratio of the Ti layer to the Al layer is between 0.02 to 0.08.

6. The method of claim 5, wherein the Al layer has a thickness between 50 to 200 nm.

7. The method of claim 1, wherein a deposition temperature of the Al is less than 450 C.

8. The method of claim 1, wherein the metal stack further comprises a further metal layer overlaying and in contact with the Ti/Al bi-layer.

9. The method of claim 8, wherein the further metal layer comprises at least one metal selected from the group consisting of Ti, TiN, Cu, and W.

10. The method of claim 1, wherein the anneal is performed in an inert atmosphere or in a forming gas.

11. The method of claim 10, wherein the anneal is performed at a temperature between 450 C. to 650 C.

12. The method of claim 1, wherein the semiconductor substrate comprises silicon, SiC, or sapphire.

13. The method of claim 1, wherein the buffer layer comprises a plurality of sub-layers and each of the sub-layers comprises N and at least one of Al or Ga.

14. The method of claim 1, wherein the channel layer comprises GaN.

15. The method of claim 1, wherein the barrier layer comprises AlGaN.

16. The method of claim 1, wherein the passivation layer comprises at least one of SiN, AlN, AlSiN, Al2O3, or SiO2.

17. The method of claim 1, further comprising performing a wet clean prior to forming the metal stack, wherein the wet clean is performed with a chemical solution comprising at least one of HCl, HF, BHF, TMAH, or NH4OH.

18. A structure comprising: a semiconductor substrate; a buffer layer, a channel layer, a barrier layer, a two-dimensional electron gas (2DEG) layer at an interface between the channel layer and the barrier layer, and a passivation layer; a silicon layer overlying and in contact with the 2DEG layer; an Au-free metal stack for forming an ohmic contact, wherein the Au-free metal stack includes a Ti/Al bi-layer having a Ti layer overlying and in contact with the silicon layer and an Al layer overlying and in contact with the Ti layer, wherein a thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1, wherein the silicon layer forms a eutectic melt with the Ti/Al bi-layer.

19. A III-nitride device including the structure of claim 18, further comprising an Au-free ohmic contact formed from the metal stack comprising the Ti/Al bi-layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) All drawings are intended to illustrate some aspects and embodiments of the present disclosure. The drawings described are only schematic and are non-limiting.

(2) FIG. 1 schematically illustrates recessed ohmic contacts according to embodiments of the disclosure.

(3) FIG. 2 shows a cross-section SEM image of ohmic contacts according to embodiments of the disclosure.

(4) FIG. 3 shows contact resistance (R.sub.c) values versus Ti/Al thickness according to embodiments of the disclosure.

(5) FIG. 4 shows I-V curves up to 10 V for contacts with low (according to embodiments of the disclosure) and high R.sub.c (comparative data), wherein a contact spacing was 12 m.

(6) FIG. 5 schematically illustrates recessed ohmic contacts with Si interlayer according to embodiments of the disclosure.

(7) FIG. 6 shows contact resistance Rc (mm) for different thickness of a silicon layer underneath a Ti/Al bi-layer in accordance with embodiments of the disclosure.

DETAILED DESCRIPTION

(8) The present disclosure relates to the fabrication of Au-free ohmic contacts for III-N power devices using a Ti/Al-comprising metal stack having a contact resistance lower than those reported in the literature.

(9) Further, the present disclosure relates to the fabrication of Au-free ohmic contacts for AlGaN/GaN power devices using a Ti/Al-comprising metal stack having a contact resistance lower than 1 mm.

(10) Specific embodiments of the disclosure disclose Ti/Al bi-layers with a contact resistance of about 0.62 mm and a method of manufacturing thereof. Advantageously, the method of the disclosure may employ alloy temperatures as low as 550 C. or lower.

(11) The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the disclosure.

(12) Furthermore, the terms first, second, and the like in the description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.

(13) Moreover, the terms top, under, and the like in the description are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

(14) In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

(15) Where, herein, a specific chemical name or formula is given, the material may include non-stoichiometric variations of the stoichiometrically exact formula identified by the chemical name. Lack of numerical subscript by an element in the formula stoichiometrically signifies the number one (1). Variations in the range plus/minus 20% of the exact stoichiometric number are comprised in the chemical name or formula, for the present purposes. Where an algebraic subscript is given, then variations in the range of about plus/minus 20% are comprised relative to the value of each subscript. Such varied values do not necessarily sum to a whole number and this departure is contemplated. Such variations may occur due to either intended selection and control of the process conditions, or due to unintended process variations.

(16) In a first aspect the present disclosure, a method for manufacturing an Au-free ohmic contact for a III-N device includes providing a semiconductor substrate, and thereon a buffer layer, a channel layer, a barrier layer, and a passivation layer. A two-dimensional electron gas (2DEG) layer may be formed at the interface between the channel layer and the barrier layer. The method also includes forming a recess in the passivation layer and/or (partially) in the barrier layer and/or partially in the channel layer, thereby reaching respectively close to or up to or past the 2DEG layer. Further, the method includes forming an Au-free metal stack in the recess, wherein the metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess and an Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer may be from between about 0.01 to 0.1. In the present example, after forming the metal stack, the method includes performing an anneal, such as a rapid thermal anneal.

(17) Before forming the Ti/Al bi-layer in the recess, a silicon layer may be formed at least at and in contact with a bottom of the recess. In one example, this silicon layer has a thickness above zero up to 50 nm, such as between 2 and 20 nm.

(18) In the Ti/Al bi-layer, the Al layer may have a thickness of 50-200 nm. In addition, the deposition temperature of the Al may be between room temperature and 450 C. In the Ti/A; bi-layer, the Ti layer may have a thickness corresponding to a Ti/Al ratio of 0.01 to 0.1, such as between 0.02 to 0.08, or between 0.03 and 0.06.

(19) In embodiments of the disclosure, the Au-free metal stack may or may not comprise a further metal layer overlaying and in contact with the Ti/Al bi-layer. The further metal layer may include at least one metal selected from the group consisting of Ti, TiN, Cu, and W. This further metal layer is typically added, not to obtain the ohmic contact that is formed by the Si/Ti/Al, but for other reasons, such as to facilitate lithography processing, to avoid oxidation of the Al top layer, or to lower the metal resistance.

(20) The further metal layer may include or consist of one layer on top of the Ti/Al bi-layer, such as in the following examples: Ti/Al/TiN or Ti/Al/W. Alternatively, the further metal layer can be a multi-layer comprising, for example, two layers, such as in the following examples: Ti/Al/Ti/TiN or Ti/Al/Ti/W.

(21) The anneal process, which is also referred to herein as alloy formation, may be performed in an inert atmosphere or in the presence of a forming gas. Examples of an inert atmosphere include but are not limited to N.sub.2.

(22) In different embodiments, the anneal is performed at a temperature from 450 C. to 650 C. The latter, also referred to as alloy temperature, is substantially lower than the alloy temperatures known in the art for Au-free ohmic contacts. In another example, the anneal may be performed at a temperature between 500 C. and 550 C.

(23) In embodiments of the disclosure, the semiconductor substrate may include silicon, SiC, or sapphire. In particular examples, the semiconductor substrate may be a silicon wafer. Further, the buffer layer may comprise a plurality of sub-layers, and each of the sub-layers may comprise Al and/or Ga, and N, for example, AlGaN. In addition, a nucleation layer can be present at the interface between the semiconductor substrate and the buffer layer. Further, the channel layer may include GaN and the barrier layer may include AlGaN. In addition, a capping layer may be present overlying and in contact with the barrier layer.

(24) In embodiments of the disclosure, the passivation layer comprises SiN, AlN, AlSiN, Al.sub.2O.sub.3, SiO.sub.2, SiC, and/or SiCN. Further, the passivation layer may include or consist of Low Pressure Chemical Vapour Deposition (LPCVD) SiN, Rapid Thermal Chemical Vapour Deposition (RTCVD) SiN, Plasma-enhanced Atomic Layer Deposition (PEALD) SiN, or in-situ (MOCVD) SiN.

(25) Prior to forming the metal stack, a wet clean is may be performed to prepare the exposed surface of the recess for the metal deposition. The wet clean may be performed with a chemical solution comprising at least one of HCl, HF, BHF, TMAH, NH.sub.4OH, or a mixture (applied simultaneously) or combination (applied sequentially) thereof.

(26) In specific embodiments of the disclosure, undoped AlGaN/GaN/AlGaN double heterostructure layers are grown on 200 mm Silicon wafers by Metal-Organic Chemical Vapor Deposition (MOCVD).

(27) The symbols herein further refer to FIG. 1. On a Si substrate (not shown) a 200 nm-thick AlN nucleation layer (not shown) was first grown, followed by a buffer layer (10) comprised of 400 nm Al.sub.0.75Ga.sub.0.25N, 400 nm Al.sub.0.44Ga.sub.0.56N, and 1800 nm Al.sub.0.2Ga.sub.0.8N. Then a 150 nm-thick GaN channel (20) was grown followed by a thin AlN spacer (not shown) of about 1 nm and by Al.sub.0.2Ga.sub.0.8N barrier (30) of about 15 nm. Finally, in the present example, a 2 nm GaN is used as capping layer (not shown).

(28) A 150 nm-thick ex situ SiN passivation layer (40) was deposited by Rapid Thermal Chemical Vapor Deposition (RTCVD) at 700 C. This layer adequately passivates the GaN substrate surface and thereby avoids depletion of a 2-dimensional electron gas (2DEG) (21) that forms at the AlGaN/GaN interface. Alternatively, in other embodiments, the SiN passivation layer is formed in situ, e.g., in the same chamber/deposition platform with the III-nitride layers.

(29) In embodiments of the disclosure the passivation layer is deposited before ohmic contact formation, then ohmic contact trenches are defined by etching through this passivation layer. As a result, the passivation layer is still present on the GaN substrate at the edge of the ohmic contact, and also 2DEG depletion is avoided at the edge of the ohmic contact. This allows the ohmic contact to be in intimate sideways contact with an un-depleted 2DEG, thereby allowing the use of contact annealing temperatures that are substantially lower with respect to those reported in the art. For comparison, in case the passivation layer is deposited after formation of the ohmic contact formation, step coverage issues (such as voids in the layer) at the bottom corner of the topography formed by the ohmic contact on the GaN substrate can lead to a locally unpassivated GaN substrate at the edge of the ohmic contact, and hence a depleted 2DEG at the edge of the ohmic contact.

(30) The formation of ohmic contacts starts with a removal of the RTCVD nitride and the AlGaN barrier in the contact area down to the location of the 2DEG in the GaN channel as shown schematically in FIG. 1. An HCl-based clean is then carried out prior to the metal deposition. After metal stack deposition, an anneal at about 550 C. in N.sub.2 ambient for 90 s completes the formation of the ohmic contact.

(31) A CMOS-compatible metal stack (50) used for ohmic contacts may be composed of Ti (x nm)/Al (y nm), optionally with Ti (20 nm)/TiN (60 nm) on top the Al, where x and y were varied in different tests. In one example, Ti and TiN are sputtered at room temperature, while the Al is deposited at 350 C. The relative amount of Al in the Ti/Al stack plays a role in attenuating the aggressive TiGaN reaction, while excess Ti would lead to the formation of voids below the TiN.

(32) FIG. 2 shows a cross-section scanning electron microscopy (X-SEM) image of the recessed ohmic contact after alloy formation at 550 C. A smooth and sharp interface is observed between the contact and the GaN channel surface.

(33) The 2DEG sheet resistance at the AlGaN/GaN interface was extracted on Van der Pauw structures and the value obtained was 40010 /sq over the full 200 mm wafer, resulting in a good quality and uniformity of the 2DEG.

(34) In accordance with the present disclosure, Ohmic contacts were characterized with the standard transfer length method (TLM) technique. The box chart shown in FIG. 3 shows a median value and a spread over the 200 mm wafer for R.sub.c values obtained for different Ti and Al thicknesses in the ohmic metal stack.

(35) It was found that certain ratios of the Ti/Al thickness are preferred since they result in lower R.sub.c, with a minimum value of 0.620.06 mm obtained when using 5 nm Ti and 100 nm Al in the metal stack.

(36) Saturation of current through ohmic contacts to AlGaN/GaN HEMT layers has been investigated and different theories have been proposed as explanation, such as self-heating causing velocity saturation or the impact of surface traps acting as a virtual gate depleting locally the 2DEG. Together with the extraction of R.sub.c, current measurements were performed at 10 V on a single TLM pad.

(37) In FIG. 4, I-V wafer mapping over the full 200 mm wafer up to 10 V for two wafers with different Ti/Al ratios are compared: (1) Ti/Al bi-layer thicknesses 5 nm Ti/100 nm Al; and (2) Ti/Al bi-layer thicknesses 20 nm Ti/100 nm Al. The sample with 5 nm/100 nm Ti/Al having the lowest R.sub.c (as shown in FIG. 3) is also showing a higher current at 10 V (about 0.6 A/mm) than the sample with 20 nm Ti/100 nm Al.

(38) Optionally as shown in FIG. 5, in embodiments of this disclosure, a silicon layer (60) may be inserted in between the Ti/Al bi-layer (50) and a bottom of a recess (70). In the presented example, the Si layer may be deposited by CVD at 540 C., but the Si layer may also be deposited by sputtering.

(39) The silicon layer impacts the alloying phase. Firstly, it will form an eutectic melt with the Al/Ti bi-layer in the metal stack. This eutectic melt has a lower melting temperature, allowing the Al diffusion to start at a lower temperature. The Al at the AlGaN barrier/metal interface will form a AlN interlayer. As there is competition for Nitrogen between the AlGaN barrier layer and the AlN interlayer, both layers will be deficient in N. The N-vacancies in AlN and AlGaN have the effect of n-type doping in the layers and will create a highly doped interface layer with a large amount of charge carriers, resulting in a low contact resistance Rc. Moreover, silicon is also an n-type dopant in the Al(Ga)N material system and, during the alloying phase, silicon could also contribute to an increase in the amount of charge carriers, further helping in reducing the contact resistance.

(40) The device illustrated by FIG. 5 can be formed as follows. A recess (70) is patterned at least in the AlGaN barrier layer (30). The recess should preferably leave less than 5 nm of the barrier layer and this recess can extend up to 10 nm into the GaN channel layer (20). Using a wet clean or a plasma clean, the exposed surface of the patterned layers is cleaned thereby removing oxides and contamination. Then a silicon layer (60) is deposited. The processing window for the thickness of the silicon layer is large, for example, the silicon thickness can range from several nanometers to 10's of nanometers. After depositing the silicon layer (60), an optional surface cleaning can be performed to remove surface oxidation and contamination before depositing the metal stack comprising the Ti/Al bi-layer. This wet clean performed prior to forming the metal stack can be performed with a chemical solution comprising at least one of HCl, HF, BHF, TMAH, NH.sub.4OH, or a mixture thereof. The wet clean can also involve sequentially applying these chemical solutions or combinations or mixtures thereof.

(41) The formation of the metal stack can continue as discussed in the foregoing embodiments.

(42) In FIG. 5 the contact resistance Rc of the Au-free ohmic contact is given for different thicknesses of the silicon layer formed underneath the Ti/Al stack. The thickness of the silicon layer may be varied from 2 nm to 20 nm for given conditions of the metal stack formation. The contact resistance is nearly insensitive to the Si thickness, with most measured values between 0.25 mm to 0.35 mm.

(43) In a second aspect of the disclosure an intermediate structure in the process of manufacturing of an III-nitride device having Au-free ohmic contacts is disclosed. The intermediate structure includes a semiconductor substrate, a III-nitride heterostructure on the semiconductor substrate, a passivation layer on the III-nitride heterostructure, and a metal stack for forming ohmic contacts. In one example, the metal stack comprises a Ti/Al bi-layer including a Ti layer and an Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is from 0.01 to 0.1, in accordance with one embodiment. Optionally, a silicon layer is present underneath the Ti/Al bi-layer.

(44) The III-nitride heterostructure may also include, as described in the first aspect of the disclosure discussed above, a buffer layer, a channel layer, a barrier layer, and a passivation layer, with a 2DEG layer formed at an interface between the channel layer and the barrier layer.

(45) For the different compositions of the metal stack and of the III-nitride layers and passivation layer, reference is made to those compositions disclosed in relation to the first aspect of the disclosure.

(46) In a further aspect of the disclosure, a III-nitride device obtainable from the intermediate structure of the second aspect is disclosed. The III-nitride device comprises ohmic contacts formed by anneal from the metal stack comprising the Ti/Al bi-layer, which may be in contact with a silicon layer.

(47) The anneal for alloy formation is applied at a temperature lower than those known in the art as disclosed in detail in the first aspect of the disclosure, followed by the subsequent process steps of a conventional manufacturing flow.