Light emitting diode

Abstract

A light emitting diode including a first light emitting cell and a second light emitting cell disposed on a substrate and spaced apart from each other to expose a surface of the substrate, a first transparent layer disposed on and electrically connected to the first light emitting cell, first connection section disposed on a portion of the first light emitting cell, a second connection section disposed on a portion of the second light emitting cell, a first interconnection and a second interconnection electrically connecting the first light emitting cell and the second light emitting cell, and an insulation layer disposed between the first and second interconnections and a side surface of the first light emitting cell.

Claims

1. A light emitting diode, comprising: a first light emitting cell disposed on a substrate; a second light emitting cell disposed on the substrate, the second light emitting cell separated from the first light emitting cell; a first electrode layer electrically connected to the first light emitting cell; a first insulation layer disposed on and covering the first and second light emitting cells, the first insulation layer comprising a first opening on the first light emitting cell; an interconnection electrically connected to the first light emitting cell and the second light emitting cell, the interconnection comprising: a first portion and a second portion disposed on opposite sides of the second light emitting cell such that the first and second portions face each other and electrically contact the second light emitting cell; a third portion disposed on the first light emitting cell and electrically contacting the first light emitting cell; and a fourth portion disposed between the first and second light emitting cells and electrically connecting the third portion to the first and second portions.

2. The light emitting diode of claim 1, wherein the first and second portions of the interconnection are substantially parallel to each other.

3. The light emitting diode of claim 2, wherein the first and second portions of the interconnection extend away from the first light emitting cell and over the second light emitting cell such that the first and second portions extend along a periphery of the second light emitting cell.

4. The light emitting diode of claim 3, wherein: the third portion of the interconnection is disposed near a side of the first light emitting cell that is adjacent to the second light emitting cell; and the third portion of the interconnection extends in a direction that is substantially perpendicular to the first and second portions.

5. The light emitting diode of claim 4, further comprising a second insulation layer disposed between the fourth portion of the interconnection and a side surface of the first light emitting cell.

6. The light emitting diode of claim 1, wherein the first insulation layer is disposed on the first electrode layer.

7. The light emitting diode of claim 6, wherein the third portion of the interconnection contacts the first electrode layer through the first opening of the first insulation layer.

8. The light emitting diode of claim 7, further comprising: a second electrode layer electrically connected to the second light emitting cell.

9. The light emitting diode of claim 8, wherein the first insulation layer is disposed on the second electrode layer.

10. The light emitting diode of claim 9, wherein the first and second light emitting cells each comprising: a lower semiconductor layer disposed on the substrate, an upper semiconductor layer disposed on the lower semiconductor layer, and an active layer disposed on the substrate between the lower semiconductor layer and the upper semiconductor layer.

11. The light emitting diode of claim 10, wherein: each of the lower semiconductor layer, the upper semiconductor layer, and the active layer of each of the first and second light emitting cells comprising a gallium nitride-based material.

12. The light emitting diode of claim 11, wherein the gallium nitride-based material comprises at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN).

13. The light emitting diode of claim 12, wherein: the first light emitting cell further comprises a buffer layer disposed between the substrate and the lower semiconductor layer of the first light emitting cell, and the second light emitting cell further comprises a buffer layer disposed between the substrate and the lower semiconductor layer of the second light emitting cell.

14. The light emitting diode of claim 10, wherein the fourth portion of the interconnection contacts a side surface of the lower semiconductor layer of the second light emitting cell.

15. The light emitting diode of claim 13, wherein the fourth portion of the interconnection contacts the buffer layer of the second light emitting cell.

16. The light emitting diode of claim 15, wherein the fourth portion of the interconnection contacts a side surface of the buffer layer of the second light emitting cell.

17. The light emitting diode of claim 16, wherein the side surface of the buffer layer of the second light emitting cell is inclined.

18. The light emitting diode of claim 10, wherein the first insulation layer is disposed directly on a side surface of the lower semiconductor layer of the second light emitting cell.

19. The light emitting diode of claim 18, wherein the first insulation layer is disposed directly on an upper surface and a side surface of the upper semiconductor layer of the second light emitting cell.

20. The light emitting diode of claim 19, wherein the side surfaces of the upper semiconductor layer and the lower semiconductor layer of the second light emitting cell are inclined.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

(2) FIG. 1 is a schematic plan view of a light emitting diode in the related art.

(3) FIG. 2 and FIG. 3 are schematic sectional views taken along line A-A of FIG. 1.

(4) FIG. 4 is a schematic sectional view of a light emitting diode according to an exemplary embodiment of the present invention.

(5) FIGS. 5, 6, 7, 8, 9, 10, and 11 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the exemplary embodiment of FIG. 4.

(6) FIG. 12 is a schematic sectional view of a light emitting diode according to an exemplary embodiment of the present invention.

(7) FIGS. 13, 14, 15, and 16 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the exemplary embodiment of FIG. 12.

(8) FIG. 17 is a schematic plan view of a light emitting diode according to an exemplary embodiment of the present invention.

(9) FIG. 18 is a schematic sectional view taken along line B-B of FIG. 17.

(10) FIGS. 19, 20, 21, 22, 23, 24, and 25 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the exemplary embodiment of FIG. 18.

(11) FIG. 26 is a schematic plan view of a light emitting diode according to an exemplary embodiment of the present invention.

(12) FIGS. 27, 28, 29, and 30 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the exemplary embodiment of FIG. 26.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(13) The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements.

(14) It will be understood that when an element or layer is referred to as being on or connected to another element or layer, it can be directly on or directly connected to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being directly on or directly connected to another element or layer, there are no intervening elements or layers present. It will be understood that for the purposes of this disclosure, at least one of X, Y, and Z can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ).

(15) Spatially relative terms, such as beneath, below, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. Thus, the exemplary term below can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

(16) FIG. 4 is a schematic sectional view of a light emitting diode according to an exemplary embodiment of the present invention.

(17) Referring to FIG. 4, a light emitting diode according to one embodiment of the invention includes a substrate 51, light emitting cells S1, S2, a transparent electrode layer 61, a current blocking layer 60a, an insulation layer 60b, an insulation protective layer 63, and an interconnection 65. The light emitting diode may further include a buffer layer 53.

(18) The substrate 51 may be an insulating or conductive substrate. For example, the substrate 51 may be a sapphire substrate, a gallium nitride substrate, a silicon carbide (SiC) substrate, or a silicon substrate. On a single substrate 51, the first light emitting cell S1 and the second light emitting cell S2 are separated from each other. Each of the first and second light emitting cells S1, S2 has a stack structure 56, which includes a lower semiconductor layer 55, an upper semiconductor layer 59 disposed on one area of the lower semiconductor layer, and an active layer 57 interposed between the lower semiconductor layer and the upper semiconductor layer. Here, the upper and lower semiconductor layers may be p-type and n-type semiconductor layers, respectively, or vice versa.

(19) Each of the lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may be formed of a gallium nitride-based material, for example, (Al, In, Ga)N. The active layer 57 may be formed of a material having a composition capable of emitting light in a desired wavelength range, for example, ultra violet (UV) light or blue light, and the lower and upper semiconductor layers 55, 59 are formed of a material having a wider band gap than that of the active layer 57.

(20) As shown, the lower semiconductor layer 55 and/or the upper semiconductor layer 59 may be formed of a single layer or multiple layers. In addition, the active layer 57 may have a single quantum-well structure or a multi-quantum well structure.

(21) Each of the first and second light emitting cells S1, S2 may have an inclined side surface, an inclined angle of which ranges from 15 to 80 with respect to an upper surface of the substrate 51. Although not shown, the lower semiconductor layer 55 may have a stepped portion formed along a sidewall thereof.

(22) The active layer 57 and the upper semiconductor layer 59 are disposed on some area of the lower semiconductor layer 55, and the other area of the lower semiconductor layer 55 is exposed as shown in FIG. 4. Although the side surfaces of the active layer 57 and upper semiconductor layer 57 are shown as being vertical side surfaces in FIG. 4, it should be understood that these side surfaces may also be inclined.

(23) In FIG. 4, the first light emitting cell S1 and the second light emitting cell S2 are partially shown. However, it should be noted that the first light emitting cell S1 and the second light emitting cell S2 have a similar or the same structure. Specifically, the first and second light emitting cells S1, S2 have the same stack structure, and some area of the lower semiconductor layer 55 of the first light emitting cell S1 is exposed as in some area of the lower semiconductor layer 55 of the second light emitting cell S2.

(24) The buffer layer 53 may be interposed between the light emitting cells S1, S2 and the substrate 51. The buffer layer 53 is used to relieve lattice mismatch between the substrate 51 and the lower semiconductor layer 55 when the substrate 51 is a growth substrate.

(25) The transparent electrode layer 61 is disposed on each of the light emitting cells S1, S2. Specifically, a first transparent electrode layer 61 is disposed on the first light emitting cell S1, and a second transparent electrode layer 61 is disposed on the second light emitting cell S2. The transparent electrode layer 61 may be disposed on an upper surface of the upper semiconductor layer 59 to be connected to the upper semiconductor layer 59, and may have a smaller area than that of the upper semiconductor layer 59. In other words, the transparent electrode layer 61 may be recessed from an edge of the upper semiconductor layer 59. Thus, the light emitting diode according to this embodiment may prevent current crowding at the edge of the transparent electrode layer 61 through the sidewalls of the light emitting cells S1, S2.

(26) The current blocking layer 60a may be disposed on each of the light emitting cells S1, S2 between the transparent electrode layer 61 and each of the light emitting cells S1, S2. Particularly, the current blocking layer 60a is disposed near one edge of the first light emitting cell S1, and a portion of the transparent electrode layer 61 is disposed on the current blocking layer 60a. The current blocking layer 60a is formed of an insulation material, and particularly, may include a distributed Bragg reflector formed by alternately stacking layers having different indices of refraction.

(27) The insulation layer 60b covers a portion of the side surface of the first light emitting cell S1. As shown in FIG. 4, the insulation layer 60b extends to cover a portion of a side surface of the lower semiconductor layer 55 of the second light emitting cell S2. The insulation layer 60b has the same structure as that of the current blocking layer 60a and is formed of the same material as that of the current blocking layer 60a, and may include a distributed Bragg reflector. When the insulation layer 60b includes the distributed Bragg reflector formed of multiple layers, it is possible to efficiently suppress formation of defects such as pinholes in the insulation layer 60b. Alternatively, the insulation layer 60b may be separated from the current blocking layer 60a.

(28) The interconnection 65 electrically connects the first light emitting cell S1 to the second light emitting cell S2. The interconnection 65 is electrically connected at one end thereof to the transparent electrode layer 61 on the first light emitting cell S1 and at the other end thereof to the lower semiconductor layer 55 of the second light emitting cell S2, whereby the first light emitting cell S1 can be directly connected in series to the second light emitting cell S2.

(29) The interconnection 65 may contact the transparent electrode layer 61 over an entire overlapping area between the interconnection 65 and the transparent electrode layer 61. In the related art, a portion of the insulation layer 33 is disposed between the transparent electrode layer 31 and the interconnection 35. However, in this embodiment, the interconnection 65 directly contacts the transparent electrode layer 61 without any insulating material interposed therebetween.

(30) Further, the current blocking layer 60a may be disposed over an entire overlapping area between the interconnection 65 and the transparent electrode layer 61, and the current blocking layer 60a and the insulation layer 60b may be disposed over an entire overlapping area between the interconnection 65 and the first light emitting cell S1. In addition, the insulation layer 60b may be disposed between the second light emitting cell S2 and the interconnection 65 except for a connection area between the interconnection 65 and the second light emitting cell S2.

(31) When the current blocking layer 60a and the insulation layer 60b have reflective characteristics like distributed Bragg reflectors, the current blocking layer 60a and the insulation layer 60b may be substantially within the same area as that of the interconnection 65 in an area two times or less than that of the interconnection 65. The current blocking layer 60a and the insulation layer 60b prevent absorption of light by the interconnection 65 when light is emitted from the active layer 57. However, when the current blocking layer 60a and the insulation layer 60b occupy an excessively large area, there is a possibility of blocking discharge of light. Thus, it may be necessary to limit the area of the current blocking layer 60a and the insulation layer 60b.

(32) The insulation protective layer 63 may be disposed outside the area of the interconnection 65. The insulation protective layer 63 covers the first and second light emitting cells S1, S2 outside the area of the interconnection 65. The insulation protective layer 63 may be formed of a silicon oxide layer (SiO.sub.2) or a silicon nitride layer. The insulation protective layer 63 is formed with an opening through which the transparent electrode layer 61 on the first light emitting cell S1 and the lower semiconductor layer of the second light emitting cell S2 are exposed, and the interconnection 65 may be disposed within this opening.

(33) A side surface of the insulation protective layer 63 and a side surface of the interconnection 65 may be disposed to face each other, or to contact each other. Alternatively, the side surface of the insulation protective layer 63 may be separated from the side surface of the interconnection 65 to face each other.

(34) According to this embodiment, the current blocking layer 60a and the insulation layer 60b may be formed of the same material and have the same structure, and thus may be formed by the same process. In addition, since the interconnection 65 is disposed within the opening of the insulation protective layer 63, the insulation protective layer 63 and the interconnection 65 may be formed using the same mask pattern.

(35) In this embodiment, the light emitting diode is illustrated as including two light emitting cells, that is, the first light emitting cell S1 and the second light emitting cell S2. However, the present invention is not limited to the two light emitting cells, and more light emitting cells may be electrically connected to each other by interconnections 65. For example, the interconnections 65 may electrically connect the lower semiconductor layers 55 of adjacent light emitting cells to the transparent electrode layers 61 thereof to form a series array of the light emitting cells. The light emitting diode according to this embodiment may include a plurality of such arrays, which is connected to each other in reverse parallel and connected to an AC source. In addition, the light emitting diode may be provided with a bridge rectifier (not shown) connected to the series array of light emitting cells, such that the light emitting cells can be driven by an AC source. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as that of the light emitting cells S1, S2 using the interconnections 65.

(36) FIG. 5 to FIG. 11 are sectional views illustrating a method of fabricating a light emitting diode according to one embodiment of the present invention.

(37) Referring to FIG. 5, a semiconductor stack structure 56 is formed on a substrate 51, and includes a lower semiconductor layer 55, an active layer 57 and an upper semiconductor layer 59. In addition, before formation of the lower semiconductor layer 55, a buffer layer 53 may be formed on the substrate 51.

(38) The substrate 51 may be a sapphire (Al.sub.2O.sub.3) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, a silicon (Si) substrate, a gallium arsenide (GaAs), a gallium phosphide (GaP) substrate, a lithium alumina (LiAl.sub.2O.sub.3) substrate, a boron nitride (BN) substrate, an aluminum nitride (AlN) substrate, or a gallium nitride (GaN) substrate, without being limited thereto. That is, the substrate 51 may be selected from among various materials dependent upon materials of semiconductor layers to be formed thereon.

(39) The buffer layer 53 is formed to relieve lattice mismatch between the substrate 51 and the semiconductor layer 55 formed thereon, and may be formed of, for example, gallium nitride (GaN) or aluminium nitride (AlN). When the substrate 51 is a conductive substrate, the buffer layer 53 may be formed as an insulation layer or a semi-insulation layer, for example, AlN or semi-insulation GaN.

(40) Each of the lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, for example, (Al, In, Ga)N. The lower and upper semiconductor layers 55, 59 and the active layer 57 may be discontinuously or continuously formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, hydride vapor phase epitaxy (HVPE), and the like.

(41) Here, the lower and upper semiconductor layers are n-type and p-type semiconductor layers, respectively, or vice versa. The n-type semiconductor layer is formed by doping a gallium nitride-based compound semiconductor layer with, for example, silicon (Si) impurities, and the p-type semiconductor layer is formed by doping the gallium nitride-based compound semiconductor layer with, for example, magnesium (Mg) impurities.

(42) Referring to FIG. 6, a plurality of light emitting cells S1, S2 is formed to be separated from each other by photolithography and etching. Each of the light emitting cells S1, S2 has an inclined side surface, and the lower semiconductor layer 55 of each of the light emitting cells S1, S2 is partially exposed.

(43) In each of the light emitting cells S1, S2, the lower semiconductor layer 55 is first exposed by mesa-etching, and the light emitting cells are separated from each other by a cell isolation process. Alternatively, the light emitting cells S1, S2 may be first separated from each other by the cell isolation process, and then are subjected to mesa etching to expose the lower semiconductor layers 55 thereof.

(44) Referring to FIG. 7, a current blocking layer 60a covering a partial area of the first light emitting cell S1 is formed together with an insulation layer 60b covering a partial area of a side surface of the first light emitting cell S1. The insulation layer 60b may also extend to cover a portion of a side surface of the lower semiconductor layer 55 of the second light emitting cell S2.

(45) The current blocking layer 60a and the insulation layer 60b may be formed by depositing an insulation material layer, followed by patterning the insulation material layer through photolithography and etching. Alternatively, the current blocking layer 60a and the insulation layer 60b may be formed of an insulation material through a lift-off process. In particular, the current blocking layer 60a and the insulation layer 60b may be formed as distributed Bragg reflectors by alternately stacking layers having different indices of refraction, for example, a SiO.sub.2 layer and a TiO.sub.2 layer. When the insulation layer 60b is a distributed Bragg reflector formed of multiple layers, it is possible to prevent formation of defects such as pinholes in the insulation layer 60b, whereby the insulation layer 60b may be formed to be relatively thin as compared with conventional techniques.

(46) As shown in FIG. 7, the current blocking layer 60a and the insulation layer 60b may be connected to each other, without being limited thereto.

(47) Next, a transparent electrode layer 61 is formed on the first and second light emitting cells S1, S2. The transparent electrode layer 61 may be formed of a conductive material such as indium tin oxide (ITO) or zinc oxide, or a metal layer such as Ni/Au. The transparent electrode layer 61 is connected to the upper semiconductor layer 59 and is partially disposed on the current blocking layer 60a. The transparent electrode layer 61 may be formed by a lift-off process, without being limited thereto. Alternatively, the transparent electrode layer 61 may be formed by photolithography and etching.

(48) Referring to FIG. 8, an insulation protective layer 63 is formed to cover the first and second light emitting cells S1, S2. The insulation protective layer 63 covers the transparent electrode layer 61 and the insulation layer 60b. In addition, the insulation protective layer 63 may cover an overall area of the first and second light emitting cells S1, S2. The insulation protective layer 63 may be formed as an insulation material layer such as a silicon oxide layer or a silicon nitride layer by chemical vapor deposition or the like.

(49) Referring to FIG. 9, a mask pattern 70 having an opening is formed on the insulation protective layer 63. The opening of the mask pattern 70 corresponds to an area of the interconnection. Next, some region of the insulation protective layer 63 is etched using the mask pattern 70 as a mask. As a result, an opening is formed in the insulation protective layer 63 to expose some of the transparent electrode layer 61 and the insulation layer 60b, and the lower semiconductor layer 55 of the second light emitting cell S2 therethrough.

(50) Referring to FIG. 10, with the mask pattern 70 remaining on the insulation protective layer 63, a conductive material is deposited to form an interconnection 65 in the opening of the mask pattern 70. At this point, a portion 65a of the conductive material may be deposited on the mask pattern 70. The conductive material may be deposited by plating, electron-beam evaporation or sputtering.

(51) Referring to FIG. 11, the mask pattern 70 is removed together with the portion 65a of the conductive material on the mask pattern 70. Accordingly, the interconnection 65 electrically connecting the first and second light emitting cells S1, S2 to each other is finally formed.

(52) Here, one end of the interconnection 65 is connected to the transparent electrode layer 61 of the first light emitting cell S1, and the other end thereof to the lower semiconductor layer 55 of the second light emitting cell S2. In addition, the one end of the interconnection 65 is connected to the transparent electrode layer 61 within an upper area of the current blocking layer 60a. The interconnection 65 is separated from the side surface of the first light emitting cell S1 and the side surface of the second light emitting cell S2 via the insulation layer 60b. Furthermore, the interconnection 65 is disposed within the upper area of the current blocking layer 60a and the insulation layer 60b except for a portion of the interconnection 65 electrically connected to the lower semiconductor layer 55 of the second light emitting cell S2.

(53) In this embodiment, the current blocking layer 60a and the insulation layer 60b are formed by the same process. Accordingly, the insulation protective layer 63 and the interconnection 65 may be formed using the same mask pattern 70, whereby the light emitting diode can be fabricated using the same number of exposure processes while adding the current blocking layer 60a.

(54) FIG. 12 is a schematic sectional view of a light emitting diode according to an exemplary embodiment of the present invention.

(55) Referring to FIG. 12, the light emitting diode according to this embodiment is generally similar to the light emitting diode described with reference to FIG. 4, and further includes a transparent conductive layer 62.

(56) In the light emitting diode according to this embodiment, a substrate 51, light emitting cells S1, S2, a buffer layer 53, a transparent electrode layer 61, a current blocking layer 60a, an insulation layer 60b, an insulation protective layer 63 and an interconnection 65 are similar to those of the light emitting diode according to the above embodiment described with reference to FIG. 4, and detailed descriptions thereof will be omitted.

(57) The transparent conductive layer 62 is disposed between the insulation layer 60b and the interconnection 65. The transparent conductive layer 62 has a narrower line width than the insulation layer 60b, thereby preventing short circuit of the upper semiconductor layer 59 and the lower semiconductor layer 55 due to the transparent conductive layer 62. That is, when the insulation layer 60b is thicker than the transparent conductive layer 62, the insulation layer 60b may prevent a short circuit.

(58) On the other hand, the transparent conductive layer 62 is connected to the first transparent electrode layer 61, and may connect the first transparent electrode layer 61 to the second light emitting cell S2. For example, one end of the transparent conductive layer 62 may be electrically connected to the lower semiconductor layer 55 of the second light emitting cell. In addition, when two or more light emitting cells are connected to each other, a second transparent conductive layer 62 may extend from a second transparent electrode layer 61 on the second light emitting cell S2.

(59) In this embodiment, since the transparent conductive layer 62 is disposed between the interconnection 65 and the insulation layer 60b, electric current can flow through the transparent conductive layer 62 even in the case where the interconnection 65 is disconnected, thereby improving electrical stability of the light emitting diode.

(60) FIG. 13 to FIG. 16 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the present exemplary embodiment.

(61) Referring to FIG. 13, as in the method described with reference to FIG. 5 and FIG. 6, a semiconductor stack structure 56 is formed on a substrate 51 and a plurality of light emitting cells S1, S2 is formed to be separated from each other via photolithography and etching. Then, as described with reference to FIG. 7, a current blocking layer 60a covering a partial area of the first light emitting cell S1 is formed together with an insulation layer 60b covering a partial area of a side surface of the first light emitting cell S1. The insulation layer 60b may also extend to cover a portion of a side surface of the lower semiconductor layer 55 of the second light emitting cell S2.

(62) As described with reference to FIG. 7, the current blocking layer 60a and the insulation layer 60b may be formed as distributed Bragg reflectors by alternately stacking layers having different indices of refraction, for example, a SiO2 layer and a TiO2 layer. When the insulation layer 60b is a distributed Bragg reflector formed of multiple layers, it is possible to prevent formation of defects such as pinholes in the insulation layer 60b, whereby the insulation layer 60b may be formed to be relatively thin as compared with conventional techniques.

(63) Next, a transparent electrode layer 61 is formed on the first and second light emitting cells S1, S2. As described with reference to FIG. 7, the transparent electrode layer 61 may be formed of a conductive material such as indium tin oxide (ITO) or zinc oxide, or a metal layer such as Ni/Au. The transparent electrode layer 61 is connected to the upper semiconductor layer 59 and is partially disposed on the current blocking layer 60a. The transparent electrode layer 61 may be formed by a lift-off process, without being limited thereto. Alternatively, the transparent electrode layer 61 may be formed by photolithography and etching.

(64) During formation of the transparent electrode layer 61, a transparent conductive layer 62 is also formed. The transparent conductive layer 62 may be formed of the same material as that of the transparent electrode layer 61 through the same process. The transparent conductive layer 62 is formed on the insulation layer 60b, and may be connected to the transparent electrode layer 61. Further, one end of the transparent conductive layer 62 may be electrically connected to the lower semiconductor layer 55 of the second light emitting cell S2.

(65) Referring to FIG. 14, an insulation protective layer 63 is formed to cover the first and second light emitting cells S1, S2. The insulation protective layer 63 covers the transparent electrode layer 61, the transparent conductive layer 62 and the insulation layer 60b. In addition, the insulation protective layer 63 may cover an overall area of the first and second light emitting cells S1, S2. The insulation protective layer 63 may be formed as an insulation material layer such as a silicon oxide layer or a silicon nitride layer by chemical vapor deposition or the like.

(66) Referring to FIG. 15, as described with reference to FIG. 9, a mask pattern 70 having an opening is formed on the insulation protective layer 63. The opening of the mask pattern 70 corresponds to an area of the interconnection. Next, some region of the insulation protective layer 63 is etched using the mask pattern 70 as a mask. As a result, an opening is formed in the insulation protective layer 63 to expose some of the transparent electrode layer 61 and the transparent conductive layer 62, and the lower semiconductor layer 55 of the second light emitting cell S2 therethrough. Further, a portion of the insulation layer 60b is exposed through the opening.

(67) Referring to FIG. 16, as described with reference to FIG. 10, with the mask pattern 70 remaining on the insulation protective layer 63, a conductive material is deposited to form an interconnection 65 in the opening of the mask pattern 70.

(68) Next, as described with reference to FIG. 11, the mask pattern 70 is removed together with a portion 65a of the conductive material on the mask pattern 70. Accordingly, the interconnection 65 electrically connecting the first and second light emitting cells S1, S2 to each other is finally formed.

(69) In the embodiment described with reference to FIG. 5 to FIG. 11, the insulation layer 60b may be damaged during etching of the insulation protective layer 63. For example, when the insulation protective layer 63 is subjected to etching using an etching solution such as fluoric acid, the insulation layer 60b including an oxide layer may be damaged by the etching solution. Thus, the insulation layer 60b may not insulate the interconnection 65 from the first light emitting cell S1, thereby causing short circuit.

(70) On the contrary, in the present exemplary embodiment, since the transparent conductive layer 62 is disposed on the insulation layer 60b, the insulation layer 60b under the transparent conductive layer 62 can be protected from etching damage. Thus, it is possible to prevent short circuit due to the interconnection 65.

(71) In the present exemplary embodiment, the transparent electrode layer 61 and the transparent conductive layer 62 may be formed by the same process. Thus, the light emitting diode can be fabricated using the same number of exposure processes while adding the transparent conductive layer 62.

(72) FIG. 17 is a schematic plan view of a light emitting diode according to an exemplary embodiment of the present invention, and FIG. 18 is a schematic sectional view taken along line B-B of FIG. 17.

(73) Referring to FIG. 17 and FIG. 18, the light emitting diode includes a substrate 51, light emitting cells S1, S2, a transparent electrode layer 61, a current blocking layer 60a, an insulation layer 60b, an insulation protective layer 63, and an interconnection 65. The light emitting diode may further include a buffer layer 53.

(74) The substrate 51 may be an insulating or conductive substrate. For example, the substrate 51 may be a sapphire substrate, a gallium nitride substrate, a silicon carbide (SiC) substrate, or a silicon substrate. In addition, the substrate 51 may be a substrate having a convex-concave pattern (not shown) on an upper surface thereof, such as a patterned sapphire substrate.

(75) On a single substrate 51, the first light emitting cell S1 and the second light emitting cell S2 are separated from each other. Each of the first and second light emitting cells S1, S2 has a stack structure 56, which includes a lower semiconductor layer 55, an upper semiconductor layer 59 disposed on one area of the lower semiconductor layer, and an active layer 57 interposed between the lower semiconductor layer and the upper semiconductor layer. Here, the upper and lower semiconductor layers may be p-type and n-type semiconductor layers, respectively, or vice versa.

(76) Each of the lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may be formed of a gallium nitride-based material, for example, (Al, In, Ga)N. The active layer 57 may be formed of a material having a composition capable of emitting light in a desired wavelength range, for example, UV or blue light, and the lower and upper semiconductor layers 55, 59 are formed of a material having a wider band gap than that of the active layer 57.

(77) As shown, the lower semiconductor layer 55 and/or the upper semiconductor layer 59 may be formed of a single layer or multiple layers. In addition, the active layer 57 may have a single quantum-well structure or a multi-quantum well structure.

(78) Each of the first and second light emitting cells S1, S2 may have an inclined side surface, an inclined angle of which ranges from 15 to 80 with respect to an upper surface of the substrate 51.

(79) The active layer 57 and the upper semiconductor layer 59 are disposed on the lower semiconductor layer 55. An upper surface of the lower semiconductor layer 55 may be completely covered by the active layer 57 such that the side surface of the lower semiconductor layer 55 can be exposed.

(80) In FIG. 18, the first light emitting cell S1 and the second light emitting cell S2 are partially shown. However, it should be noted that the first light emitting cell S1 and the second light emitting cell S2 have a similar or the same structure as shown in FIG. 17. Specifically, the first and second light emitting cells S1, S2 have the same gallium nitride-based semiconductor stack structure, and may have inclined side surfaces of the same structure.

(81) The buffer layer 53 may be interposed between the light emitting cells S1, S2 and the substrate 51. The buffer layer 53 is used to relieve lattice mismatch between the substrate 51 and the lower semiconductor layer 55 formed thereon when the substrate 51 is a growth substrate.

(82) The transparent electrode layer 61 is disposed on each of the light emitting cells S1, S2. Specifically, a first transparent electrode layer 61 is disposed on the first light emitting cell S1, and a second transparent electrode layer 61 is disposed on the second light emitting cell S2. The transparent electrode layer 61 may be disposed on an upper surface of the upper semiconductor layer 59 to be connected to the upper semiconductor layer 59, and may have a smaller area than that of the upper semiconductor layer 59. In other words, the transparent electrode layer 61 may be recessed from an edge of the upper semiconductor layer 59. Thus, the light emitting diode according to this embodiment may prevent current crowding at the edge of the transparent electrode layer 61 through the sidewalls of the light emitting cells S1, S2.

(83) The current blocking layer 60a may be disposed on each of the light emitting cells S1, S2 between the transparent electrode layer 61 and each of the light emitting cells S1, S2. A portion of the transparent electrode layer 61 is disposed on the current blocking layer 60a. The current blocking layer 60a may be disposed near an edge of each of the light emitting cells S1, S2, without being limited thereto. Alternatively, the current blocking layer 60a may be disposed at a central region of each of the light emitting cells S1, S2. The current blocking layer 60a is formed of an insulation material, and particularly, may include a distributed Bragg reflector formed by alternately stacking layers having different indices of refraction.

(84) The insulation layer 60b covers a portion of the side surface of the first light emitting cell S1. As shown in FIG. 17 and FIG. 18, the insulation layer 60b may extend to an area between the first light emitting cell S1 and the second light emitting cell S2, and may cover a portion of the side surface of the lower semiconductor layer 55 of the second light emitting cell S2. The insulation layer 60b has the same structure as that of the current blocking layer 60a and is formed of the same material as that of the current blocking layer 60a, and may include a distributed Bragg reflector. The insulation layer 60b may be formed of a different process than that of the current blocking layer 60a. When the insulation layer 60b includes the distributed Bragg reflector formed of multiple layers, it is possible to efficiently suppress formation of defects such as pinholes in the insulation layer 60b. The insulation layer 60b may be directly connected to the current blocking layer 60a to be positioned adjacent thereto, but is not limited thereto. The insulation layer 60b may be separated from the current blocking layer 60a.

(85) The interconnection 65 electrically connects the first light emitting cell S1 to the second light emitting cell S2. The interconnection 65 includes a first connection section 65p and a second connection section 65n. The first connection section 65p is electrically connected to the transparent electrode layer 61 on the first light emitting cell S1, and the second connection section 65n is electrically connected to the lower semiconductor layer 55 of the second light emitting cell S2. The first connection section 65p may be disposed near one edge of the first light emitting cell S1, without being limited thereto. Alternatively, the first connection section 65p may be disposed at the central region of the first light emitting cell S1.

(86) The second connection section 65n may contact an inclined side surface of the second light emitting cell S2, particularly, an inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2. In addition, as shown in FIG. 17, the second connection section 65n may extend in opposite directions along the periphery of the second light emitting cell S2 while electrically contacting the inclined side surface of the lower semiconductor layer 55. The first light emitting cell S1 is connected in series to the second light emitting cell S2 by the first and second connection sections 65p, 65n of the interconnection 65.

(87) The interconnection 65 may contact the transparent electrode layer 61 over an entire overlapping area between the interconnection 65 and the transparent electrode layer 61. In the related art, a portion of the insulation layer 33 may be disposed between the transparent electrode layer 31 and the interconnection 35. However, in the present exemplary embodiment, the interconnection 65 directly contacts the transparent electrode layer 61 without any insulating material interposed therebetween.

(88) Further, the current blocking layer 60a may be disposed over the entire overlapping area between the interconnection 65 and the transparent electrode layer 61, and the current blocking layer 60a and the insulation layer 60b may be disposed over an entire overlapping area between the interconnection 65 and the first light emitting cell S1. In addition, the insulation layer 60b may be disposed between the second light emitting cell S2 and the interconnection 65 except for a connection area between the interconnection 65 and the second light emitting cell S2.

(89) Although the first connection section 65p and the second connection section 65n of the interconnection 65 are illustrated as being connected to each other via two paths in FIG. 17, the first connection section 65p and the second connection section 65n may be connected to each other via a single path.

(90) When the current blocking layer 60a and the insulation layer 60b have reflective characteristics like distributed Bragg reflectors, the current blocking layer 60a and the insulation layer 60b may be substantially within the same area as that of the interconnection 65 in an area two times or less than that of the interconnection 65. The current blocking layer 60a and the insulation layer 60b prevent absorption of light by the interconnection 65 when light is emitted from the active layer 57. However, when the current blocking layer 60a and the insulation layer 60b occupy an excessively large area, there is a possibility of blocking discharge of light. Thus, it may be necessary to limit the area of the current blocking layer 60a and the insulation layer 60b.

(91) The insulation protective layer 63 may be disposed outside the area of the interconnection 65. The insulation protective layer 63 covers the first and second light emitting cells S1, S2 outside the area of the interconnection 65. The insulation protective layer 63 may be formed of a silicon oxide layer (SiO.sub.2) or a silicon nitride layer. The insulation protective layer 63 is formed with an opening through which the transparent electrode layer 61 on the first light emitting cell S1 and the lower semiconductor layer of the second light emitting cell S2 are exposed, and the interconnection 65 may be disposed within this opening

(92) A side surface of the insulation protective layer 63 and a side surface of the interconnection 65 may be disposed to face each other, or to contact each other. Alternatively, the side surface of the insulation protective layer 63 may be separated from the side surface of the interconnection 65 to face each other.

(93) According to this embodiment, since the second connection section 65n of the interconnection 65 electrically contacts the inclined side surface of the second light emitting cell S2, there is no need for exposure of an upper surface of the lower semiconductor layer 55 of the second light emitting cell S2. Thus, there is no need for partial removal of the upper semiconductor layer 59 and the active layer 57, thereby increasing an effective light emitting area of the light emitting diode.

(94) In addition, the current blocking layer 60a and the insulation layer 60b may be formed of the same material and have the same structure, and thus may be formed by the same process. Further, since the interconnection 65 is disposed within the opening of the insulation protective layer 63, the insulation protective layer 63 and the interconnection 65 may be formed using the same mask pattern.

(95) In this embodiment, the light emitting diode is illustrated as including two light emitting cells, that is, the first light emitting cell S1 and the second light emitting cell S2. However, the present invention is not limited to the two light emitting cells, and more light emitting cells may be electrically connected to each other by interconnections 65. For example, the interconnections 65 may electrically connect the lower semiconductor layers 55 of adjacent light emitting cells to the transparent electrode layers 61 thereof to form a series array of the light emitting cells. The light emitting diode according to this embodiment may include a plurality of such arrays, which is connected to each other in reverse parallel and connected to an AC source. In addition, the light emitting diode may be provided with a bridge rectifier (not shown) connected to the series array of light emitting cells, such that the light emitting cells can be driven by an AC source. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as that of the light emitting cells S1, S2 using the interconnections 65.

(96) FIG. 19 to FIG. 25 are sectional views illustrating a method of fabricating a light emitting diode according to one embodiment of the invention.

(97) Referring to FIG. 19, a semiconductor stack structure 56 is formed on a substrate 51, and includes a lower semiconductor layer 55, an active layer 57 and an upper semiconductor layer 59. In addition, before formation of the lower semiconductor layer 55, a buffer layer 53 may be formed on the substrate 51.

(98) The substrate 51 may be a sapphire (Al.sub.2O.sub.3) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, a silicon (Si) substrate, a gallium arsenide (GaAs), a gallium phosphide (GaP) substrate, a lithium alumina (LiAl.sub.2O.sub.3) substrate, a boron nitride (BN) substrate, an aluminum nitride (AlN) substrate, or a gallium nitride (GaN) substrate, without being limited thereto. That is, the substrate 51 may be selected from among various materials dependent upon materials of semiconductor layers to be formed thereon. In addition, the substrate 51 may be a substrate having a convex-concave pattern (not shown) on an upper surface thereof, such as a patterned sapphire substrate.

(99) The buffer layer 53 is formed to relieve lattice mismatch between the substrate 51 and the semiconductor layer 55 formed thereon, and may be formed of, for example, gallium nitride (GaN) or aluminium nitride (AlN). When the substrate 51 is a conductive substrate, the buffer layer 53 may be formed as an insulation layer or a semi-insulation layer, for example, AlN or semi-insulation GaN.

(100) Each of the lower semiconductor layer 55, the active layer 57 and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, for example, (Al, In, Ga)N. The lower and upper semiconductor layers 55, 59 and the active layer 57 may be discontinuously or continuously formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, hydride vapor phase epitaxy (HVPE), and the like.

(101) Here, the lower and upper semiconductor layers are n-type and p-type semiconductor layers, respectively, or vice versa. The n-type semiconductor layer is formed by doping a gallium nitride-based compound semiconductor layer with, for example, silicon (Si) impurities, and the p-type semiconductor layer is formed by doping the gallium nitride-based compound semiconductor layer with, for example, magnesium (Mg) impurities.

(102) Referring to FIG. 20, a plurality of light emitting cells S1, S2 is formed to be separated from each other by photolithography and etching. Each of the light emitting cells S1, S2 has an inclined side surface. In a conventional method of fabricating a light emitting diode, photolithography and etching processes are added to expose a portion of an upper surface of the lower semiconductor layer 55 of each of the light emitting cells S1, S2. In this embodiment, however, the photolithography and etching processes for partially exposing the upper surface of the lower semiconductor layer 55 are omitted.

(103) Referring to FIG. 21, a current blocking layer 60a covering a partial area of the first light emitting cell S1 is formed together with an insulation layer 60b covering a partial area of a side surface of the first light emitting cell S1. The insulation layer 60b may also extend to cover an area between the first light emitting cell S1 and the second light emitting cell S2, and may cover a portion of the side surface of the lower semiconductor layer 55 of the second light emitting cell S2.

(104) The current blocking layer 60a and the insulation layer 60b may be formed by depositing an insulation material layer, followed by patterning the insulation material layer through photolithography and etching. Alternatively, the current blocking layer 60a and the insulation layer 60b may be formed as insulation material layers through a lift-off process. In particular, the current blocking layer 60a and the insulation layer 60b may be formed as distributed Bragg reflectors by alternately stacking layers having different indices of refraction, for example, a SiO.sub.2 layer and a TiO.sub.2 layer. When the insulation layer 60b is a distributed Bragg reflector formed of multiple layers, it is possible to prevent formation of defects such as pinholes in the insulation layer 60b, whereby the insulation layer 60b may be formed to be relatively thin as compared with conventional techniques.

(105) As shown in FIG. 21, the current blocking layer 60a and the insulation layer 60b may be connected to each other, without being limited thereto.

(106) Next, a transparent electrode layer 61 is formed on the first and second light emitting cells S1, S2. The transparent electrode layer 61 may be formed of a conductive material such as indium tin oxide (ITO) or zinc oxide, or a metal layer such as Ni/Au. The transparent electrode layer 61 is connected to the upper semiconductor layer 59 and is partially disposed on the current blocking layer 60a. The transparent electrode layer 61 may be formed by a lift-off process, without being limited thereto. Alternatively, the transparent electrode layer 61 may be formed by photolithography and etching.

(107) Referring to FIG. 22, an insulation protective layer 63 is formed to cover the first and second light emitting cells S1, S2. The insulation protective layer 63 covers the transparent electrode layer 61 and the insulation layer 60b. In addition, the insulation protective layer 63 may cover an overall area of the first and second light emitting cells S1, S2. The insulation protective layer 63 may be formed as an insulation material layer such as a silicon oxide layer or a silicon nitride layer by chemical vapor deposition or the like.

(108) Referring to FIG. 23, a mask pattern 70 having an opening is formed on the insulation protective layer 63. The opening of the mask pattern 70 corresponds to an area of the interconnection. Next, some region of the insulation protective layer 63 is etched using the mask pattern 70 as a mask. As a result, an opening is formed in the insulation protective layer 63 to expose some of the transparent electrode layer 61 and the insulation layer 60b, and an inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2 therethrough.

(109) Referring to FIG. 24, with the mask pattern 70 remaining on the insulation protective layer 63, a conductive material is deposited to form an interconnection 65 in the opening of the mask pattern 70. At this point, a portion 65a of the conductive material may be deposited on the mask pattern 70. The conductive material may be deposited by plating, electron-beam evaporation or sputtering.

(110) Referring to FIG. 25, the mask pattern 70 is removed together with the portion 65a of the conductive material on the mask pattern 70. Accordingly, the interconnection 65 electrically connecting the first and second light emitting cells S1, S2 to each other is finally formed.

(111) Here, a first connection section 65p of the interconnection 65 is connected to the transparent electrode layer 61 of the first light emitting cell S1, and a second connection section 65n of the interconnection 65 is connected to the inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2. The first connection section 65p of the interconnection 65 is connected to the transparent electrode layer 60a within an upper area of the current blocking layer 60a. The interconnection 65 is separated from the side surface of the first light emitting cell S1 by the insulation layer 60b.

(112) In this embodiment, the current blocking layer 60a and the insulation layer 60b are formed by the same process. Accordingly, the insulation protective layer 63 and the interconnection 65 may be formed using the same mask pattern 70, whereby the light emitting diode can be fabricated using the same number of exposure processes while adding the current blocking layer 60a.

(113) FIG. 26 is a schematic sectional view of a light emitting diode according to an exemplary embodiment of the present invention.

(114) Referring to FIG. 26, the light emitting diode according to the present exemplary embodiment is generally similar to the light emitting device described with reference to FIG. 17 and FIG. 18, and further includes a transparent conductive layer 62.

(115) In the light emitting diode according to this embodiment, a substrate 51, light emitting cells S1, S2, a buffer layer 53, a transparent electrode layer 61, a current blocking layer 60a, an insulation layer 60b, an insulation protective layer 63 and an interconnection 65 are similar to those of the light emitting diode according to the above embodiment described with reference to FIG. 17 and FIG. 18, and detailed descriptions thereof will be omitted.

(116) The transparent conductive layer 62 is disposed between the insulation layer 60b and the interconnection 65. The transparent conductive layer 62 has a narrower line width than the insulation layer 60b, thereby preventing short circuit of the upper semiconductor layer 59 and the lower semiconductor layer 55 due to the transparent conductive layer 62.

(117) On the other hand, the transparent conductive layer 62 is connected to the first transparent electrode layer 61, and may connect the first transparent electrode layer 61 to the second light emitting cell S2. For example, one end of the transparent conductive layer 62 may be electrically connected to the lower semiconductor layer 55 of the second light emitting cell. In addition, when two or more light emitting cells are connected to each other, a second transparent conductive layer 62 may extend from a second transparent electrode layer 61 on the second light emitting cell S2.

(118) In this embodiment, since the transparent conductive layer 62 is disposed between the interconnection 65 and the insulation layer 60b, electric current can flow through the transparent conductive layer 62 even in the case where the interconnection 65 is disconnected, thereby improving electric stability of the light emitting diode.

(119) FIG. 27 to FIG. 30 are schematic sectional views illustrating a method of fabricating a light emitting diode according to the exemplary embodiment of FIG. 26.

(120) Referring to FIG. 27, as in the method described with reference to FIG. 19 and FIG. 20, a semiconductor stack structure 56 is formed on a substrate 51 and a plurality of light emitting cells S1, S2 is formed to be separated from each other via photolithography and etching. Then, as described with reference to FIG. 21, a current blocking layer 60a covering a partial area of the first light emitting cell S1 is formed together with an insulation layer 60b covering a partial area of a side surface of the first light emitting cell S1.

(121) As described with reference to FIG. 21, the current blocking layer 60a and the insulation layer 60b may be formed as distributed Bragg reflectors by alternately stacking layers having different indices of refraction, for example, a SiO.sub.2 layer and a TiO.sub.2 layer. When the insulation layer 60b is a distributed Bragg reflector formed of multiple layers, it is possible to prevent formation of defects such as pinholes in the insulation layer 60b, whereby the insulation layer 60b may be formed to be relatively thin as compared with conventional techniques.

(122) Next, a transparent electrode layer 61 is formed on the first and second light emitting cells S1, S2. As described with reference to FIG. 21, the transparent electrode layer 61 may be formed of a conductive material such as indium tin oxide (ITO) or zinc oxide, or a metal layer such as Ni/Au. The transparent electrode layer 61 is connected to the upper semiconductor layer 59 and is partially disposed on the current blocking layer 60a. The transparent electrode layer 61 may be formed by a lift-off process, without being limited thereto. Alternatively, the transparent electrode layer 61 may be formed by photolithography and etching.

(123) During formation of the transparent electrode layer 61, a transparent conductive layer 62 is also formed. The transparent conductive layer 62 may be formed of the same material as that of the transparent electrode layer 61 through the same process. The transparent conductive layer 62 is formed on the insulation layer 60b, and may be connected to the transparent electrode layer 61. Further, one end of the transparent conductive layer 62 may be electrically connected to an inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2.

(124) Referring to 28, an insulation protective layer 63 is formed to cover the first and second light emitting cells S1, S2. The insulation protective layer 63 covers the transparent electrode layer 61, the transparent conductive layer 62 and the insulation layer 60b. In addition, the insulation protective layer 63 may cover an overall area of the first and second light emitting cells S1, S2. The insulation protective layer 63 may be formed as an insulation material layer such as a silicon oxide layer or a silicon nitride layer by chemical vapor deposition or the like.

(125) Referring to FIG. 29, as described with reference to FIG. 23, a mask pattern 70 having an opening is formed on the insulation protective layer 63. The opening of the mask pattern 70 corresponds to an area of the interconnection. Next, some region of the insulation protective layer 63 is etched using the mask pattern 70 as a mask. As a result, an opening is formed in the insulation protective layer 63 to expose some of the transparent electrode layer 61 and the transparent conductive layer 62, and the inclined side surface of the lower semiconductor layer 55 of the second light emitting cell S2 therethrough. A portion of the insulation layer 60b is exposed through the opening. Further, a portion of the insulation layer 60b is exposed through the opening.

(126) Referring to FIG. 30, as described with reference to FIG. 24, with the mask pattern 70 remaining on the insulation protective layer 63, a conductive material is deposited to form an interconnection 65 in the opening of the mask pattern 70.

(127) Next, as described with reference to FIG. 25, the mask pattern 70 is removed together with a portion 65a of the conductive material on the mask pattern 70. Accordingly, the interconnection 65 electrically connecting the first and second light emitting cells S1, S2 to each other is finally formed.

(128) In the embodiment described with reference to FIG. 19 to FIG. 25, the insulation layer 60b may be damaged during etching of the insulation protective layer 63. For example, when the insulation protective layer 63 is subjected to etching using an etching solution such as fluoric acid, the insulation layer 60b including an oxide layer may be damaged by the etching solution. Thus, the insulation layer 60b may not insulate the interconnection 65 from the first light emitting cell S1, thereby causing short circuit.

(129) In the present exemplary embodiment, since the transparent conductive layer 62 is disposed on the insulation layer 60b, the insulation layer 60b under the transparent conductive layer 62 can be protected from etching damage. Thus, it is possible to prevent short circuit due to the interconnection 65.

(130) In this embodiment, the transparent electrode layer 61 and the transparent conductive layer 62 may be formed by the same process. Thus, the light emitting diode can be fabricated using the same number of exposure processes while adding the transparent conductive layer 62.

(131) Although the invention has been illustrated with reference to some embodiments in conjunction with the drawings, it will be apparent to those skilled in the art that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention. Further, it should be understood that some features of a certain embodiment may also be applied to other embodiments without departing from the spirit and scope of the invention. Therefore, it should be understood that the embodiments are provided by way of illustration only and are given to provide complete disclosure of the invention and to provide thorough understanding of the invention to those skilled in the art. Thus, it is intended that the invention cover the modifications and variations provided they fall within the scope of the appended claims and their equivalents.