SEMICONDUCTOR DEVICE

Abstract

According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 m or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 m or more.

Claims

1. A semiconductor device comprising: a SiC layer of a first conductivity type; an electrode selectively formed on the SiC layer; and an insulator formed on the SiC layer, reaching a dicing region provided at the end portion of the SiC layer; wherein the insulator includes an insulating film under electrode arranged under the electrode and an organic insulating layer arranged so as to cover the insulating film under electrode, wherein a distance (A) of a section where the organic insulating layer is in contact with the SiC layer is 40 m or greater, and a lateral distance (B) between the electrode on the insulating film under electrode and the SiC layer is 40 m or greater.

2. A semiconductor device according to claim 1, further comprising a second conductivity type region formed in the dicing region, wherein the distance (A) of a section in which the organic insulating layer is in contact with the first conductivity type region of the SiC layer is 40 m or greater.

3. A semiconductor device according to claim 2, wherein the organic insulating layer is formed so as to cover the dicing region, and comes in contact with the second conductivity type region in the dicing region.

4. A semiconductor device according to claim 1, wherein the organic insulating layer does not cover the dicing region, and the insulator further includes an end insulating film that is made of a film of the same layer as that of the insulating film under electrode, the end insulating film covering the dicing region while being partly overlapped by the organic insulating layer, wherein an overlapped width (C) between the organic insulating layer and the end insulating film is 5 m or greater.

5. A semiconductor device according to claim 1, wherein the insulator further includes an end insulating film that is made of a film of the same layer as that of the insulating film under electrode, the end insulating film covering the dicing region, and the organic insulating layer overlaps the end insulating film so as to selectively cover the second conductivity region across the end insulating film, wherein the overlapped width (C) between the organic insulating layer and the end insulating film is 5 m or greater.

6. A semiconductor device according to claim 4, wherein the end insulating film has the same thickness as that of the insulating film under electrode.

7. A semiconductor device according to claim 1, wherein the distance (A) is 45 m to 180 m.

8. A semiconductor device according to claim 1, wherein the distance (B) is 45 m to 180 m.

9. A semiconductor device according to claim 1, wherein the total of the distance (A) and the distance (B) is 180 m or less.

10. A semiconductor device according to claim 1, wherein a breakdown voltage value (BV) is 1000 V or greater.

11. A semiconductor device according to claim 1, wherein the impurity concentration of the first conductivity type of the SiC layer is 110.sup.16cm.sup.3 or less, and the thickness of the SiC layer is 5 m or greater.

12. A semiconductor device according to claim 2, further comprising a termination structure of the second conductivity type that is composed of an impurity region formed outside the electrode in the SiC layer wherein a width (F) of the second conductivity type region is greater than or equal to the difference between a width (D) of the dicing region and a width which is twice as large as a width (E) of a depletion layer extending from the termination structure.

13. A semiconductor device according to claim 1, wherein the electrode is composed of a laminate structure represented by Ti/TiN/AlCu.

14. A semiconductor device according to claim 1, wherein the insulating film under electrode is composed of a SiO.sub.2 film having a thickness of 1 m or greater.

15. A semiconductor device according to claim 14, wherein the SiO.sub.2 film contains phosphorus (P).

16. A semiconductor device according to claim 14, wherein the SiO.sub.2 film contains boron (B).

17. A semiconductor device according to claim 1, wherein the insulating film under electrode is composed of a SiN film having a thickness of 1 m or greater.

18. A semiconductor device according to claim 1, wherein the organic insulating layer is composed of a polyimide-based material.

19. A semiconductor device according to claim 1, wherein the organic insulating layer is composed of a polybenzoxazole-based material.

20. A semiconductor device according to claim 1, wherein the organic insulating layer is composed of an acrylic-based material.

21. A semiconductor device according to claim 1, wherein a MOSFET is formed in the SiC layer as a semiconductor structure, and the electrode includes a source electrode electrically connected to a source of the MOSFET.

22. A semiconductor device according to claim 21, wherein the MOSFET has a planar-gate structure.

23. A semiconductor device according to claim 21, wherein the MOSFET has a trench-gate structure.

24. A semiconductor device according to claim 1, wherein a schottky-barrier diode is formed in the SiC layer as a semiconductor element structure, and the electrode includes a schottky electrode composing part of the schottky-barrier diode.

25. A semiconductor device according to claim 1, wherein an IGBT is formed in the SiC layer as a semiconductor element structure, and the electrode includes a source electrode electrically connected to a source of the IGBT.

26. A semiconductor device according to claim 1, wherein the organic insulating layer is in contact with the SiC layer in a plurality of regions, and the distance (A) defined as the total distance of the contact section in each of the plurality of regions is 40 m or greater.

27. A semiconductor device according to claim 1, further comprising a recess portion selectively formed in the SiC layer and filled with the organic insulating layer, wherein the distance (A) defined as the total distance of the contact section in contact with the organic insulating layer including the inner surface of the recess portion is 40 m or greater.

28. A semiconductor device comprising: a SiC layer of a first conductivity type; an electrode selectively formed on the SiC layer; an insulator formed on the SiC layer, reaching a dicing region provided at the end portion of the SiC layer; and a termination structure of a second conductivity type composed of an impurity region formed outside the electrode in the SiC layer, wherein the insulator includes an insulating film under electrode arranged under the electrode and an organic insulating layer arranged so as to cover the insulating film under electrode, wherein a distance (A) of a section where the organic insulating layer is in contact with the SiC layer is 40 m or greater, and a lateral distance (B) between the electrode on the insulating film under electrode and the SiC layer is at least two times larger than the width (E) of a depletion layer extending from the termination structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention.

[0043] FIG. 2 is an enlarged view of a portion surrounded by a dashed-dotted line II in FIG. 1.

[0044] FIG. 3 is an enlarged view of a portion surrounded by a dashed-two dotted line III FIG. 2.

[0045] FIG. 4 is a cross-sectional view of the semiconductor device taken along a line IV-IV shown in FIG. 3.

[0046] FIG. 5 is an enlarged view of a region surrounded by a dashed-two dotted line V in FIG. 2.

[0047] FIG. 6 is a cross-sectional view of the semiconductor device taken along a line VI-VI shown in FIG. 5.

[0048] FIG. 7A is a cross-sectional view illustrating a step associated with wafer cutting.

[0049] FIG. 7B is a cross-sectional view illustrating a state of a wafer after being cut.

[0050] FIG. 8 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0051] FIG. 9 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0052] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0053] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0054] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0055] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0056] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

EMBODIMENT FOR PRACTICING THE INVENTION

[0057] Hereinafter, an embodiment according to the present invention will be described in detail with reference to the attached drawings.

[0058] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, part of an element not exposed from the outer most surface of a semiconductor device 1 in actual plan view is shown in solid lines for the sake of clarity.

[0059] The semiconductor device 1 employs SiC, which is made in rectangular chip form in plan view when the outermost surface is viewed along a normal line thereto (hereinafter, simply referred to as plan view).

[0060] The semiconductor device 1 is provided with an active region 2 and an outer peripheral region 3 that surrounds the active region 2. In this embodiment the active region 2 is formed in a substantially rectangular shape in plan view in the inner portion of the semiconductor device 1, but the shape is not particularly limited.

[0061] In the active region 2, a gate metal 44, a source metal 43 as an example of an electrode according to the present invention, and a gate finger 5 are formed. A passivation film 40 is formed on the outermost surface of the semiconductor device 1 to cover these parts. The passivation film 40 is provided with openings 41, 42 to expose part of the gate metal 44 and part of the source metal 43 as a gate pad 4 and a source pad 6, respectively. Meanwhile, a whole of the gate finger 5 is covered with the passivation film 40. For the sake of clarity, the gate finger 5 is shown in solid lines while being hatched.

[0062] The gate metal 44, the gate finger 5 and the source metal 43 are made of metal wires that are composed of, for example, aluminum (Al), alloy of aluminum and copper (AlCu), copper (Cu) and so forth. Preferably, these parts are composed of a laminate structure represented by Ti/TiN/AlCu, which will be detailed later in the description of FIG. 6.

[0063] With the gate finger 5 constituted by a metal wire having a lower resistance compared to polysilicon, a gate current can be supplied in a short time even to a transistor cell 18 (see FIG. 2) that is positioned relatively faraway from the gate metal 44 (distant position). Further, Al is excellent in workability (easy to be worked), and thus formation steps of wiring can be made easier. Meanwhile, AlCu is capable of increasing the durability of the semiconductor device 1 against power cycle and humidity compared to a case where Al is employed, while increasing the joint strength of a bonding wire to the gate pad 4. When Cu is employed, a resistivity can be advantageously reduced compared to a case where Al or AlCu is employed.

[0064] The gate metal 44 is selectively formed in part of the peripheral edge (near a boundary with the outer peripheral region 3) of the active region 2. The gate finger 5 is divided into two parts with each extending from the formation position of the gate pad 4 along the peripheral edge of the active region 2 and in the inner portion of the active region 2. Thereby, the active region 2 is provided with a portion partitioned by a plurality of gate fingers 5 that extends in different directions with the gate metal 44 interposed therebetween, and cell regions 7, 45 outside the gate fingers 5.

[0065] More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in plan view, and is selectively arranged at the center portion of a side 8 of the active region 2. A side 9 that faces the side 8 and sides 10, 11 consecutively connected to both ends of these sides 8, 9 are provided in addition to the side 8 (where the gate metal is arranged) as the sides forming the active region 2.

[0066] The gate finger 5 includes a pad periphery 12 that surrounds the gate metal 44 with a distance therefrom, and a first finger 13 and a second finger 14 each extending along the side 8 of the active region 2 from the pad periphery 12 and in a direction orthogonal to the side 8.

[0067] The pad periphery 12 is formed in an annular rectangular shape along the periphery of the gate metal 44.

[0068] A pair of the first fingers 13 is formed along the side 8 extending from the pad periphery 12 toward the side 10 and the side 11 opposite the side 10.

[0069] The second finger 14 includes a linear base part 15 crossing the active region 2 to the side 9 in a direction orthogonal to the first finger 13, and a plurality of branch parts 16 integrally connected to the base part 15, extending from the connection portion with the base part 15 along the first fingers 13. In this embodiment, totally two pairs of branch parts 16 are formed and connected to two positions that are the tip end of the base part 15 and the middle portion of the base part 15, however the number of the branch parts 16 is not particularly limited.

[0070] Thereby, the cell regions 7, 45 are partitioned by the first finger 13 and the second finger 14 (base part 15 and branch part 16) in the active region 2. In this embodiment, a total of four inner cell regions 7 is formed with each one positioned at each corner of the intersection formed by the base part 15 and the central branch part 16. Further an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

[0071] The source metal 43 is formed to cover substantially a whole of the inner cell region 7 and the outer cell region 45. The passivation film 40 is provided with totally four openings 42 so that the source pad 6 is respectively arranged in each inner cell region 7.

[0072] Further, a recess 17 is formed in accordance with the shape of the gate metal 44. The recess 17 is arranged with the gate metal 44 set back from the first finger 14 toward the inner portion of an active region 2, and is formed to avoid the gate metal 44.

[0073] FIG. 2 is an enlarged view of a portion of FIG. 1 surrounded by a dashed-dotted line H. That is, FIG. 2 shows an enlarged view of the gate pad 4 of the semiconductor device 1 and the region near the gate pad 4. Now, referring to FIG. 2, part of an element not exposed from the outer most surface of a semiconductor device 1 in actual plan view is shown in solid lines for the sake of clarity.

[0074] As shown in FIG. 2, a plurality of transistor cells 18 is arranged in the inner cell region 7 and the outer cell region 45 partitioned by the gate fingers 5 (pad periphery 12, first finger 13, and second finger 14).

[0075] In this embodiment, the plurality of transistor cells 18 is arranged in a matrix pattern in plan view in each inner cell region 7 and outer cell region 45. The plurality of transistor cells 18 is aligned in accordance with the shape of the gate finger 5 near the gate finger 5. For example, the plurality of transistor cells 18 is aligned to bend along the shape of corners of the pad periphery 12, and is linearly aligned in accordance with the shape of the linear base part 15 of the second finger 14. The source metal 43 is formed to cover the plurality of transistor cells 18.

[0076] In FIG. 2, part of the plurality of transistor cells 17 covered with the source metal 43 is shown for the sake of clarity. Further, the arrangement patterns of the plurality of transistor cells 18 may include not only a matrix pattern, but also, for example, a stripe pattern, a zigzag pattern and so forth. Also, the planar shape of each transistor cell 18 is not limited to a rectangular shape, but may include, for example, a circular shape, a triangular shape, a hexagonal shape and so forth.

[0077] A gate electrode 19 is formed between mutually adjacent transistor cells 18. The gate electrode 19 is arranged between each matrix array transistor cell 18 in the inner cell region 7 and the outer cell region 45, and formed as a whole in a lattice shape in plan view. Meanwhile, the gate electrode 19 is also formed in a region where the gate finger 5 is arranged, in addition to the inner cell region 7 and the outer cell region 45, and the portion under the gate finger 5 is in contact with the gate finger 5.

[0078] In this embodiment, part of the gate electrode 19 is formed under the first finger 13 and the second finger 14 to face the first finger 13 and the second finger 14 as a contact portion. In FIG. 2, the part of the gate electrode 19 formed thereunder is shown as a hatched region for the sake of clarity. Thereby, the mutually adjacent gate electrodes 19 in the inner cell region 7 are consecutively formed through the gate electrode 19 crossing under the second finger 14. The consecutive formation of the gate electrode 19 maybe also applied to the formation between the inner cell region 7 and the outer cell region 45 across the gate metal 44. That is, the gate electrode 19 of these regions is consecutively formed through the gate electrode 19 crossing under the first finger 13.

[0079] The first finger 13 and the second finger 14 are each connected to the gate electrode 19 arranged thereunder through a gate contact 20. The gate contact 20 is linearly formed along each longitudinal direction of the first finger 13 and the second finger 14 in the center portion of the finger spaced apart from each side edge of the first finger 13 and the second finger 14.

[0080] Further in this embodiment, a plurality of embedded resistors 21 is arranged under the gate metal 44. The plurality of embedded resistors 21 is arranged at positions substantially equidistant from the center of gravity of the planar shape gate metal 44, and thereby the plurality of embedded resistors 21 can be preferably arranged in symmetrical pattern. In this embodiment, each of the plurality of embedded resistors 21 is positioned at each corner of the gate metal 44 rectangularly shaped in plan view, the embedded resistors 21 thereby being arranged equidistantly from the gravity center G of the gate metal 44. As such four embedded resistors 21 are formed into a symmetrical shape.

[0081] Such symmetrical patterns can be created in various ways. For example, each embedded resistor may be positioned at two diagonal corners of the gate metal 44, or may be positioned at two mutually opposite sides of the gate metal 44 so as to face each other. Further, for example, when the gate metal 44 has a circular shape in plan view, each of two embedded resistors may be positioned at both ends across the diameter of the gate metal 44, or when the gate metal 44 has a triangular shape in plan view, each of three embedded resistors may be positioned at the three corners of the gate metal 44.

[0082] Each embedded resistor 21 is formed to extend across an annular gap region 26 between the gate metal 44 and the gate finger 5 (pad periphery 12). Thereby, the embedded resistor 21 faces each of the gate metal 44 ad the gate finger 5. The gate metal 44 and the gate finger 5 (pad periphery 12) are connected to the embedded resistor 21 arranged in the region thereunder through a pad contact 22 and a cell contact 23.

[0083] In this embodiment, the four embedded resistors 21 extend outward orthogonal to two mutually opposite sides of the gate metal 44 from a portion under each peripheral edge 24 of the gate metal 44 along the two mutually opposite sides to a portion under the pad periphery 12. Each embedded resistor 21 is formed into a rectangular shape in plan view, and has a size of 200 m or less (200 m200 m or less). Practically, if the size of each embedded resistor 21 is 200 m or less, the area of a region sacrificed by the embedded resistor 21 can be reduced in the area on the SiC epitaxial layer 28 (see FIG. 4), and thus space saving can be achieved.

[0084] Further, the pad contact 22 and the cell contact 23 are respectively formed in straight lines parallel to each other along the sides of the gate metal 44 and the pad periphery 12.

[0085] The gate pad 4 is secured at the central portion of the gate metals 44 as a wire region surrounded by the embedded resistors 21 by placing the embedded resistors 21 at positions excluding the central portion under the peripheral edge 24 of the gate metal 44 and covering the regions over the regions where the gate metals 44 are placed with the passivation film 40. The gate pad 4 is a region to which a bonding wire is connected.

[0086] That is, in this embodiment, each corner of the gate metal 44 where the embedded resistors 21 are placed is selectively covered with the passivation film 40, and thereby other portions of the gate metal 44 are exposed through the opening 41. Thereby, the gate pad 4 having a rectangular shape in plan view with each inwardly recessed corner is exposed from the outermost surface of the semiconductor device 1. In this way, the upper portion of the region where the embedded resistors 21 are arranged is covered with the passivation film 40, and thus the bonding wire can be prevented from being incorrectly bonded onto a portion of the gate metal 44 overlapping the embedded resistors 21 during the bonding of the bonding wire. As a result, the semiconductor device 1 according to this embodiment can prevent the embedded resistors 21 from being damaged or destroyed due to ultrasonic impact and so forth during the bonding of the bonding wire.

[0087] FIG. 3 is an enlarged view of a portion surrounded by a dashed-two dotted line III in FIG. 2. FIG. 4 is a cross-sectional view of the semiconductor device taken along a line IV-IV shown in FIG. 3. The scale size of each composing element in FIGS. 3, 4 can be different from those in FIGS. 1, 2 for the sake of clarity, and similarly the scale size of each composing element can be different between FIG. 3 and FIG. 4. Further, the elements not actually exposed from the outermost surface of the semiconductor device 1 are partly shown in solid lines in FIGS. 3 and 4 for the sake of clarity.

[0088] Next, more specific structure of the embedded resistors 21 and the nearby region thereof will be described referring to the sectional view of the semiconductor device 1.

[0089] The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is laminated on the SiC substrate 27, and this laminate structure is shown as an example of the SiC layer according to the present invention.

[0090] The SiC substrate 27 and the SiC epitaxial layer 28 are n.sup.+ type and n.sup. type SiCs, respectively. The impurity concentration of an n.sup.+ type SiC substrate 27 is, for example, 110.sup.17 cm.sup.3 to 110.sup.21 cm.sup.3. Meanwhile, the impurity concentration of the n.sup. type SiC epitaxial layer 28 is, for example, 110.sup.14 cm.sup.3 to 110.sup.16 cm.sup.3. Further, for example, nitrogen (N), phosphorus (P), arsenic (As) and so forth can be used as n-type impurities (the same applies hereinafter).

[0091] Further, the thickness of the SiC substrate 27 is, for example, 50 m to 1000 m, and the thickness of the SiC epitaxial layer 28 is, for example, 5 m or greater (specifically 5 m to 100 m).

[0092] A plurality of transistor cells 18 is formed on the surface of the SiC epitaxial layer 28 in the inner cell region 7. The plurality of transistor cells 18 includes a p.sup. type body region 29, an n.sup.+ type source region 30 selectively formed in the inner portion of the p.sup. type body region 29 spaced apart from the peripheral edge of the p.sup. type body region 29, and a p.sup.+ type body contact region 31 selectively formed in the inner portion of the n.sup.+ type source region 30 spaced apart from the peripheral edge of the n.sup.+ type source region 30. Further, the n.sup. type portion of the SiC epitaxial layer 28 serves as a common drain region for the plurality of transistor cells 18.

[0093] As show in FIG. 3, when planarly viewed, the n.sup.+ type source region 30 is formed to surround the p.sup.+ type body contact region 31 except the transistor cells 18 along the pad periphery 12 (gate finger 5) and the p.sup. type body region 29 is formed to surround the n.sup.+ type source region 30. The annular region of the p.sup. type body region 29 surrounding the n.sup.+ type source region 30 is a channel region 32 where a channel is formed when the semiconductor device 1 is turned on.

[0094] Meanwhile, in the transistor cells 18 along the pad periphery 12 (gate finger 5), the p.sup. type body region 29 and the p.sup.+ type body contact region 31 are electrically connected to the later described p.sup. type region 34 and p.sup.+ type region 33, respectively.

[0095] The impurity concentration of the p.sup. type body region 29 is, for example, 110.sup.14 cm.sup.3 to 110.sup.19 cm.sup.3; the impurity concentration of the n.sup.+ type source region 30 is, for example, 110.sup.17 cm.sup.3 to 110.sup.21 cm.sup.3; and the impurity concentration of the p.sup.+ type body contact region 31 is, for example, 110.sup.19 cm.sup.3 to 110.sup.21 cm.sup.3.

[0096] When forming these regions 29 to 31, for example, the p.sup. type body region 29 is formed by ion injection in the surface part of the SiC epitaxial layer 28. Thereafter, n-type impurity ions and p-type impurity ions are injected into the surface part of the p.sup. type body region 29 in this order, and thereby the n.sup.+ type source region 30 and the p.sup.+ type body contact region 31 are formed. In this way, the transistor cells 18 composed of the regions 29 to 31 are formed. For example, boron (B), aluminum (Al) and so forth can be used as p-type impurities (the same applies hereinafter).

[0097] The p.sup. type region 34 is formed in the surface part of the SiC epitaxial layer 28 in the regions except for the inner cell region 7 and the outer cell region 45, more specifically in the regions under the gate metal 44, the gate finger 5, and the gap region 26 of the active region 2. The p.sup.+ type region 33 is formed in the surface part of the p.sup. type region 34.

[0098] The p.sup.+ type region 33 is formed to extend almost over the entire surface of the regions under the gate metal 44 and so forth so as to selectively expose the p.sup. type portion of the p.sup. type region 34 on the SiC surface in the region facing the embedded resistors 21 in the SiC epitaxial layer 28 while selectively exposing the p.sup.+ type portion of the p.sup.+ type region 33 on the SiC surface in the rest of regions in the SiC epitaxial layer 28. That is, the gate metal 44 and the gate finger 5 face the p.sup. type portion in the region where the embedded resistors 21 are placed, but the most part of the gate metal 44 and the gate finger 5 face the p.sup.+ type portion in the other region. Further, the p.sup.+ type region 33 and the p.sup. type region 34 are each formed to extend to the region under the source metal 43, and are integrally connected to the p.sup.+ type body contact region 31 and the p type body region 29 under the source metal 43 (outer portion of the source pad 6 in this embodiment). In FIG. 3, the p+ type body contact region 31 and the p+ type region 33 of the transistor cells 18 along the pad periphery 12 (gate finger 5) are shown by the hatched region. The p+ type body contact region 31 is practically fixed at the ground potential together with the source metal 43 to thereby stabilize the p+ type region 33 at 0 V. For this reason, the most part of the gate metal 44 and the gate finger 5 preferably face the p.sup.+ type portion 33 as shown in this embodiment.

[0099] The p.sup.+ type portion 33 and the p.sup. type region 34 are each formed in the same process as the p.sup.+ type body contact region 31 and the p.sup. type body region 29, and these are the same in impurity concentration and depth.

[0100] A gate insulating film 35 is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is composed of an insulating material such as silicon oxide, and has a thickness of, for example, 0.001 m to 1 m. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the embedded resistors 21 from the SiC epitaxial layer 28.

[0101] The gate electrode 19 and the embedded resistors 21 are formed on the gate insulating film 35. The gate electrode 19 is formed to face the channel region 32 of each transistor cell 18 across the gate insulating film 35. Whereas, the embedded resistors 21 are formed to face the exposed p.sup. portion of the p.sup. type region 34 across the gate insulating film 35.

[0102] Both the gate electrode 19 and the embedded resistors 21 are formed are made of p-type polysilicon, and may be formed in the same process. In this embodiment, the gate electrode 19 and the embedded resistors 21 include boron (B) as p-type impurities. Boron (B) doped polysilicon (embedded resistors 21) has a large value of specific electrical resistance compared to phosphorus (P) doped polysilicon generally used in a Si semiconductor device. As such, the boron (B) doped polysilicon (embedded resistors 21) can create the same value of resistance as the phosphorus (P) doped polysilicon with a smaller area than that of the phosphorus (P) doped polysilicon. Therefore, the area occupied by the embedded resistors 21 on the SiC epitaxial layer 28 can be decreased to effectively use the space.

[0103] The concentration of the p-type impurities contained in the polysilicon may be changed as necessary in accordance with each designed value of resistance of the gate electrode 19 and the embedded resistor 21. The concentration is set in this embodiment so that the sheet resistance of the embedded resistor 21 is greater than or equal to 10 /. The resistance value of the embedded resistor 21 as a whole can be easily made greater than the variation in resistance values among a plurality of semiconductor devices 1 without increasing the area of the embedded resistor 21 provided that the sheet resistance of the embedded resistor 21 is greater than or equal to 10 /. For example, if the variation in resistance values is between 0.1 and 20, inclusive, the resistance value of the embedded resistor 21 can be easily made between 2 and 40, inclusive with a smaller area. As a result, the area of a region sacrificed by the embedded resistor 21 can be reduced in the area on the SiC epitaxial layer 28, and thus other elements can be laid out without being much affected by the area of the embedded resistor 21. In this case, the total resistance value of the gate electrode 19 and the embedded resistor 21 is preferably between 4 and 50, inclusive.

[0104] The thickness of the gate electrode 19 and the embedded resistor 21 is preferably 2 m or less. The whole resistance of the embedded resistor 21 can be easily made greater than the variation in resistance values among a plurality of semiconductor devices 1 by making the thickness of the embedded resistor 21 less than or equal to 2 m. On the contrary, if the embedded resistor 21 is too much thick, the resistance value thereof unpreferably decreases greatly.

[0105] Further, an insulating film 47 is formed on the SiC epitaxial layer 28. The insulating film 47 is composed of an insulating material such as silicon oxide (SiO.sub.2) and silicon nitride (SiN), and has a thickness of 1 m to 5 m. Particularly, boron phosphorus silicon glass (BPSG) film having a thickness of 1 m or greater is preferably used.

[0106] The insulating film 47 includes an interlayer film 36 formed to cover the gate electrode 19 and the embedded resistor 21. The interlayer film 36 is formed to enter a region (first region) where the gate electrode 19 and the embedded resistor 21 are not placed in the region on the gate insulating film 35. Thereby, the distance (thickness T of insulating film) between the SiC epitaxial layer 28 and the gate metal 44 can be made greater in the region where the embedded resistor 21 is not placed, and thus the capacitance therebetween can be reduced.

[0107] The pad contact 22 and the cell contact 23 are formed to pass through the interlayer film 36. The pad contact 22 and the cell contact 23 are made of a metal via integrally formed with the gate metal 44 and the gate finger 5 (pad periphery 12).

[0108] Further, a source contact 46 is formed to pass through the interlayer film 36 so that the p.sup.+ body contact region 31 is in contact with the source metal 43. The source contact 46 is made of a metal via integrally formed with the source metal 43.

[0109] The gate metal 44, the gate finger 5, and the source metal 43 are formed on the interlayer film 36 spaced apart from each other.

[0110] The passivation film 40 is formed on the interlayer film 36 to cover the gate metal 44 the gate finger 5, and the source metal 43. The passivation film 40 is provided with openings 41, 42 to partly expose the gate metal 44 and the source metal 43.

[0111] As described above, the polysilicon resistor (embedded resistor 21) is interposed between the gate metal 44 the gate finger 5 as shown in FIG. 3 and FIG. 4 according to the semiconductor device 1. That is, the embedded resistor 21 is provided in the middle of a current path from the outside to the plurality of the transistor cells 18.

[0112] The resistance value of the embedded resistor 21 can be made dominant in the total resistance value (resistance value of gate resistor) of the gate electrode 19 and the embedded resistor 21 by adjusting the resistance value of the embedded resistor 21. Therefore, a current is prevented from flowing into a semiconductor device 1 in which the gate electrode 19 has a relatively low resistance value by setting the resistance value of the embedded resistor 21 greater than the variation in resistance values of the gate electrodes 19 even when using a plurality of parallel-connected semiconductor devices 1 with the gate electrodes 19 having the variation in resistance values. As a result, noise can be reduced when using such semiconductor devices 1.

[0113] Moreover, polysilicon composing the embedded resistor 21 is a material whose resistance value is easily changed by the injection of impurities. The processing technique for polysilicon has also been established in the conventional semiconductor technology. As such, when adopting the embedded resistor 21, the polysilicon as the material thereof prevents the structure of the semiconductor 1 itself and a module provided with the semiconductor 1 from becoming complex.

[0114] Similarly to the gate electrodes 19, although variation may take place in the size and the thickness of the embedded resistor 21 due to the variation in the processing accuracy (etching dimension and so forth) when manufacturing the semiconductor device 1, the processing dimension is smaller than the gate electrode 19. Therefore, the variation in the embedded resistors 21 hardly triggers the occurrence of noise.

[0115] The embedded resistor is connected to the gate metal 44 at the lower portion of the gate metal 44, and thus a gate current flowing into the current path continuing from the outside to the plurality of the transistor cells 18 can be controlled at the entrance of the current path. Thereby, a rush current can be prevented from flowing in only a specific transistor cell 18.

[0116] For example, in FIG. 2, when it is assumed that the embedded resistor 21 is formed as a bypass for the first finger 13 and the second finger 14 in the middle of the fingers 13, 14 of the gate finger 5, a rush current may flow in the gate electrode 19 through the gate contact 20 from the fingers 13, 14 before reaching the embedded resistor 21 in the side closer to the gate metal 44 than the embedded resistor 21. In contrast, given that a gate current can be controlled at the entrance of the current path as shown in this embodiment, the variation in switching speeds among a plurality of the transistor cells can be reduced.

[0117] Further, as shown in FIG. 2, the embedded resistors 21 are symmetrically arranged. The feature of this arrangement also helps to reduce the variation in switching speeds among a plurality of transistor cells 18.

[0118] Further, as shown in FIGS. 3 and 4, the region facing the embedded resistor 21 in the SiC epitaxial layer 28 is the p.sup. type region 34 having the impurity concentration of 110.sup.19 cm.sup.3 or less. Thereby, the dielectric breakdown of the gate insulating film 35 can be favorably suppressed. Further, a p.sup. type region can hardly store carriers compared to a n-type region, and thus the capacitance of the region between the embedded resistor 21 and the p.sup. type region 34 facing each other across the gate insulating film 35 can be also reduced.

[0119] Further as shown in FIGS. 3 and 4, the gate metal 44 and the embedded resistor 21 are connected by the pad contact 22 made of the metal via. With this configuration, the resistance value which the embedded resistor 21 gives to the current path from the outside to the plurality of transistor cells 18 can be easily adjusted by the process of changing the position of the pad contact 22 along the surface of the SiC epitaxial layer 28 or the process of changing the diameter of the via, and so forth.

[0120] For example, only by moving the pad contact 22 toward the pad periphery 12 like a pad contact 37 shown in a dashed line in FIG. 4, a distance from a position of the pad contact in contact with the embedded resistor 21 to the pad periphery 12 can be easily decreased from D.sub.1 to D.sub.2. Thereby, the resistance value of the embedded resistor 21 can be reduced. To the contrary, if the position of the pad contact is moved away from the pad periphery 12, the resistance value of the embedded resistor 21 can be increased. Alternatively, only by decreasing the via diameter compared to the pad contact 22 like a pad contact 38 shown in dashed line in FIG. 3, the resistance value of the current path directed to the embedded resistor 21 can be increased. To the contrary, if the via diameter is increased, the resistance value of the current path can be reduced.

[0121] Furthermore, these processes can be carried out only by using a mask adapted to distance design or via diameter design when forming the pad contact 22 (via), and thus the manufacturing process can be prevented from becoming complex.

[0122] FIG. 5 is an enlarged view of a region surrounded by a dashed-two dotted line V in FIG. 2. FIG. 6 is a cross-sectional view of the semiconductor device taken along a line VI-VI shown in FIG. 5. The scale size of each composing element in FIGS. 5 and 6 can be different from those in FIGS. 1 to 4 for the sake of clarity, and similarly the scale size of each composing element can be different between FIG. 5 and FIG. 6. Further, the elements not actually exposed from the outermost surface of the semiconductor device 1 are partly shown in solid lines in FIGS. 5 and 6 for the sake of clarity.

[0123] Next, the more specific structure of the peripheral edge and the outer peripheral region 3 of the active region 2 of the semiconductor device 1 is described together with the cross-sectional structure of the semiconductor device 1.

[0124] As previously described, a plurality of the transistor cells 18 is arrayed in matrix in plan view in the outer cell region 45 formed in the peripheral edge of the active region 2. Each transistor cell 18 is configured similarly to the structure described referring to FIG. 3 and FIG. 4.

[0125] A p.sup. type region 51 is formed in the surface part of the SiC epitaxial layer 28 outside the outer cell region 45. A p.sup.+ type region 52 is formed in the surface part of the p.sup. type region 51. The p.sup. type region 51 is linearly formed along the peripheral edge of the active region 2 and integrally formed with the p.sup. type body region 29 of the plurality of the outermost transistor cells 18. Only part of the p.sup. type region 51 next to the outer cell region 45 is shown in FIG. 5, but the p.sup. type region 51 may surround the cell region (the inner cell region 7 and the outer cell region 45) along the whole circumference of the active region 2. The p.sup.+ type region 52 is linearly formed to longitudinally extend in the inner region of the p.sup. type region 51 (the region spaced apart from the peripheral edge of the p.sup. type region 51). The p.sup. type region 51 and the p.sup.+ type region 52 are formed in the same process as the p.sup. type body region 29 and the p.sup.+ type body contact region 31, respectively, and the impurity concentration and the depth are also the same.

[0126] A plurality of guard rings 53 as an example of the termination structure of the present invention is formed to surround the cell region (the inner cell region 7 and the outer cell region 45) along the peripheral edge of the active region 2. The plurality of guard rings 53 is arranged in a guard ring region which has a given width (G) from the outermost region (the p.sup. type region 51 in this embodiment) of the regions set to the same potential as the source metal 43 in the SiC epitaxial layer 28. The given width (G) is 5 m to 100 m in this embodiment (for example, 28 m). When the guard rings 53 are formed in the same process as the p.sup. type body region 29, the impurity concentration and the depth are also the same. When formed in other processes, the impurity concentration is, for example, 110.sup.14 cm.sup.3 to 110.sup.19 cm.sup.3, and the depth is 0.1 m to 2 m.

[0127] Meanwhile, in the outer peripheral region 3, a p.sup. type region 55 is formed in the surface part of the SiC epitaxial layer 28, and a p.sup.+ type region 56 is formed in the surface part of the p.sup. type region 55. The p.sup. type region 55 and the p.sup.+ type region 56 are formed in the same process as the p.sup. type body region 29 and the p.sup.+ type body contact region 31 similarly to the p.sup. type region 51 and the p.sup.+ type region 52 (the impurity concentration and the depth are the same). However, the p.sup. type region 55 and the p.sup.+ type region 56 has a laminate structure wherein the p.sup.+ type region 56 is formed over the entire surface of the p.sup. type region 55.

[0128] The p.sup. type region 55 and the p.sup.+ type region 56 are positioned in a dicing region 54 provided at the end of the SiC epitaxial layer 28. The dicing region 54 is a region having a given width including a dicing line 58, which is provided at the boundary between adjacent semiconductors 1 on a wafer 57 as shown in FIGS. 7A and 7B. The wafer 57 is diced into individual semiconductor devices 1 by cutting along the dicing line 58. In this process, a predetermined marginal width needs to be provided by taking the positional displacement of a dicing saw into account, and this marginal portion remains as the dicing region 54 after the dicing process.

[0129] The p.sup. type region 55 and the p.sup.+ type region 56 are arranged to be exposed from the end surface 59 of the SiC epitaxial layer 28 in the dicing region 54. The width (F) of the p.sup. type region 55 and the p.sup.+ type region 56 with reference to the exposed surface (an end surface 59) is 5 m to 100 m (for example, 20 m) in this embodiment. This width (F) may be set, for example, within the range greater than or equal to the difference between the width (D) of the dicing region 54 and a width which is twice as large as the width (E) of a depletion layer 60 extending from the guard ring 53. In designing the width (F), the width (D) of the dicing region 54 may use the distance (for example, 13 m) from the end surface 59 of the SiC epitaxial layer 28 to the end edge of the passivation film 40 in this embodiment. Meanwhile, the width (E) of the depletion layer 60 may use a value calculated by the following expression (1):

[00001]$\begin{array}{cc}\left[\mathrm{Formula}.Math..Math.1\right].Math.& \\ \mathrm{Width}.Math..Math.\left(E\right)=W\left(\mathrm{.Math.m}\right)=\sqrt{\frac{2.Math..Math.{\mathrm{.Math.}}_s.Math.V_{\mathrm{bi}}}{{\mathrm{qN}}_B}}& \left(1\right)\end{array}$

[0130] Where, .sub.s represents a dielectric constant; V.sub.bi represents a built-in potential in the pn junction between the p-type guard ring 53 and the n-type SiC epitaxial layer 28; q represents the absolute value of the charge; and N.sub.B represents the donor concentration of the n-type SiC epitaxial layer 28.

[0131] The insulating film 47 further includes an insulating film under metal 61 as an example of the insulating film under electrode according to the present invention and an end insulating film 62 in addition to the interlayer film 36. The insulating film 47 is provided with a contact hole 63 for exposing the p.sup.+ type region 52. The inner portion of the contact hole 63 as a boundary is the interlayer film 36, which is formed on the gate insulating film 35. The outer portion adjacent to the interlayer 36 across the contact hole 63 is the insulating film under metal 61.

[0132] The source metal 43 is connected the p.sup.+ type region 52 through the contact hole 63. Further, the source metal 43 has an overlap portion 64 extending laterally outside to overlap the insulating film under metal 61. The overlap portion 64 faces the guard ring 53 across the insulating film under metal 61. In this embodiment, the overlap portion 64 is provided to partly covers the region where the guard ring 53 is formed (guard ring region having the width (G)) and the end thereof is arranged inside the outer end of the guard ring region. Although the overlap portion 64 may cover the whole of the guard ring region, the position of the end is determined so that a distance (B) shown in FIG. 6 is 40 m or greater (for example, 45 m to 180 m). The distance (B) represents the lateral length of the source metal 43 on the insulating film under metal 61 and the SiC epitaxial layer 28. In this embodiment, the distance (B) is the length from the end edge of the overlap portion 64 to the end edge of t. Further, the distance (B) may be at least two times greater than the width (E) of the depletion layer 60.

[0133] Further, as previously described, the source metal 43 is preferably composed of a laminate structure represented by Ti/TiN/AlCu. For example, in this embodiment, the source metal 43 includes Ti/TiN film 65 (barrier film) and an AlCu film 66 laminated in that order from the side of the SiC epitaxial layer 28. The Ti/TiN film 65 and the AlCu film 66 are not shown in FIG. 4.

[0134] An n-type region 67 (a region of a first conductivity type) is formed outside the insulating film under metal 61 to expose the SiC surface of the SiC epitaxial layer 28 over a distance (A). The n-type region 67 is part of the SiC epitaxial layer 28 exposed through an opening 68 formed outside the insulating film under metal 61 (between the insulating film under metal 61 and the end insulating film 62 in this embodiment). As shown in FIG. 5, for example, the opening 68 is linearly formed along the boundary between the active region 2 and the outer peripheral region 3. The distance (A) of the n-type region 67 is greater than 40 m (for example, 45 m to 180 m), however, a total of the distances (A) and (B) is preferably 180 m or less. By setting the total distance of the distance (A) and the distance (B) to 180 m or less, the chip size of the semiconductor device 1 can be kept within favorable sizes.

[0135] The end insulating film 62 is formed so as to cover the dicing region 54 of the SiC epitaxial layer 28. Specifically, the end insulating film 62 laterally extends from the end surface 59 of the SiC epitaxial layer 28 to the inner region beyond the dicing region 54. In this embodiment, the width (H) of the end insulating film 62 with reference to the end surface 59 is 10 m to 105 m (for example, 22 m). Thereby, the p.sup. type region 55 and the p.sup.+ type region 56 (p-type regions) are covered with the end insulating film 62.

[0136] As with the insulating film 47, the passivation film 40 is an example of the insulator according to the present invention, and is made of an organic insulator. The usable organic insulators include, for example, a polyimide-based material, a polybenzoxazole-based material, and an acrylic-based material. That is, in this embodiment, the passivation film 40 is constituted as an organic passivation film. Further, the thickness of the passivation film 40 is, for example, 0.2 m to 20 m.

[0137] The passivation film 40 is formed to cover the insulating film 47. In this embodiment, the passivation film 40 is formed to cover almost all the SiC epitaxial layer 28 except for the end thereof (in other words, the dicing region 54 is partitioned by the passivation film 40). Therefore, the passivation film 40 is in contact with the n-type region 67 of the SiC epitaxial layer 28 in the opening 68 of the insulating film 47 over the distance (A) of 40 m or greater.

[0138] The passivation film 40 does not cover the end of the SiC epitaxial layer 28, but has an overlap portion 69 that partly overlaps the end insulating film 62. The SiC surface of the SiC epitaxial layer 28 is prevented from being exposed to the outside by this overlap portion 69. Further, the overlapped width (C) formed by the overlap portion 69 and the end insulating film 62 is 5 m or greater (for example, 9 m) in this embodiment. Further, in this embodiment, the overlap portion 69 is formed inwardly away from the p-type region (the p.sup. type region 55 and the p.sup.+ type region 56) in plan view. Thereby, the overlapped portion 69 faces the n-type portion of the SiC epitaxial layer 28 across the end insulating film 62, and does not face the p-type region.

[0139] As described above, according to the semiconductor device 1, the distance (A) is 40 m or greater as shown in FIGS. 5 and 6, and thus the contact area between the organic passivation film 40 and the SiC epitaxial layer 28 (n-type region 67) can be sufficiently secured. Thereby, the adhesion of the organic passivation film 40 to the SiC epitaxial layer 28 can be improved. In addition, the distance (B) is 40 m or greater, or at least two times greater than the width (E) of the depletion layer 60, and thus can withstand a high-temperature, high-humidity, high-voltage test (for example, 85 C., 85% RH, and an applied voltage of 960V for 1000 consecutive hours). Setting the distance (A) and the distance (B) to the above described range is a quite new finding in a SiC semiconductor device. In a SiC, since the expansion of a depletion layer in the horizontal direction is smaller than in a Si, conventionally a chip size did not need to be increased by extending the distance (A) and the distance (B). This is not only because the depletion layer 60 was unlikely to reach the end surface 59 of a chip even without increasing the chip size, but because an increase in chip size possibly caused a rise in on-resistance per a unit of chip area. Under this background, the inventors of this application found that the durability against a high-temperature/high-humidity/high-voltage tests could be improved by purposely extending the distance (A) and the distance (B) to 40 m or greater.

[0140] Further in this embodiment, the p-type region (the p.sup. type region 55 and the p.sup.+ type region 56) is formed in the SiC epitaxial layer 28, and the p-type region is covered with the end insulating film 62. As such, when testing the electrical characteristics of a semiconductor device 1 in a state of the wafer 57 before the dicing process shown in FIG. 7A, the burden of a voltage Va applied in the atmosphere between the dicing region 54 and the source metal 43 (the portion exposed through the opening 42) can be reduced.

[0141] When carrying out a test, for example, the source metal 43 of one semiconductor device 1 is set to 0 V and the rear surface of the wafer 57 is set to 1000 V or greater (for example, 1700 V). Thereby, a maximum application voltage (BV) is applied to generate a potential difference of 1000 V or greater between the source metal 43 and the wafer 57, and thereby a withstand voltage of each MOSFET is measured. At this time, since the n-type portion of the wafer 57 including part of the dicing region 54 (the portion excluding the p.sup. type region 55 and the p.sup.+ type region 56) is fixed at a potential of 1000 V or greater, a potential difference of 1000 V or greater is generated between the dicing region 54 and the source metal 43. Even in this case, the p-type region (the p.sup. type region 55 and the p.sup.+ type region 56) is formed along the dicing region 54 according to this embodiment, and the dicing region 54 is covered with the end insulating film 62. As such, the maximum application voltage (BV) of 1000 V or greater applied between the dicing region 54 and the source metal 43 can be moderated in two stages of the end insulating film 62 and the p-type region (the p.sup. type region 55 and the p.sup.+ type region 56). Thereby, the burden of a voltage Va applied in the atmosphere between the dicing region 54 and the source metal 43 can be reduced. As a result, the semiconductor device 1 having a breakdown voltage value (BV) of 1000 V or greater can be achieved.

[0142] Further, by setting the thickness of the insulating film under metal 61 to 1 m or greater, insulation breakdown can be prevented even when a voltage of 1000 V or greater is applied to the insulating film under metal 61. Further, if the insulating film 47 is made of BPSG, it is possible to easily planarized the insulating film under metal 61 and the end insulating film 62 while rounding off and smoothing the corners of the insulating films 61, 62 by carrying out reflow soldering. As a result, the adhesion of the passivation film 40 to the insulating films 61, 62 can be improved.

[0143] Further, since the dicing region 54 is not covered with the passivation film 40, the semiconductor devices 1 in the state of the wafer 57b can be easily divided (diced) into individual semiconductor devices 1.

[0144] FIG. 8 to FIG. 14 are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention. The same reference numerals as those in claim 6 are applied to the mutually corresponding elements.

[0145] Next, in other embodiments according to the present invention, description will be made mainly to those different from the elements in the previously described semiconductor device 1.

[0146] In a semiconductor device 72 in FIG. 8, the overlap portion 69 of the passivation film 40 is selectively formed to cover the p-type region (the p.sup. type region 55 and the p.sup.+ type region 56) across the end insulating film 62. Thereby, the overlap portion 69 has a portion overlapped by the p-type region.

[0147] In a semiconductor device 73 in FIG. 9, the end insulating film 62 is not formed, instead, the passivation film 40 covers the SiC epitaxial layer 28 up to the end surface 59. In this case, the dicing region 54 may be formed by defining a suitable width (D) from the end surface 59. Further, the distance (A) may be defined by the length from the end edge of the insulating film under metal 61 to the end surface 59 of the SiC epitaxial layer 28.

[0148] A semiconductor device 74 shown in FIG. 10 has the same structure as the semiconductor device 73 shown in FIG. 9 except that the p.sup. type region 55 and the p.sup.+ type region 56 (p-type regions) are formed in the dicing region 54. In this case, the distance (A) may be defined by the length from the end edge of the insulating film under metal 61 to the p-type region. That is, the distance (A) of a section in which the passivation film 40 is in contact with the n-type portion of the SiC epitaxial layer 28 may be 40 m or greater.

[0149] A semiconductor device 75 shown in FIG. 11 has at least two openings 68 on the outer side of the insulating film under metal 61 in the insulating film 47. In this embodiment, each of the openings 68 is formed between the insulating film under metal 61 and an outer insulating film 79 and between the outer insulating film 79 and the end surface 59 of the SiC epitaxial layer 28. The passivation film 40 is in contact with the n-type regions 67 of the SiC epitaxial layer 28 over a distance (A.sub.1) and a distance (A.sub.2) in each opening 68. In this case, the distance of the section in which the passivation film 40 is in contact with the n-type region 67 can be represented as the sum of the distance (A.sub.1) and the distance (A.sub.2) of the respective contact sections, and the sum of the distances may be 40 m or greater.

[0150] A semiconductor device 76 shown in FIG. 12 has the same structure as the semiconductor device 73 shown in FIG. 9 except that a recess 80 is selectively formed in the n-type region 67. The passivation film 40 is in contact with the n-type region 67 on the inner surface (bottom surface and both lateral surfaces) of the recess 80. In this case, the distance of the section in which the passivation film 40 is in contact with the n-type region 67 can be defined as the total of the contact distance (A.sub.5) excluding the recess 80, and the distance (A.sub.3) and the distance (A.sub.4) of the contact sections on the bottom surface and both lateral surfaces of the recess 80 respectively, and the total distance may be 40 m or greater.

[0151] In a semiconductor device 77 in FIG. 13, the transistor cell 18 is constituted by a MOSFET cell having a trench-gate structure. In this case, the gate electrode 19 is embedded in a gate trench 39 formed in each region between the plurality of the transistor cells 18 across the gate insulating film 35.

[0152] In a semiconductor device 78 in FIG. 14, a schottky-barrier diode 81 is formed in the active region 2. That is, a schottky metal 82 that forms schottky junction with the SiC epitaxial layer 28 is provided in place of the source metal 43.

[0153] As described above, any of the semiconductor devices 72 to 78 has the following three features: (1) the distance (A) is 40 m or greater; (2) the distance (B) is 40 m or greater, or alternately is at least two times greater than the width (E) of the depletion layer 60; and (3) the end of the SiC epitaxial layer 28 is covered with an insulator (the end insulating film 62 or the passivation film 40). Therefore, these embodiments also can provide a SiC semiconductor device capable of preventing electrical discharge during an electrical characteristic test carried out in a wafer state while withstanding a high-temperature, high-humidity, high-voltage test similarly to the embodiments shown in FIGS. 1 to 6.

[0154] Although the embodiments according to the present invention have been described as above, the present invention can be also practiced by other embodiments.

[0155] For example, the transistor cell 18 may be an IGBT cell having a planar-gate structure or a trench-gate structure. In this case, a p.sup.+ type SiC substrate 27 may be used in place of the n.sup.+ type SiC substrate 27 in FIGS. 4 and 13. Alternately, the various types of the structures of semiconductor elements may be formed in the active region 2.

[0156] Further, the surface electrode of the source metal 43 or the schottky metal 82 does not need to be made of metal, and may be a semiconductor electrode such as polysilicon.

[0157] Further, the embedded resistor 21 does not need to be embedded in the interlayer film 36 under the gate metal 44, and instead, for example, polysilicon wiring for connecting the gate metal 44 and the gate finger 5 may be formed as an embedded resistor.

[0158] Further, a material having a resistance value that is greater than or equal to that of the gate metal 44 and the gate finger 5 (for example, metal wiring made of aluminum (Al), aluminum-copper alloy (AlCu), copper (Cu)) may be used as the material of the embedded resistor 21 instead of polysilicon. The total resistance value of the resistance value of the gate electrode 19 and the resistance value of the embedded resistor 21 can be increased because the distance between the gate metal 44 and the gate finger 5 can be increased, even though the embedded resistor 21 is made of metal.

[0159] Further, the embedded resistor 21 does not need to be formed under the gate metal 44, and may be formed under, for example, the gate finger 5.

[0160] Further, the embedded resistor 21 may be linearly formed along the part of the peripheral edge 24 of the gate metal 44, or may be annularly formed along the entire circumference of the peripheral edge 24 of the gate metal 44.

[0161] Further, the conductivity type of each semiconductor portion may be reversed in the semiconductor device 1. For example, p type may be changed to n type, and vice versa in the semiconductor device 1.

[0162] It is to be understood that variations and modifications can be made without departing from the scope and spirit of the present invention.

[0163] This application corresponds to Patent Application No. 2014-102699 submitted to Japanese Patent Office on May 16, 2014, and the entire contents of this application are hereby incorporated by reference.

DESCRIPTION OF THE REFERENCE NUMERALS

[0164] 1 Semiconductor device [0165] 2 Active region [0166] 18 Transistor cell [0167] 19 Gate electrode [0168] 27 SiC substrate [0169] 28 SiC epitaxial layer [0170] 29 p.sup. type body region [0171] 30 n.sup.+ source region [0172] 31 p.sup.+ body contact region [0173] 32 Channel region [0174] 35 Gate insulating film [0175] 36 Interlayer film [0176] 39 Gate trench [0177] 40 Passivation film [0178] 43 Source metal [0179] 44 Gate metal [0180] 47 Insulating film [0181] 51 p.sup. type region [0182] 52 p.sup.+ type region [0183] 53 Guard ring [0184] 54 Dicing region [0185] 55 p.sup. type region [0186] 56 p.sup.+ type region [0187] 57 Wafer [0188] 58 Dicing line [0189] 59 End surface [0190] 60 Depletion layer [0191] 61 Insulating film under metal [0192] 62 End insulating film [0193] 63 Contact hole [0194] 64 Overlap portion [0195] 65 Ti/TiN film [0196] 66 AlCu film [0197] 67 n-type region [0198] 69 overlapped portion [0199] 72 Semiconductor device [0200] 73 Semiconductor device [0201] 74 Semiconductor device [0202] 75 Semiconductor device [0203] 76 Semiconductor device [0204] 77 Semiconductor device [0205] 78 Semiconductor device [0206] 79 Semiconductor device [0207] 80 Recess [0208] 81 Schottky-barrier diode [0209] 82 Schottky metal