DISPLAY PANEL AND DISPLAY DEVICE
20170110081 ยท 2017-04-20
Assignee
- Boe Technology Group Co., Ltd. (Beijing, CN)
- Beijing Boe Optoelectronics Technology Co., Ltd. (Beijing, CN)
Inventors
- Shuai Han (Beijing, CN)
- Lingyun Shi (Beijing, CN)
- Hao Zhang (Beijing, CN)
- Quanhua HE (Beijing, CN)
- Bo Gao (Beijing, CN)
- Jialong LI (Beijing, CN)
- Di Wang (Beijing, CN)
- Wei Wang (Beijing, CN)
Cpc classification
H02M3/07
ELECTRICITY
G09G2310/0291
PHYSICS
G09G2310/0286
PHYSICS
International classification
Abstract
A display panel and a display device are disclosed. The display panel includes an array substrate (21) and a driving IC (11). The array substrate (21) includes a shift register (211). The shift register (211) includes a plurality of shift register units (2111) which are connected in multi stages. The array substrate (21) further includes a charge pump (22) which is connected with each of the shift register units (2111). An input terminal of the charge pump (22) is connected with the driving IC (11). An output terminal of the charge pump (22) is connected with each of the shift register units (2111). According to the disclosure, a charge pump is disposed on the array substrate, so as to lower a cost of the display panel.
Claims
1. A display panel, comprising an array substrate and a driving IC, the array substrate comprising a shift register which comprises a plurality of shift register units which are connected in multi stages, wherein the array substrate further comprises a charge pump which is connected with each of the shift register units, an input terminal of the charge pump is connected with the driving IC, and an output terminal of the charge pump is connected with each of the shift register units.
2. The display panel of claim 1, wherein the charge pump is configured to amplify a voltage signal output from the driving IC and output the amplified voltage signal to each of the shift register units.
3. The display panel of claim 1, wherein each stage of the shift register units is connected with a group of gate lines, every two adjacent rows of the gate lines form a group of gate lines, and the gate lines of different groups do not share a common gate line.
4. The display panel of claim 1, wherein the array substrate comprises a first shift register disposed at a left bazel of the display panel, a second shift register disposed at a right bazel of the display panel, a first charge pump connected with the first shift register and a second charge pump connected with the second shift register.
5. The display panel of claim 4, wherein each stage of the shift register units of the first shift register and a same stage of the shift register units of the second shift register are connected with a same group of the gate lines, every two adjacent rows of the gate lines form a group of gate lines, and the gate lines of different groups do not share a common gate line.
6. The display panel of claim 4, wherein each stage of the shift register units of the first shift register is connected with odd-numbered rows of the gate lines, and each stage of the shift register units of the second shift register is connected with even-numbered rows of the gate lines; or each stage of the shift register units of the first shift register is connected with even-numbered rows of the gate lines, and each stage of the shift register units of the second shift register is connected with odd-numbered rows of the gate lines.
7. The display panel of claim 1, wherein the shift register comprises N stages of shift register units, an input signal of n-th stage of the shift register units is supplied by an output of (n1)-th stage of the shift register units, and a reset signal of n-th stage of the shift register units is supplied by an output of (n+1)-th stage of the shift register units, wherein 1<n<N, and N is a positive integer larger than 1.
8. The display panel of claim 1, wherein each stage of the shift register units comprises a first input terminal configured to be input a high level signal and a second input configured to be input a low level signal, and the first and second input terminals are connected with a first output terminal configured to output the high level signal and a second output terminal configured to output the low level signal of the charge pump, respectively.
9. The display panel of claim 1, wherein each stage of the shift register units is an identical shift register unit.
10. A display device comprising the display panel of claim 1.
11. The display panel of claim 2, wherein each stage of the shift register units is connected with a group of gate lines, every two adjacent rows of the gate lines form a group of gate lines, and the gate lines of different groups do not share a common gate line.
12. The display panel of claim 2, wherein the array substrate comprises a first shift register disposed at a left bazel of the display panel, a second shift register disposed at a right bazel of the display panel, a first charge pump connected with the first shift register and a second charge pump connected with the second shift register.
13. The display panel of claim 3, wherein the array substrate comprises a first shift register disposed at a left bazel of the display panel, a second shift register disposed at a right bazel of the display panel, a first charge pump connected with the first shift register and a second charge pump connected with the second shift register.
14. The display panel of claim 5, wherein each stage of the shift register units of the first shift register is connected with odd-numbered rows of the gate lines, and each stage of the shift register units of the second shift register is connected with even-numbered rows of the gate lines; or each stage of the shift register units of the first shift register is connected with even-numbered rows of the gate lines, and each stage of the shift register units of the second shift register is connected with odd-numbered rows of the gate lines.
15. The display panel of claim 2, wherein the shift register comprises N stages of shift register units, an input signal of n-th stage of the shift register units is supplied by an output of (n1)-th stage of the shift register units, and a reset signal of n-th stage of the shift register units is supplied by an output of (n+1)-th stage of the shift register units, wherein 1<n<N, and N is a positive integer larger than 1.
16. The display panel of claim 3, wherein the shift register comprises N stages of shift register units, an input signal of n-th stage of the shift register units is supplied by an output of (n1)-th stage of the shift register units, and a reset signal of n-th stage of the shift register units is supplied by an output of (n+1)-th stage of the shift register units, wherein 1<n<N, and N is a positive integer larger than 1.
17. The display panel of claim 4, wherein the shift register comprises N stages of shift register units, an input signal of n-th stage of the shift register units is supplied by an output of (n1)-th stage of the shift register units, and a reset signal of n-th stage of the shift register units is supplied by an output of (n+1)-th stage of the shift register units, wherein 1<n<N, and N is a positive integer larger than 1.
18. The display panel of claim 5, wherein the shift register comprises N stages of shift register units, an input signal of n-th stage of the shift register units is supplied by an output of (n1)-th stage of the shift register units, and a reset signal of n-th stage of the shift register units is supplied by an output of (n+1)-th stage of the shift register units, wherein 1<n<N, and N is a positive integer larger than 1.
19. The display panel of claim 2, wherein each stage of the shift register units comprises a first input terminal configured to be input a high level signal and a second input configured to be input a low level signal, and the first and second input terminals are connected with a first output terminal configured to output the high level signal and a second output terminal configured to output the low level signal of the charge pump, respectively.
20. The display panel of claim 3, wherein each stage of the shift register units comprises a first input terminal configured to be input a high level signal and a second input configured to be input a low level signal, and the first and second input terminals are connected with a first output terminal configured to output the high level signal and a second output terminal configured to output the low level signal of the charge pump, respectively.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus the skilled in this art can obtain other drawings from these drawings without any inventive work.
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DETAILED DESCRIPTION
[0028] In order to make objects, technical details and advantages of the embodiments of the invention apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. Apparently, the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.
[0029] Unless defined otherwise, all the technical and scientific terms used herein have meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms, such as first, second or the like, which are used in the description and the claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but for distinguishing various components. Also, the terms, such as a/an, one, the/said or the like, are not intended to limit the amount, but for indicating the existence of at lease one element. The terms, such as connection/connecting/connected, or the like, are not intended to define a physical connection or mechanical connection, but may include an electrical connection/coupling, direct or indirect. The terms, such as on, under, left, right, or the like, are only used to indicate relative position relationship, and when the position of the object which is described is changed, the relative position relationship may be changed accordingly. A thickness and shape of thin films of the drawings does not reflect a real proportion, and it only illustrates the disclosure.
[0030] Embodiments of the disclosure provide a display panel and a display device, wherein a charge pump is disposed on an array substrate, so as to reduce a cost of the display panel and increase product competitiveness of the display panel.
[0031] Technical solutions according to the embodiments of the disclosure will be particularly described below in connection with the accompanying drawings.
Embodiment One
[0032] Referring to
[0033] It should be noted that, in the display panel, the array substrate is disposed on the driving IC. Compared to
[0034] A manner of connection in multiple stages of the shift register units will be briefly introduced to make a principle of the shift register more clear. For example, referring to
[0035] Each stage of the shift register unit is further provided with two input terminals, configured to be input a high level signal VGH and a low level signal VGL respectively, and the two input terminals are connected with a first output terminal configured to be output the high level signal VGH and a second output terminal configured to be output the low level signal VGL of the charge pump 22, respectively.
[0036] For example, the charge pump 22 is configured to amplify a voltage signal output from the driving IC 11, and output the amplified voltage signal to each of the shift register units 2111.
[0037] The output voltages of the driving IC 11 are VSP and VSN, the output voltages charges a capacitor which control transmittance of pixel units, wherein the VSP is a positive voltage and the VSN is a negative voltage. The charge pump 22 is configured to amplify the voltage signals VSP and VSN, to obtain a high level signal VGH and a low level signal VGL which are used to input the shift register 211. The low level signal VGL and the high level signal VGH are supplied to the shift register 211 so as to output scan signals for driving gate electrodes.
[0038] In this embodiment, the charge pump 22 is disposed on the array substrate 21, so that the charge pump 22 amplifies the voltages VSP and VSN to generate the high level signal VGH and the low level signal VGL and output them to each of the shift register units 2111 when the driving IC 11 outputs voltage signals VSP and VSN to the charge pump. Because all the charge pumps 22 and each of the shift register units 2111 are disposed on the array substrate 21, a distance between the charge pump and each of the shift register units is reduced, so as to reduce a period for transmitting signals.
[0039] For example, referring to
[0040] It should be noted that, an output terminal of each stage of the shift register units can be connected with two rows of gate lines simultaneously, so that when the shift register unit outputs a high level, the two rows of gate lines connected with the shift register unit are scanned simultaneously, to achieve a narrow bazel design when the display panel is a super high definition or a high definition display panel.
[0041] For example, when both right and left bazels of the array substrate are provided with shift registers, the array substrate comprises a first charge pump which is connected with a shift register disposed at the left bazel and a second charge pump which is connected with a shift register disposed at the right bazel.
[0042] It should be noted that, the first charge pump and the second charge pump have a same configuration. The first charge pump and the second charge pump can be a same charge pump or may be two identical charge pumps. This is not limited in the embodiment of the disclosure.
[0043] Both the left and right bazels are provided with a charge pump, so that when the charge pump disposed at the left bazel can not be operated normally, the display panel can provide voltage signals to the shift register units through the charge pump disposed at the right bazel to drive gate lines such that the display panel can work normally; or when the charge pump disposed at the right bazel can not be operated normally, the display panel can provide voltage signals to the shift register units through the charge pump disposed at the left bazel to drive the gate lines, such that the display panel can be operated normally.
[0044] In an example, referring to
[0045] Each stage of the shift register units of the shift register disposed at the left bazel and a same stage of the shift register units of the shift register disposed at the right bazel are connected with a same group of the gate lines, to achieve a narrow bazel design. Particularly, in operation, the shift register disposed at the left bazel or the shift register disposed at the right bazel can be operated alone, so that when the shift register disposed at the left bazel can not be operated normally, the shift register disposed at the right bazel can be operated to drive the gate lines and the two rows of the gate lines can be driven simultaneously, to make the display panel be operated normally and to achieve the narrow fame design; or when the shift register disposed at the right bazel can not be operated normally, the shift register disposed at the left bazel can be operated to drive the gate lines and the two rows of the gate lines can be driven simultaneously, to make the display panel to be operated normally and to achieve the narrow bazel design.
[0046] In another example, referring to
[0047] Alternatively, each stage of the shift register units 2111 of the shift register 211 disposed at the left bazel is connected with even-numbered rows of the gate lines, and each stage of the shift register units 2111 of the shift register 211 disposed the right bazel is connected with odd-numbered rows of the gate lines.
[0048] In operation, when each stage of the shift register units 2111 of the shift register 211 disposed at the left bazel is connected with odd-numbered rows of the gate lines, and each stage of the shift register units 2111 of the shift register 211 disposed at the right bazel is connected with even-numbered rows of the gate lines, the shift register units disposed in the left bazel and the right bazel scan alternately, that is, a first stage of the shift register units disposed at the left bazel scans a first row of the gate line, and then a first stage of the shift register units disposed at the right bazel scans a second row of the gate line, and a second stage of the shift register units disposed at the left bazel scans a third row of the gate line, and then a second stage of the shift register units disposed at the right bazel scans a fourth row of the gate line, and so on, so as to scan all of the gate lines.
[0049] Each stage of the shift register units of the shift register disposed at the left bazel is connected with odd-numbered rows of the gate lines, and each stage of the shift register units of the shift register disposed at the right bazel is connected with even-numbered rows of the gate lines, to achieve a narrow bazel design.
[0050] Another embodiment of the disclosure provides a display device, comprising the display panel according to above embodiments of the disclosure.
[0051] In summary, a display panel according to embodiments of the disclosure comprises an array substrate and a driving IC, wherein the array substrate comprises a shift register, which comprises a plurality of same shift register units which are connected in multi stages. The array substrate further comprises a charge pump which is connected with each of the shift register units. An input terminal of the charge pump is connected with the driving IC, and an output terminal of the charge pump is connected with each of the shift register units. The charge pump is disposed on the array substrate, to save the charge pump on the flexible circuit board, so as to lower a cost of the display panel and increase product competitiveness of the display panel.
[0052] The above mentioned embodiments are only exemplary, and can not be construed as a limit to the disclosure. One of ordinary skill in the art can make various variations and modifications without departing from the spirit and the scope of the disclosure, and thus all of equivalent technical solutions fall into the scope of the disclosure and the scope of the disclosure are defined by the accompanying claims.