Imprinted Memory

Abstract

Although photolithography is the preferred pattern-transfer method for even the 10 nm electrically-programmable memory (EPM, which comprises only periodic patterns), imprint-lithography is the preferred method to form the sub-25 nm printed memory (which comprises at least one non-periodic data-pattern). Accordingly, the present invention discloses an imprinted memory.

Claims

1. A method of manufacturing an imprinted memory, comprising the steps of: 1) forming a plurality of bottom address lines; 2) forming a data-coding layer above said bottom address lines; 3) transferring a data-pattern to said data-coding layer using imprint-lithography; 4) forming a plurality of top address lines above said data-coding layer; wherein said data-pattern represents the data stored in said imprinted memory; the dimension of said data-pattern is less than 50 nm; and, said data-pattern is a non-periodic pattern.

2. The method according to claim 1, wherein said imprinted memory is a cross-point memory.

3. The method according to claim 1, where said imprinted memory is a three-dimensional imprinted memory (3D-iP).

4. The memory according to claim 1, wherein said imprint-lithography is nanoimprint lithography (NIL).

5. The method according to claim 4, wherein said imprint-lithography is thermoplastic-NIL.

6. The method according to claim 4, wherein said imprint-lithography is photo-NIL.

7. The method according to claim 4, wherein said imprint-lithography is resist-free direct thermal-NIL.

8. The method according to claim 4, wherein said imprint-lithography is electro-chemical NIL.

9. The method according to claim 4, wherein said imprint-lithography is laser-assisted direct imprint-lithography.

10. The method according to claim 1, wherein said imprint-lithography uses full-wafer imprint or step-and-repeat imprint.

11. An imprinted memory, comprising: a plurality of bottom address lines; a data-coding layer above said bottom address lines, wherein said data-coding layer comprising a data-pattern formed by imprint-lithography; a plurality of top address lines above said data-coding layer; wherein said data-pattern represents the data stored in said imprinted memory; the dimension of said data-pattern is less than 50 nm; and, said data-pattern is a non-periodic pattern.

12. The memory according to claim 11, wherein said imprinted memory is a cross-point memory.

13. The memory according to claim 11, where said imprinted memory is a three-dimensional imprinted memory (3D-iP).

14. The memory according to claim 11, wherein said imprint-lithography is nanoimprint lithography (NIL).

15. The memory according to claim 14, wherein said imprint-lithography is thermoplastic-NIL.

16. The memory according to claim 14, wherein said imprint-lithography is photo-NIL.

17. The memory according to claim 14, wherein said imprint-lithography is resist-free direct thermal-NIL.

18. The memory according to claim 14, wherein said imprint-lithography is electro-chemical NIL.

19. The memory according to claim 14, wherein said imprint-lithography is laser-assisted direct imprint-lithography.

20. The memory according to claim 11, wherein said imprint-lithography uses full-wafer imprint or step-and-repeat imprint.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 illustrates a data-pattern in a mask-ROM.

[0020] FIGS. 2A-2C discloses processing steps of a preferred imprint-lithography.

[0021] FIGS. 3A-3B are top views of the data-pattern on two preferred data-templates.

[0022] FIG. 4 illustrates a preferred three-dimensional imprinted memory (3D-iP).

[0023] It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.

[0025] The present invention discloses an imprinted memory. Because photolithography cannot be used to form the sub-50 nm non-periodic data-pattern, imprint-lithography is used. It creates pattern by mechanical deformation of imprint resist and subsequent processes (referring to Chou et al. Imprint-lithography with 25-nanometer resolution, Science, Vol. 272, No. 5258, pp. 85-87, 1996). Imprint-lithography includes thermoplastic-NIL, photo-NIL, resist-free direct thermal-NIL, electro-chemical NIL, laser-assisted direct imprint lithography. Imprint-lithography may use a full-wafer imprint scheme, or a step-and-repeat imprint scheme.

[0026] FIGS. 2A-2C discloses processing steps of a preferred imprint-lithography. These figures are the cross-sectional views along the cut-line AA of FIG. 1. These steps are used to physically record data for the memory of FIG. 1. This preferred imprint-lithography is thermoplastic-NIL. Its detailed processing steps are as follows. First of all, the data-coding layer (e.g. an insulating dielectric) 87 is formed on a bottom layer 89 (e.g. an address line). Then a thin layer of imprint resist (e.g. thermoplastic polymer) 85 is spin coated on the data-coding layer 87 (FIG. 2A). A template 81 is brought into contact with the imprint resist 85 and they are pressed together under certain pressure. When heated up above the glass transition temperature of the polymer, the pattern on the template 81 is pressed into the softened polymer film. After being cooled down, the template 81 is separated from the wafer (FIG. 2B). Finally, an etching process is carried out to transfer the pattern in the resist 85 to the data-coding layer 87 (FIG. 2C).

[0027] Another preferred imprint-lithography is photo-NIL. In the photo-NIL, a UV-curable liquid resist is applied to the data-coding layer. After the template and the substrate are pressed together, the resist is cured in the UV light and becomes solid. After template separation, a similar pattern transfer process can be used to transfer the pattern in resist onto the underneath material. Besides thermoplastic-NIL and photo-NIL, other imprint-lithography methods are well known in the art.

[0028] The template 81 has a predefined topological pattern. It comprises a plurality of islands 83, which protrudes out of a surface of the template. The dimension of these islands (i.e. data-pattern) is less than 50 nm. The absence or existence of an island at a location on the template determines on the state of the memory cell corresponding to this location. For example, if the location for a memory cell (e.g. 5ab) has no island, then this memory cell has no data-opening (FIG. 1) and is in state 0; on the other hand, if the location for a memory cell (e.g. 5aa) has an island 83, then this memory cell has a data-opening (FIG. 1) and is in state 1. Note that, after imprint-lithography, the shape of the imprint resist 85 is inverse to the shape of the template 81.

[0029] FIG. 3A illustrates the data-pattern on a preferred data-template 81. The minimum feature size F of its island (e.g. the one at the location 5aa) could be larger than, preferably twice as much as, the minimum feature size f of the imprinted memory, e.g. the minimum half-pitch (or, the width) of its address lines (referring to Zhang). Accordingly, the data-template 81 is also referred to as xf-template (with x>1, preferably 2). This can significantly lower the data-template cost. For example, a 25 nm imprinted memory can use a 50 nm data-template. In this preferred embodiment, the islands 83 have a rectangular shape.

[0030] FIG. 3B illustrates the data-pattern on another preferred data-template 81. Its island (e.g. the one at the location 5aa) has a circular cylinder shape. Alternatively, these islands could have a cone shape, a pyramidal shape, or an asymmetrically polygonal shape. These shapes can be easily formed by electron beams that directly write data onto the data-template 81. Note that the data-patterns in FIGS. 3A and 3B are non-periodic, whereas the storage-hole pattern in Lee is periodic.

[0031] In imprint-lithography, the target pattern (i.e. the pattern formed in the data-coding layer) is an exact 1:1 copy of the source pattern (i.e. the pattern on the data-template). Because imprint-lithography is a mechanical process and would not be interfered by any optical effects (e.g. optical diffraction or optical distortion), periodicity of the target pattern has no effect on the source pattern. That means that imprint-lithography makes as good non-periodic pattern-transfer as periodic pattern-transfer. Thus, the data-template doses not need to use any RET and can readily transfer sub-50 nm non-periodic data-pattern to the data-coding layer.

[0032] Imprint-lithography can be used in three-dimensional printed memory (3D-P). Accordingly, the present invention discloses a three-dimensional imprinted memory (3D-iP). It uses imprint-lithography to record data into various memory levels. FIG. 4 illustrates a preferred 3D-iP. It uses imprint-lithography to record data. The 3D-iP is a diode-based cross-point memory. It comprises a semiconductor substrate 0 and a 3-D stack 16 stacked above. The 3-D stack 16 comprises M(M2) vertically stacked memory levels (e.g. 16A, 16B). Each memory level (e.g. 16A) comprises a plurality of upper address lines (e.g. 2a), lower address lines (e.g. 1a) and memory cells (e.g. 5aa). Each memory cell comprises a diode 3d and stores n (n1) bits. Each memory level further comprises at least a data-recording layer, such as an insulating dielectric 87, a resistive layer (referring to U.S. patent application Ser. No. 12/785,621) or an extra-dopant layer (referring to U.S. Pat. No. 7,821,080). Data are recorded into the data-coding layer of the memory levels using imprint-lithography. Memory levels (e.g. 16A, 16B) are coupled to the substrate 0 through contact vias (e.g. 1av, 1av). The substrate circuit 0X in the substrate 0 comprises a peripheral circuit for the 3-D stack 16.

[0033] While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. The invention, therefore, is not to be limited except in the spirit of the appended claims.