Adaptively controlled pre-distortion circuits for RF power amplifiers

Abstract

A system includes a crest-factor reduction circuit, a signal analyzer, and a pre-distortion circuit. The crest-factor reduction circuit reduces a crest factor of a baseband signal and generates a feedforward signal. The signal analyzer generates parameters based on the feedforward signal and an output signal from a power amplifier. The pre-distortion circuit generates a pre-distorted baseband signal based on the parameters for input to the power amplifier.

Claims

1. A system comprising: a crest-factor reduction circuit that reduces a crest factor of a baseband signal and that generates a feedforward signal; a signal analyzer that generates parameters based on the feedforward signal and an output signal from a power amplifier; a pre-distortion circuit that generates a pre-distorted baseband signal based on the parameters for input to the power amplifier; and an over-sampler that increases a data rate of the feedforward signal by at least a factor of 2.

2. The system of claim 1 wherein the pre-distortion circuit generates the pre-distorted baseband signal by applying a memoryless nonlinear gain and a polynomial function to the baseband signal.

3. The system of claim 2 wherein the memoryless nonlinear gain is applied after a unit delay to the baseband signal.

4. The system of claim 1 further comprising: an up-converter that converts the pre-distorted baseband signal based on a timing signal to a pre-distorted signal input to the power amplifier, wherein the signal analyzer comprises: a downconverter that converts the output signal from the power amplifier based on the timing signal to a first signal that is at baseband or at a near-baseband intermediate frequency; an analog-to-digital converter that converts the first signal to a second signal; and a signal analysis circuit that generates the parameters based on the second signal and the feedforward signal.

5. The system of claim 4 wherein the signal analysis circuit performs one or more of DC offset correction, frequency offset correction, I/Q imbalance correction, delay matching, and gain adjustment on one or more of the second signal and the feedforward signal.

6. The system of claim 4 wherein the signal analysis circuit generates the parameters based on minimizing a difference between the second signal and the feedforward signal.

7. The system of claim 2 wherein the polynomial function is based on the baseband signal and a delayed version of the baseband signal and comprises a power of a modulus of the baseband signal and a power of a modulus of the delayed version of the baseband signal.

8. A system comprising: a crest-factor reduction circuit that reduces a crest factor of a baseband signal and that generates a feedforward signal; a signal analyzer that generates parameters based on the feedforward signal and an output signal from a power amplifier; and a pre-distortion circuit that generates a pre-distorted baseband signal based on the parameters for input to the power amplifier, wherein the pre-distortion circuit generates the pre-distorted baseband signal by applying a memoryless nonlinear gain and a polynomial function to the baseband signal, and wherein the polynomial function is based on the baseband signal and a delayed version of the baseband signal and comprises a power of a modulus of the baseband signal and a power of a modulus of the delayed version of the baseband signal.

9. The system of claim 8 wherein the memoryless nonlinear gain is applied after a unit delay to the baseband signal.

10. The system of claim 8 further comprising an over-sampler that increases a data rate of the feedfoward signal by at least a factor of 2.

11. The system of claim 8 further comprising: an up-converter that converts the pre-distorted baseband signal based on a timing signal to a pre-distorted signal input to the power amplifier, wherein the signal analyzer comprises: a downconverter that converts the output signal from the power amplifier based on the timing signal to a first signal that is at baseband or at a near-baseband intermediate frequency; an analog-to-digital converter that converts the first signal to a second signal; and a signal analysis circuit that generates the parameters based on the second signal and the feedforward signal.

12. The system of claim 11 wherein the signal analysis circuit performs one or more of DC offset correction, frequency offset correction, I/Q imbalance correction, delay matching, and gain adjustment on one or more of the second signal and the feedforward signal.

13. The system of claim 11 wherein the signal analysis circuit generates the parameters based on minimizing a difference between the second signal and the feedforward signal.

14. A system comprising: a downconverter that converts an output signal from a power amplifier to a first signal that is at baseband or at a near-baseband intermediate frequency; an analog-to-digital converter that converts the first signal to a second signal; a signal analysis circuit that generates parameters based on the second signal and a feedforward signal representative of a baseband signal; an analog-to-digital converter enhancer circuit that receives from the signal analysis circuit a third signal representing a clock period of the feedforward signal; and a pre-distortion circuit that generates a pre-distorted baseband signal based on the parameters for input to the power amplifier.

15. The system of claim 14 further comprising a crest-factor reduction circuit that reduces a crest factor of the baseband signal and that generates the feedforward signal.

16. The system of claim 14 wherein the pre-distortion circuit generates the pre-distorted baseband signal by applying a memoryless nonlinear gain and a polynomial function to the baseband signal.

17. The system of claim 16 wherein the memoryless nonlinear gain is applied after a unit delay to the baseband signal.

18. The system of claim 16 wherein the polynomial function is based on the baseband signal and a delayed version of the baseband signal and comprises a power of a modulus of the baseband signal and a power of a modulus of the delayed version of the baseband signal.

19. The system of claim 14 further comprising an over-sampler that increases a data rate of the feedfoward signal by at least a factor of 2.

20. The system of claim 14 further comprising: an up-converter that converts the pre-distorted baseband signal based on a timing signal to a pre-distorted signal input to the power amplifier, wherein the downconverter converts the output signal from the power amplifier to the first signal based on the timing signal.

21. The system of claim 14 wherein the analog-to-digital converter enhancer circuit comprises: a digital-to-analog circuit that converts the third signal from the signal analysis circuit to a first output; and a summer that generates a second output based on the first output and the first signal from the downconverter, wherein the second output is input to the analog-to-digital converter.

22. The system of claim 14 wherein the analog-to-digital converter enhancer circuit comprises: a first digital-to-analog circuit that converts the third signal from the signal analysis circuit to a first output; a first summer that generates a second output based on the first output and the first signal from the downconverter; cascaded first and second tracking-and-hold circuits operated by complementary clock signals that generate a held signal based on the second output; a second digital-to-analog converter that converts the third signal from the signal analysis circuit to a third output; and a second summer that generates a fourth output based on the held signal and the third output, wherein the fourth output is input to the analog-to-digital converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of system 100, according to one embodiment of the present invention.

(2) FIG. 2 is block diagram 200 representing a model of the operations carried out in DPD processor 106, according to one embodiment of the present invention.

(3) FIG. 3 shows arithmetic-logic circuit 300 in one implementation of DPD processor 106 according to low-complexity model 200 of FIG. 2.

(4) FIG. 4 is a block diagram of system 400, according to one embodiment of the present invention.

(5) FIG. 5 is a block diagram of digital waveform matching circuit 500, which implements a method for measuring relative waveform distortion, according to one embodiment of the present invention.

(6) FIG. 6 is a block diagram of system 600, in accordance with one embodiment of the present invention.

(7) FIG. 7 shows waveform matching circuit 700, which performs DC offset correction, I/Q imbalance correction, frequency offset correction, linear distortion correction, delay matching, and complex gain matching, in accordance with one embodiment of the present invention.

(8) FIG. 8 shows system 800, which CFR processor 104, DPD processor 106, and signal analyzer 612, quadrature down-converter 110 are integrated into a single integrated circuit, in accordance with one embodiment of the present invention.

(9) FIG. 9 is a block diagram of system 900, including enhanced ADC 911, in accordance with one embodiment of the present invention.

(10) FIG. 10 is a block diagram showing enhanced ADCs 1011a and 1011b for the down-converted in-phase and quadrature analog signals derived from RF feedback signal 115, respectively, in accordance with one embodiment of the present invention.

(11) FIG. 11 shows waveform-transform circuit 1100, providing complex-valued digital signal D.sub.I+jD.sub.Q, in accordance with one embodiment of the present invention.

(12) FIG. 12 is a block diagram showing two-stage ADC-enhancer circuit 1200, in accordance with one embodiment of the present invention.

(13) To simplify the detailed description below and to allow cross-reference among the figures, like elements are assigned like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) FIG. 1 is a block diagram of system 100, according to one embodiment of the present invention. System 100 integrates crest-factor reduction (CFR) and digital pre-distortion (DPD) operations on a transceiver integrated circuit that is represented by circuit block 101 of FIG. 1. The transceiver circuit may be implemented using a mixed-signal CMOS process (e.g. 65-nm CMOS at this time). As shown in FIG. 1, baseband data source 103 provides a complex baseband signal to be transmitted (e.g., a 4-carrier WCDMA or 20-MHz LTE signal). Circuit block 101, which receives the baseband signal data and signal parameters 118 (not shown; provided over SPI Bus 113) from a signal analyzer circuit 102, includes CFR processor 104, double sampler 105, DPD processor 106 and digital-to-RF up-converter 107. CFR processor 104 reduces the peak-to-average power ratio (PAR) of the input complex baseband signal. The output signal of CFR processor 104 may have a sampling rate of 34 times the bandwidth of the complex baseband signal (e.g. 61.44 MS/s for a 4-carrier WCDMA or 20-MHz LTE signal). The sampling rate is doubled by double sampler 105 to 68 times the signal bandwidth of the complex baseband signal (e.g. 122.88 MS/s for a 20-MHz LTE) before being provided to DPD processor 106. The output signal from digital-to-RF 107 is the analog signal to be transmitted that is modulated on one or more RF carrier signals and pre-distorted for linearity in power amplifier 108. CFR processor 104 may implement any of a number of crest factor reduction techniques, e.g., the crest factor reduction techniques disclosed in copending U.S. patent application (Copending Application), Ser. No. 13/897,119, entitled Crest Factor Reduction for Band-Limited Multi-Carrier Signals, filed on May 17, 2013. The disclosure of Copending Application is hereby incorporated by reference in its entirety.

(15) The output signal 115 of power amplifier 108 is fed back in system 100 through another CMOS integrated circuit, represented by circuit block 102. Circuit block 102 represents a signal-analyzer integrated circuit, which is used for adaptive control of DPD operations of system 100. As shown in FIG. 1, circuit block 102 includes quadrature down-converter 110, which down-converts the feedback signal 115. The down-converted analog signal is converted into digital representation (i.e., digital signal 117) using ADCs 111. Digital circuit 112 analyzes digital signal 117 to provide signal parameters 118. Unlike circuit block 101, circuit block 102 may be implemented using a less expensive CMOS process, and may also include other circuit blocks (e.g. a circuit for controlling the bias voltages of power amplifier 108). Communication between the circuits of circuit blocks 101 and 102 may also be conducted over industry standard data communication protocol, such as that implemented in an industry standard SPI bus (represented by SPI bus 113 in FIG. 1).

(16) FIG. 2 is block diagram 200 representing a model of the operations carried out in DPD processor 106, according to one embodiment of the present invention. As shown in FIG. 2, DPD processor 106 receives a sequence of complex samples {x.sub.k} and outputs a complex sequence {y.sub.k}. The discrete-time input-output relation of DPD processor 106 may be represented by:
y.sub.k=x.sub.klG(|x.sub.kl|;v.sub.1)+P(x.sub.k,x.sub.k1, . . . ,x.sub.kN;v.sub.2)(1)
where xG(|x|; v.sub.1) is a memory-less non-linearity (with vector parameter v.sub.1 represented by block 201 in FIG. 2. The memory-less non-linearity of block 201 is applied to a copy of the input signal delayed in delay element 202 by samples, N is the memory span of DPD processor 106 (e::; N) and P is a non-linear function (with vector parameter v.sub.2) of N+1 complex variables, which is represented by block 203 in FIG. 2. Vector parameters v.sub.1 and v.sub.2 may be, for example, some of signal parameters 118 received from the signal analyzer of circuit block 102 of FIG. 1. Memory-less non-linearity of block 201 may be seen as a complex gain which depends only on the instantaneous amplitude of the input signal.

(17) The non-linear function P(x.sub.k,x.sub.k1, . . . , x.sub.kN; v.sub.2) of block 203, also referred to as the memory kernel, mitigates memory effects in power amplifier 108, which can impose a fundamental limit on the performance of DPD processor 106, as such memory effects are difficult to fully compensate for. The memory kernel may be implemented using many possible algorithms, such as memory polynomials, discrete-time Volterra series, and artificial neural networks. DPD processors in the prior art are typically complicated datapath processors because of the complexity of the algorithms implemented (e.g. discrete-time Volterra series with a large number of terms, and adaptation algorithms with extremely high computational complexity). Complex adaption algorithms include, for example, parameter estimations of complicated behavior models). The present inventors discover that the computation complexity of both the DPD processor 106 and the adaptation algorithms may be reduced. According to one embodiment of invention, DPD processor 106 may implement the following input-output relation:

(18) $\begin{array}{cc}{y}_k=x_{k-1}G\left(.Math.x_{k-1}.Math.;v_1\right)+j{c}_0\left(x_k-x_{k-2}\right)+x_{k-1}\left(c_1.Math.x_k.Math.+c_2{.Math.x_k.Math.}^2+c_3{.Math.x_k.Math.}^4+c_4.Math.x_{k-2}.Math.+c_5{.Math.x_{k-2}.Math.}^2+c_6{.Math.x_{k-2}.Math.}^4\right)+x_k(c_1.Math.x_k.Math.+c_8{.Math.x_k.Math.}^2+c_9{.Math.x_k.Math.}^4+x_{k-2}\left(c_{10}.Math.x_{k-2}.Math.+c_{11}{.Math.x_{k-2}.Math.}^2+c_{12}{.Math.x_{k-2}.Math.}^4\right)& \left(2\right)\end{array}$
where j={square root over (1)}, c.sub.0 is a real number and the c, coefficients, 1nN, are complex values. Laboratory experiments show that the low-complexity equation (2) can be implemented in a straightforward manner to deliver a surprisingly high performance over a wide range of power amplifiers, including those power amplifiers that are based on LDMOS, GaN, SiGe-HBT, GaAs and other types of transistors.

(19) FIG. 3 shows arithmetic-logic circuit 300 in one implementation of DPD processor 106 according to low-complexity model 200 of FIG. 2. In fact, as shown in FIG. 3, arithmetic-logic circuit 300 may be used to implement equation (2) above. Arithmetic-logic circuit 300 includes amplitude detector 319 which provides the absolute value of each incoming digital sample received from input terminal 301. The absolute values of digital samples at various delays are used, for example, in the non-linear gain and the polynomial terms of Equation (2).

(20) Each digital sample may be represented, for example, by a fixed-point complex number in rectangular coordinate form. As some complex number computations may be simpler if carried out in polar coordinate form, amplitude detector 319 may use the CORDIC algorithm to convert a complex number from rectangular coordinate form to polar coordinate form. Computing in rectangular coordinates form, amplitude detector 319 may be implemented using multipliers and a fixed-point square-root algorithm, the absolute value of x=x.sub.I+jx.sub.Q being {square root over (x.sub.I.sup.2+x.sub.Q.sup.2)}.

(21) One way to calculate the square root takes advantage that a positive fixed-point number n may be represented in the form n=2.sup.m(1+) where m is an integer and a is a fixed-point number satisfying 0<1. One can approximate log.sub.2 n by the function q log 2(n)=m+. The logarithm (base 2) of the square-root of n may then be expressed as

(22) $\frac{1}{2}\log 2\left(n\right)=\frac{1}{2}m+).$
The square root can be approximated by

(23) $2^{m/2}\left(1+\frac{1}{2}\right)$
for an even m, or

(24) $2^{\left(m-l\right)/2}1.414\left(1+\frac{1}{2}\right),$
for an odd m. The digital circuit for the q log 2( ) function can be very simply implemented. Alternately, a polynomial fit may be used to calculate {square root over (1+)} (e.g. 1.0013+0.48210.0702.sup.2). The square root for n using the polynomial fit is 2.sup.m/2 (1.0013+0.48210.0702.sup.2) for an even m, or 2.sup.(m1)/21.414(1.0013+0.48210.0702.sup.2), for an odd m.

(25) Returning to arithmetic-logic circuit 300 of FIG. 3, delay elements 314 and 316, multiplier 305, and non-linear gain element 311 together implements the non-linear gain term x.sub.k1G(|x.sub.k1|; v.sub.1). Non-linear gain element 311 may be implemented by a combination of look-up table (LUT) together with one-dimensional linear interpolation between adjacent table elements. Under this approach, the LUT circuit looks up a predetermined number of the most-significant-bits of its input value, and then adds to it the value of the remaining bits, which is obtained by linear interpolation. Thus, such a LUT circuit provides the piece-wise linear approximation of smooth non-linear functions.

(26) As shown in FIG. 3, multiplier 318 and polynomial element 317 implements polynomial term x.sub.kP.sub.3(|x.sub.k|). Delay elements 313, 314, 315 and 316, multiplier 307, and polynomial element 309 implements polynomial term x.sub.k2P.sub.4(|x.sub.k2|). Delay elements 315 and 316, multiplier 305, adder 308 and polynomial elements 310 and 312 implements polynomial polynomial term x.sub.k1(P.sub.1(|x.sub.k|)+P.sub.2(|x.sub.k2|)). Polynomial elements 309, 310, 312, 317 may each implement, for example, a 4th-order polynomial function such as c1r+c2r2+c3r4. Each polynomial element may be implemented, for example, by adders, multipliers or LUT circuits or any combination of some or all of these elements.

(27) As mentioned above, as shown in FIG. 1, the adaptive control of DPD processor 106 is based on RF feedback signal 115, which is obtained from 30-dB coupler 109 at the output terminal of power amplifier 108. (RF feedback signal 115 may be attenuated before being provided to signal analyzer integrated circuit 102. RF feedback signal 115 is the output signal of power amplifier 108 together with some possible interference. In a multiple-input multiple-out (MIMO) system, for example, such interference may arise from multi-antenna coupling. The interference at the output terminal of coupler 109 is an antenna interference attenuated by the isolation ratio (>30 dB) of coupler 109. Typically, the signal-to-interference ratio in the feedback path of RF feedback signal 115 is better than 40 dB.

(28) RF feedback signal 115 is converted to analog in-phase and quadrature signals by quadrature down-converter 110 in signal analyzer integrated circuit 102. Local oscillator (LO) signal 114 for down-converter 110 may be provided by a PLL-based tunable frequency synthesizer that has a frequency resolution of 0.1 MHz. The down-converter synthesizer is adjusted to approximately the center frequency of baseband RF signal from baseband data source 103. The output I/Q signals of quadrature down-converter 110 are converted to digital signals by ADCs 111, which may be conventional pipelined ADCs with 12-bit resolution and a 10.5-bit ENOB. The clock rate of ADCs 111 may be variable and adjusted to roughly 4.5 times the signal bandwidth, e.g. 80100 MS/s for 20-MHz LTE.

(29) Digital signal analyzer 112 may use fast Fourier transform (FFT) and the Welch's algorithm to measure the power spectrum density (PSD) of RF feedback signal 115. Within signal analyzer integrated circuit 102, digital circuit block 112 may include a circuit for computing a 256-point FFT. From a PSD analysis, signal analyzer integrated circuit 102 obtains an estimate of the out-of-band emission power of RF feedback signal 115. Digital circuit block 112 may also include a micro-controller that runs a stochastic optimization algorithm (see, e.g., the disclosure of U.S. Pat. No. 8,136,081). Such an optimization step adjusts the control parameters of DPD processor 106 and minimizes out-of-band emission power. Serial Peripheral Interface (SPI) bus 113 exchanges information between signal analyzer integrated circuit 102 and the transceiver integrated circuit.

(30) In one embodiment, coefficient c.sub.0 in Equation (2) above is not adjusted from minimizing the out-of-band emission power of RF feedback signal 115. Coefficient c.sub.0 controls a linear filtering effect that can compensate for non-flat gain across the bandwidth of the input RF signal.

(31) The LUT circuit in non-linear gain element 311 may be configured as a piece-wise linear approximation of the polynomial G(r)=.sub.n=1.sup.10a.sub.nr.sup.n, with a.sub.n being complex-valued coefficients. For many power amplifiers, function G(r) may be further simplified to:
G(r)=a.sub.1r+a.sub.2r.sup.2+a.sub.4r.sup.4+a.sub.6r.sup.6+a.sub.8r.sup.8
Such a polynomial representation reduces the degree of freedom of control parameters for DPD adaptation. This adaptation method is based on finding the set of parameter values that minimize the out-of-band emission power resulting from the non-linear distortion in RF feedback signal 115. Out-of-band emission is insensitive to I/Q imbalance in quadrature down-converter 110 and other sources of interferences, such as the interference due to multi-antenna coupling in a MIMO system.

(32) FIG. 4 is a block diagram of system 400, according to a second embodiment of the present invention. As shown in FIG. 4, in addition to RF feedback signal 115 (RFFB), signal analyzer integrated circuit 402 receives power amplifier input signal 411 (RFIN). Complex baseband digital signals are obtained from RF feedback signal 115 and power amplifier input signal 411 using quadrature down-converters 412a and 412b. Quadrature down-converters 412a and 412b may be provided the same LO signal 114. The down-converted feedback signals are converted to digital domain in ADCs 111, ADCs 111 are shown in FIG. 4 as ADCs 413a and 413b. Signal analyzer integrated circuit 402 measures not only the power spectral density (PSD) of each input signal, but also the relative waveform distortion between RF feedback signal 115 and power amplifier input feedback signal 410. Using a signal analyzer that operates on an output signal of a power amplifier so as to control linearity of the power amplifier is taught, for example, in U.S. Pat. No. 8,145,150.

(33) Relative waveform distortion may be measured in signal analyzer integrated circuit 402 using a digital waveform-matching subsystem, such as waveform-matching circuit 500 illustrated by block diagram in FIG. 5. (Although waveform matching circuit 500 is described herein as a circuit, the operations carried out in waveform matching circuit 500 may also be implemented, entirely or in part, in software executable on a microprocessor). Waveform matching circuit 500 corrects for DC offset, I/Q imbalance, and linear distortion in both RF feedback signal 115 and power amplifier input feedback signal 410. As shown in FIG. 5, waveform matching circuit 500 provides DC offset corrections to RF feedback signal 115 and power amplifier feedback signal 410 in DC offset correction circuits 501a and 501b, respectively. The DC offset-corrected signals are then corrected for I/Q imbalance in I/Q imbalance correction circuits 502a and 502b, respectively. The following method may be used for correcting I/Q imbalances: (a) Detuning the LO frequency of a quadrature down-converter (e.g., down-converter 412a or 412b) from the center frequency of RF signals (e.g. RF feedback signal 115 or power amplifier input feedback signal 114) by an amount equal to or slightly higher than half of the RF signal bandwidth; (b) measuring the PSD that shows the mirror-leakage power due to I/Q imbalance; and (c) adjusting the I/Q imbalance parameters of waveform matching circuit (e.g., I/Q imbalance correction circuit 502a or 502b) to minimize the mirror-leakage power.

(34) FIG. 5 also shows complex gain and delay matching by finite impulse response (FIR) filter 503a and integer delay circuit 503b in the signal paths of RF feedback signal 115 and power amplifier input feedback signal 410, respectively. FIR filter 503a includes a complex-coefficient FIR filter that provides, not only delay matching, but also linear distortion correction. Complex gain and delay matching may be accomplished, for example, using the techniques disclosed in U.S. Pat. No. 8,295,394. Waveform matching circuit 500 provides matched complex signals (A.sub.k and B.sub.k), in which signal B.sub.k is the complex gain and delay matched output signal of FIR filter 503a, weighted by a correlation between the output signal of FIR filter 503a and the output signal A.sub.k of delay circuit 503b. Error signal A.sub.r B.sub.k is provided by summer 505. An optimum matching is achieved by minimizing mean square error detected at mean square error detector 507 of the error signal A.sub.kB.sub.k (i.e. the average power of |A.sub.kB.sub.k|.sup.2).

(35) From statistical samples of A.sub.k/B.sub.k, signal analyzer 414 measures the conditional expectations:
.sub.m=E{(A.sub.k/B.sub.k)|r.sub.m<|B.sub.k|<r.sub.m+r}, for r.sub.m=(m0.5)r,m=1,2, . . .(3)
where the selected step size r may be a fraction (e.g., 1/32) of the envelope peak. Using the calculated conditional expectations, the LUT circuit of non-linear gain element 311 in DPD processor 106 are programmed to contain:
G(mr)(4)
The stored values in the LUT circuits are monitored and updated from time to time. The memory kernel coefficients (except for c.sub.0) are controlled to minimize the out-of-band emission in RF feedback signal 115.

(36) According to one embodiment of the present invention, signal analyzer integrated circuit 102 may be implemented, for example, by the RFPAL product from Scintera Corporation, Santa Clara, Calif. in conjunction with a microcontroller (e.g., Intel 8051). Signal analyzer integrated circuit 102 carries out the following basic functions: (a) monitoring the average power and power spectrum of RF feedback signal 115 (RFFB) and power amplifier input signal 410 (RFIN); (b) waveform matching between the RFIN and RFFB signals; (c) monitoring the transmitter LO leakage that causes a spectral line on the power spectrum; (d) monitoring the transmitter I/Q imbalance from the mutual correlation and average-power imbalance between the I/Q components; and (e) monitoring the power amplifier status, such as bias voltages and ambient temperatures.

(37) FIG. 6 is a block diagram of system 600, in accordance with one embodiment of the present invention. In system 600, in addition to receiving RF feedback signal 115 and exchanging data and control signals generally over SRI bus 113, signal analyzer integrated circuit 602 also receives from transceiver circuit block 101 output data signal 618 of CFR processor 104, and local oscillator (LO) reference timing signal 614. Up- and down-converters in system 600, i.e., up-converter in digital-to-RF up-converter 107 and quadrature down-converter 110, may be controlled by common LO reference timing signal 614. LO reference timing signal 614 may be obtained, for example, from a crystal oscillator from the up-converter synthesizer in digital-to-RF up-converter 107. Sharing reference timing signal 614 between digital-to-RF up-converter 107 and quadrature down-converter 110 allows phase synchronization between the frequency synthesizers. Quadrature down-converter 110 has a synthesizer that is normally adjusted to the nominal center frequency of RF feedback signal 115 plus a small frequency offset. The frequency offset results from a coarser frequency resolution in the synthesizer of quadrature down-converter 110, relative to the frequency resolution in the synthesizer the up-converter in digital-to-RF up-converter 107. Output data signal 618 of CFR processor 104 also shares a timing signal with ADCs 111.

(38) Digital signal analyzer 612 of FIG. 6 receives both digital data signal 618, which is the crest factor-reduced complex baseband input signal from data source 103, and digital signal 117, which is the digital representation from ADCs 111 of down-converted RF feedback signal 115. In addition to PSD measurement, digital signal analyzer 612 provides waveform matching between digital data signal 618 and digital signal 117. FIG. 7 shows waveform matching circuit 700, which performs DC offset correction on digital signal 117 (block 701), I/Q imbalance correction on both digital data signal 618 and digital signal 117 (blocks 702a and 702b, respectively), frequency offset correction, linear distortion correction, delay matching, and complex gain matching (FIR filter block 703 and frequency correction block 704), in accordance with one embodiment of the present invention. (Although waveform matching circuit 700 is described herein as a circuit, the functions of waveform matching circuit 700 may also be performed, entirely or in part, by software executable in a microprocessor or a digital signal processor.) Waveform matching circuit 700 generates matched signals D.sub.k and B.sub.k, which are respectively the output signal of frequency correction block 704 and the output signal of I/Q compensation correction block 702a, weighted by a correlation between signal DK and the output signal of I/A imbalance correction block 704. A difference between the two matched signals is taken at summer 505. Optimum matching is achieved by minimizing mean square error (i.e., the average power of |D.sub.kB.sub.k|.sup.2).

(39) From statistical samples of D.sub.k/B.sub.k, signal analyzer 612 measures the conditioned expectations:
.sub.m=E{(D.sub.k/B.sub.k)|r.sub.m<|B.sub.k|<r.sub.m+r}, for r.sub.m=(m0.5)r,m=1,2 . . .(5)
The table data in the LUT circuits for non-linear gain model 311 of DPD processor 106 are updated to
G.sup.(new)(mr)=.sub.m.Math.G.sup.(old)(mr)(6)

(40) The memory kernel coefficients (except for c.sub.0) in DPD processor 106 are controlled to minimize the out-of-band emission of the feedback signal.

(41) One advantage of the adaptation methods of the present invention allows the sampling rate of RF feedback signal 115 to be reduced to only 34 times the signal bandwidth (e.g. 61.44 MS/s for 20-MHz LTE). Therefore, transceiver integrated circuit 101 may send digital data signal 618 to digital signal analyzer 612, instead of the double-sampled signal (i.e., the input signal to DPD processor 106). In contrast, conventional DPD models for the power amplifiers must use the double-sampled signal for parameter estimation. Because the methods can take advantage of a lower ADC rate, signal analyzer 612 may be substantially simpler than conventional signal analyzers for DPD applications.

(42) FIG. 8 shows system 800, which CFR processor 104, DPD processor 106, and signal analyzer 612, quadrature down-converter 110 are integrated into a single integrated circuit, in accordance with one embodiment of the present invention. As shown in FIG. 8, Digital-to-RF up-converter 107 may be integrated into a transceiver integrated circuit (e.g., transceiver integrated circuit 802), which may be manufactured using a prevailing CMOS circuit manufacturing technology (e.g. 65-nm or 45-nm CMOS in year 2013). At the same time, the digital circuits, such as CFR processor 104, DPD processor 106, and signal analyzer 612, quadrature down-converter 110, may be manufactured using an older CMOS process (e.g. 0.13-m CMOS) to take advantage the trade-off between development cost and power consumption, as CFR and DPD algorithms applicable to the present invention are low complexity and high performance.

(43) FIG. 9 is a block diagram of system 900, including enhanced ADC 911, in accordance with one embodiment of the present invention. Enhanced ADC 911 provides a higher analog-to-digital conversion rate and accuracy at a lower power than conventional pipelined ADC. As shown in FIG. 9, system 900 is similar to system 600 of FIG. 6, with enhanced ADC 911 receiving digital signals 913 from digital signal analyzer 912. Digital signals 913 includes digital signals D.sub.k,I and D.sub.k,Q, which are used to enhanced conversion rate and accuracy in analog-to-digital conversion for the down-converted quadrature signals derived from RF feedback signal 115.

(44) FIG. 10 is a block diagram showing enhanced ADCs 1011a and 1011b for the down-converted in-phase and quadrature analog signals derived from RF feedback signal 115, respectively. The down-converted in-phase and quadrature analog signals derived from RF feedback signal 115 are shown in FIG. 10 as analog signals 1014a and 1014b. Enhanced ADCs 1011a and 1011b each include an ADC enhancer circuit, shown in FIG. 10 as ADC enhancer circuits 1011a and 1011b, respectively. ADC enhancer circuits 1011a and 101b receive signals D.sub.m and D.sub.k,Q and analog signals 1014a and 1014b to provide output signals 1015a and 1015b to conventional ADCs 111a and 111b, respectively. (Conventional ADC 111a and 111b may be implemented using the same circuits in ADC 111 of FIGS. 1, 4 and 6). Typically, quadrature down-converter 110 provides current-mode output for analog signals 1014a and 1014b. ADC enhancer circuits 1012a and 1012b use a current-steering digital-to-analog converter (DAC) technique. From input analog current signal V(t) (i.e., analog signals 1014a or 1014b) and digital signal D.sub.k (i.e., D.sub.k,I or D.sub.k,Q), ADC enhancer circuit 1012a or 1012b generates an analog signal V(t)D(t) through the current sum. In FIG. 10, current D(t)=.sub.kD.sub.ku(tkT) is the output current of DAC 1016a or 1016b, where u(t) is a rectangular pulse with one clock-period duration. The V(t)D(t) current is converted to analog voltage by load impedance 1017a or 1017b, followed by amplification in voltage amplifier 1018a or 1018b. Signals in ADC enhancer circuits 1012a and 1012b are preferably implemented as differential signals.

(45) A front-end circuit in ADC 111a or 111b is a switching capacitor track-and-hold (T/H) circuit driven clock signal CLK. The clock rate (sub-ADC sampling rate) may be a multiple of the data rate of digital signal D.sub.k. To simplify the following discussion, the sub-ADC sampling rate is provided to be the same as the data rate of digital signal D.sub.k. ADC 111a and 111b provides digital signal S.sub.k,I and S.sub.k,Q. S.sub.k (i.e., S.sub.k,I or S.sub.k,Q) is given by:
S.sub.k+=A.Math.[V(t.sub.k)D.sub.k]+q.sub.k(7)
where is an integer delay, A is the gain of ADC enhancer circuit 1012a or 1012b, is a DC offset, and q.sub.k is a residual error dominated by the quantization error of ADC 111a or 111. The (A,) parameters of ADC enhancer circuits 1012a or 1012 may be accurately identified from a calibration by turning off analog input current V(t).

(46) The complex-valued digital signal D.sub.I+jD.sub.Q, is generated from waveform-transform circuit 1100 shown in FIG. 11. Waveform transform circuit 1100 receives a copy of digital data signal 618 from CFR processor 104. Digital data signal 618 may be represented as the value C.sub.I+jC.sub.Q. Waveform-transform circuit 1100 first performs an I/Q imbalance correction (block 1101), FIR filtering (block 1102, for delay matching and linear distortion correction), complex gain adjustment (mixer 1103), frequency offset correction (mixer 1104), and DC offset correction (summer 1105). To provide frequency offset correction, the gain-adjusted complex-valued signal is multiplied with e.sup.j2(f)k. For nearly-zero-IF down-conversion with a small frequency offset, the data rate of the D.sub.I+jD.sub.Q equals to the data rate of digital data signal C.sub.I+jC.sub.Q, which is 34 times the original RF bandwidth (e.g. 61.44 MS/s for 20-MHz LTE).

(47) Analog amplifiers in ADC enhancer circuits 1011a and 1011b may be provided by open-loop amplifiers without precise gain control and may be designed to have selectable low, medium, and high-gain modes. For example, the enhancer gain is 0, 15, and 30 dB. The enhanced ADCs start operation from the following procedure: (a) switching the ADC enhancer circuits 1011a or 1011b to a low-gain mode; (b) Using a stochastic optimization algorithm (e.g. any suitable one of the algorithms disclosed in U.S. Pat. No. 8,136,081) to adjust the control parameters of the waveform-transform circuit 1100 and to minimize the average power of output signal S.sub.I+jS.sub.Q of ADC 111a or 111b; (c) switching ADC enhancer circuits 1011a and 1011b to a medium-gain mode; (d) redoing waveform matching (i.e. adjusting the control parameters of the waveform-transform circuit 1100) to minimize the average power of S.sub.I+jS.sub.Q; (e) reconstruct the signal V.sub.I+jV.sub.Q as:
V.sub.k,I=D.sub.k,I.sub.I+S.sub.k+,I/A.sub.I and V.sub.k,Q=D.sub.k,Q.sub.Q+S.sub.k+,Q/A.sub.Q(8)

(48) and; (f) switching ADC enhancer circuits 1011a and 1011b to a high-gain mode, and repeating steps (d) and (e) periodically.

(49) The precision or ENOB enhancement of the reconstructed signal given by equation (8) is approximately (20 log.sub.10A)/6 bits, with (20 log.sub.10A the enhancer gain in dB. Enhanced ADCs (e.g., enhanced ADCs 911) directly generate two complex-valued digital signals expressed as
{tilde over (Y)}.sub.k+=(D.sub.k,I+jD.sub.k,Q)(.sub.I+j.sub.Q)(9)
{tilde over (B)}.sub.k={tilde over (Y)}.sub.k(S.sub.k,I/A.sub.I+jS.sub.k,Q/A.sub.Q)(10)
where {tilde over (Y)}.sub.k is a delayed copy of the frequency-offset corrected output in FIG. 11 (e.g., output value of integer delay block 1106), and {tilde over (B)}.sub.k accurately digitizes the quadrature down-converter output. {tilde over (Y)}.sub.k and {tilde over (B)}.sub.k are a pair of matched signals. After removing the 1/Q imbalance and DC offsets of quadrature down-converter 110, corrected signals Y.sub.k and B.sub.k are obtained. From statistical samples of Y.sub.k/B.sub.k, the signal analyzer can measure the conditioned expectations
.sub.m=E{(Y.sub.k/B.sub.k)|r.sub.m<|B.sub.k|<r.sub.m+r}, for r.sub.m=(m0.5)r,m=1,2, . . .(11)
which may be used to update the values in the LUT circuits in DPD processor 106 to compensate for the memory-less non-linearity in power amplifier 108. As for the non-linear memory effects, DPD processor 106 minimizes the out-of-band emission of RF feedback signal 115.

(50) As discussed above, initially, ADC enhancer circuits 1011a and 1011 bare at a low-gain mode. In this initial stage, digital pre-distortion techniques can only linearize power amplifier 108 to a point with relatively poor linearity, due to the coarse precision of ADCs 111a and 111b. In the next step, ADC enhancer circuits 1011a and 1011b are switched to a medium-gain mode, and the enhanced precision of ADC 111a and 111b improves the pre-distortion. Then, the enhancer circuits 1011a and 1011b are switched to a high-gain mode and the output signal of power amplifier 108 can achieve further a higher linearity. The maximum-allowed ADC enhancer circuit gain is limited by residual non-linear distortions that cannot be removed by digital pre-distortion techniques. Lab experiments have shown that, for a large variety of power amplifiers, the DPD methods of the present invention allow for 30-dB or higher ADC enhancer circuit gain. Therefore, the ADC enhancer circuit of the present invention can provide ENOB enhancement of 5-bit or more.

(51) The ADC enhancer circuits of the present invention lower the requirement on ADCs. As a result, power efficient 6-bit ADCs may be selected with a 5.5-bit ENOB. For example, time-interleaved successive approximation ADCs or folding-flash ADCs may be used. Such ADCs may operate at a sampling rate of 1000 MS/s in 65-nm CMOS. Enhanced ADCs of the present invention may provide an ENOB of 10.5 bit or higher at significantly lower power than conventional pipelined ADCs.

(52) The down-converted RF feedback signal from power amplifier 108 includes a large known signal component. The present invention provides a mixed-signal processing method (the ADC enhancer circuit) that can separate the known signal from the residual distortion and noise. The analog-to-digital (A/D) conversion of the distortion plus noise is much easier than direct A/D conversion of RF feedback signal 115. The undesired distortion may be suppressed by digital pre-distortion techniques. The present invention also provides a novel DPD method that performs well in conjunction with the ADC enhancement technique.

(53) FIG. 12 is a block diagram showing two-stage ADC enhancer circuit 1200, in accordance with one embodiment of the present invention. ADC enhancer circuit 1200 may be used in each of I and Q channels. First-stage 1201 of ADC enhancer circuit 1200 applies the current-steering technique discussed above in conjunction with FIG. 10. Cascaded T/H circuits 1214 and 1215 driven by complementary clock signals serve as a master-slave sample-and-hold block that holds analog samples for each clock period. Second stage 1202 of ADC enhancer circuit 1200 uses a charge-redistribution technique to acquire each analog voltage sample, which is then subtracted from a voltage from a voltage output DAC 1216. The difference signal is amplified in amplifier 1218 and then provided to an ADC, such as conventional ADC 111 discussed above. Thus, with analog input signal V(t) and digital input signal D.sub.k, an enhanced ADC of the present invention incorporating ADC enhancer circuit 1200 provides:
S.sub.k+=A.sub.2A.sub.1[V(t.sub.k)D.sub.k.sup.(1)]A.sub.2D.sub.k+1.sup.(2)+A.sub.2A.sub.1+q.sub.k(12)
where D.sub.k.sup.(1) and D.sub.k.sup.(2) (i.e., 1221 and 1222) are the input signals from digital processing circuit 1220 to first and second stages 1201 and 1202, respectively; and A.sub.1 and A.sub.2 are the gains of amplifiers 1213 and 1218. The parameters (A.sub.1, A.sub.2, ) can be accurately identified 30 from calibrations. In one embodiment, signal D.sub.k is provided as:
D.sub.k.sup.(1)=A.sub.1.Math.round(D.sub.k/A.sub.1),D.sub.k.sup.(2)=A.sub.1(D.sub.k1D.sub.k1.sup.(1))(13)
such that:
S.sub.k+=A.sub.2A.sub.1[V(t.sub.k)D.sub.k+]+q.sub.k(8)
which is identical to the value of S.sub.k+r obtained from equation (7), when the ADC enhancer circuit gain A=A.sub.1A.sub.2.

(54) The enhanced ADCs of the present invention can operate at a sampling rate of 1000 MS/s or higher. Thus, signal analyzer 902 can support non-zero intermediate-frequency down-conversion for RF signals with an original bandwidth up to 100 MHz. In one embodiment, only one ADC associated with either the in-phase or quadrature component is used for signal analysis. A double-rate or quadruple-rate up-sampler may preferably be inserted, for example, between complex-gain multiplier 1103 and frequency-offset multiplier 1104 of FIG. 11, as the intermediate frequency is typically 2.5 times the bandwidth of the original RF signal. If a quadruple-rate up-sampler is provided, the ADC clock rate is also preferably the quadruple rate.

(55) The above detailed description is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible.

(56) The present invention is set forth in the accompanying claims.