Common-mode feedback circuit, corresponding signal processing circuit and method

Abstract

A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.

Claims

1. A common-mode feedback circuit comprising: a transconductor input stage having differential input terminals; a frequency-compensated gain stage coupled to said transconductor input stage and having differential output terminals; a common-mode feedback loop including a comparator configured to produce a feedback error signal for said transconductor input stage by comparing a common-mode sensing signal indicative of a common-mode voltage level sensed at said differential output terminals with a reference; said common-mode feedback loop including a converter configured to convert the common-mode voltage level sensed at said differential output terminals into a current signal coupled to said comparator, said converter comprising a pair of common-mode detector resistors coupled to said differential output terminals, and said comparator comprising a current amplifier.

2. The common-mode feedback circuit of claim 1, further comprising a cascode current mirror with a first portion coupled with said comparator and a second portion coupled with said transconductor input stage.

3. The common-mode feedback circuit of claim 1, further comprising a multi-output current mirror having respective gains towards said transconductor input stage and said comparator.

4. The common-mode feedback circuit of claim 1, wherein said transconductor input stage comprises output nodes coupled to said frequency-compensated gain stage and the feedback error signal of said common-mode feedback loop is injected into one of said output nodes of said transconductor input stage, and a tail current generator of said transconductor input stage.

5. The common-mode feedback circuit of claim 1, wherein said comparator comprises a transistor pair sensitive to said reference and said current signal from said converter.

6. The common-mode feedback circuit of claim 5, wherein said common-mode feedback loop comprises at least one further transistor coupled with a transistor of said transistor pair to generate said feedback error signal for said transconductor input stage.

7. The common-mode feedback circuit of claim 6, further comprising at least one of: a start-up current generator coupled with a current generator circuit at said comparator; a beta helper coupled to a differential transistor pair in said comparator; and at least one of a first error-compensating resistor and a second self-bias resistor coupled with an input terminal of said comparator for said reference.

8. An integrated circuit comprising: a transconductor input stage; a frequency-compensated gain stage coupled to said transconductor input stage and having differential output terminals; and a common-mode feedback loop including a comparator configured to produce a feedback error signal for said transconductor input stage by comparing a common-mode sensing signal indicative of a common-mode voltage level sensed at said differential output terminals with a reference; said common-mode feedback loop including a converter configured to convert a common-mode voltage sensing signal into a current signal coupled to said comparator, said converter comprising a pair of common-mode detector resistors coupled to said differential output terminals, and said comparator comprising a current amplifier.

9. The integrated circuit of claim 8, further comprising a cascode current mirror with a first portion coupled with said comparator and a second portion coupled with said transconductor input stage.

10. The integrated circuit of claim 8, further comprising a multi-output current mirror having respective gains towards said transconductor input stage and said comparator.

11. A method of providing feedback in a common-mode feedback circuit comprising a transconductor input stage having differential input terminals, a frequency-compensated gain stage coupled to said transconductor input stage and having differential output terminals, a converter comprising a pair of common-mode detector resistors coupled to said differential output terminals, and a comparator comprising a current amplifier, the method comprising: producing a common-mode feedback error signal by a comparison of a common-mode sensing signal indicative of a common-mode voltage at said differential output terminals with a reference; and converting said common-mode sensing signal into a current signal for said comparison.

12. The method of claim 11, further comprising a cascode current mirror with a first portion coupled with said comparator and a second portion coupled with said transconductor input stage.

13. The method of claim 11, further comprising a multi-output current mirror having respective gains towards said transconductor input stage and said comparator.

14. An integrated circuit comprising: a transconductor input stage having differential input terminals; a frequency-compensated gain stage coupled to said transconductor input stage and having differential output terminals; a common-mode feedback loop including a comparator configured to produce a feedback error signal for said transconductor input stage; and a multi-output current mirror comprising a first portion coupled with said comparator and a second portion coupled with said transconductor input stage; said common-mode feedback loop including a converter configured to convert a common-mode voltage level sensed at said differential output terminals into a current signal coupled to said comparator.

15. The integrated circuit of claim 14, wherein the multi-output current mirror has respective gains towards said transconductor input stage and said comparator.

16. The integrated circuit of claim 14, wherein said transconductor input stage comprises output nodes coupled to said frequency-compensated gain stage and the feedback error signal of said common-mode feedback loop is injected into one of said output nodes of said transconductor input stage, and a tail current generator of said transconductor input stage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, purely by way of non-limiting example, with reference to the annexed figures, wherein:

(2) FIG. 1 is a basic diagram of a prior art common-mode feedback circuit;

(3) FIG. 2 is exemplary of a possible implementation of the basic diagram of FIG. 1;

(4) FIG. 3 is a circuit diagram exemplary of embodiments of the invention;

(5) FIG. 4 is a generalized circuit diagram exemplary of embodiments of the invention;

(6) FIGS. 5 to 7 are further circuit diagrams exemplary of embodiments of the invention; and

(7) FIGS. 8 to 11 are partial circuit diagrams exemplary of features adapted to be included in embodiments of the invention.

DETAILED DESCRIPTION

(8) In the ensuing description various specific details are illustrated, aimed at providing an in-depth understanding of various examples of embodiments of the invention. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that the various aspects of the embodiments will not be obscured.

(9) Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relationship to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in various points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(10) The foregoing applies, by way of non-limiting example, to the features shown in FIGS. 8 to 11, while shown as possibly applied to the circuit topology of FIG. 3, these features can be applied to any of the other circuit topologies exemplified herein.

(11) The references used herein are provided merely for convenience and hence do not define the sphere of protection or the scope of the embodiments. In that respect it will be appreciated that identical or similar entities will be indicated by the same references throughout the figures, without repeating a corresponding description for each figure.

(12) FIG. 1 is a basic diagram of a common-mode feedback (CMFB) circuit as described, for example, in E. Snchez-Sinencio and J. Silva-Martnez, Design of continuous-time filters from 0.1 Hz to 2.0 GHz: Tutorial notes, in 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004).

(13) In the diagram, V.sub.in.sup.+ and V.sub.in.sup. denote the (differential, i.e., positive and negative) inputs, while V.sub.out.sup.+ and V.sub.out.sup. denote the (differential) outputs. A load, not visible in the figures, may be connected to the output nodes V.sub.out.sup.+ and V.sub.out.sup..

(14) The output common-mode voltage level V.sub.CM is sensed through a common-mode detector CMD and compared with a reference voltage, V.sub.REF, e.g., in an error amplifier EA. The resulting error signal from the error amplifier EA is then fed to the biasing circuit I.sub.BIAS of the opamp in such a way as to implement a negative feedback.

(15) The CMFB loop may be designed to ensure frequency compensation and circuit stability. This may increase the complexity of the overall design, its power consumption, and the amount of silicon area used. The frequency response of the (main) differential path may also be degraded in conventional CMFB schemes.

(16) For instance, a possible implementation of the circuit layout of FIG. 1 as illustrated in FIG. 2 may include a pair of resistors R1, R2 as an exemplary way of performing common-mode voltage detection (CMD). The diagram of FIG. 2 is exemplary of a wide bandwidth opamp, relying on a very simple topology in order to limit the number of frequency poles.

(17) In addition to entities already introduced in connection with FIG. 1, the diagram of FIG. 2 shows a differential transconductor stage 10 with a high output impedance including a pair of (e.g., bipolar) transistors Q.sub.1, Q.sub.2 driven by the input voltage terminals V.sub.in.sup.+ and V.sub.in.sup.. The differential transconductor stage 10 is coupled with a current mirror 12 including four transistors (e.g. MOSFETs) M.sub.1, M.sub.2, M.sub.3, M.sub.4.

(18) The outputs A, A from the differential transconductor stage 10 are applied to a high output impedance (e.g., non-inverting) gain stage 14 including two (e.g., bipolar) transistors Q.sub.3, Q.sub.4 in emitter-follower configuration.

(19) References V.sub.CC and V.sub.EE denote voltage levels providing power feed to the circuit where I.sub.T denotes the tail current generator of the differential transconductor stage 10, while I.sub.3 and I.sub.4 denote the current intensities through the transistors Q.sub.3 and Q.sub.4.

(20) In the possible implementation exemplified in FIG. 2, the frequency response of the differential gain may include two main contributions:

(21) a dominant pole at the high-impedance node (A, A) as schematically represented by capacitances C.sub.C1, C.sub.C2 coupled to the bases of transistors Q.sub.3 and Q.sub.4,

(22) a secondary pole at the capacitive load (B, B) as schematically represented by capacitances C.sub.L1, C.sub.L2 coupled to the output voltage terminals V.sub.out.sup.+ and V.sub.out.

(23) Capacitors C.sub.L1, C.sub.L2 may negatively affect compensation since the phase margin becomes increasingly smaller as the values of these capacitances increases.

(24) The frequency response may also include additional high-frequency poles which may degrade the CMFB phase margin (PM) compared to the differential one. These additional high-frequency poles may include, for example, a pole at the output of the resistive common-mode detector (parasitic capacitance at the node C of FIG. 2), as well as possible further poles within the error amplifier EA (this may be particularly true for low common mode voltages involving pnp- or MOS-based error amplifier topologies).

(25) Compensation capacitors C.sub.C1-C.sub.C2 may provide sufficient PM to both the differential and CMFB loops. For a given minimum PM specification, the differential loop gain may be overcompensated (lower bandwidth, slower time response) to ensure the required PM to the CMFB loop.

(26) Therefore, a fast CMFB loop may help in avoiding limitations on the differential frequency response.

(27) E. Snchez-Sinencio and J. Silva-Martnez (previously cited) disclose a loop architecture adapted to provide a faster CMFB response, where the functions of common-mode detection (voltage averaging) and comparison with the reference are performed in reverse order compared to the arrangement of FIG. 1. However, this approach involves using linear error amplifiers, because a possibly large differential signal is fed to their inputs in addition to the common-mode voltage component. Linear error amplifiers may, in turn, increase the overall current consumption and/or silicon area occupation.

(28) U.S. Pat. No. 5,933,056 discloses a circuit aimed at improving the frequency response of the CMFB path by exploiting a short feedback path, which still suffers from the pole at the common-mode detector output.

(29) This may be related to the fact that this arrangement actually relies on a voltage comparison, rather than on a current-based approach. It was noted that current-mode circuits may attain improved frequency responses, because they typically entail low-impedance nodes, i.e., high-frequency poles, compared to standard voltage-based topologies.

(30) Using a current-mode approach may thus be helpful in implementing a fast CMFB loop, as exemplified, for example, in U.S. Pat. No. 6,362,682. In the circuit topology described therein, the feedback signal of the common-mode loop is the sum (average) of the currents flowing through a pair of resistors.

(31) In high-gain feedback loops, the feedback signal tends to zero at steady-state, so that, under such conditions, the voltage drop across resistors tends to zero as well, and the output common-mode voltage may correctly track the voltage level at the reference input (V.sub.REF). Implementations as exemplified, for example, in U.S. Pat. No. 6,362,682 may however suffer (e.g., under large-signal differential excitation) from a non-linear transistor behavior which may affect the accuracy of the output common-mode voltage control.

(32) FIGS. 3 to 11 are exemplary of embodiments which may overcome the drawbacks outlined in the foregoing.

(33) It will be appreciated that certain designations introduced in FIGS. 1 and 2 will be retained throughout FIGS. 3 to 11 without repeating a corresponding description. Again, a load (not visible in the figures) may be connected to the output nodes V.sub.out.sup.+ and V.sub.out.sup..

(34) In the exemplary layout of FIG. 3, an output from a common-mode converter including resistors R1 and R2 (e.g., the point C where the two resistors R1 and R2 are connected) is fed to a comparator including a pair of (e.g., bipolar) transistors Q.sub.A, Q.sub.B coupled with a cascode current mirror 12, 16 including transistors M.sub.1 through M.sub.8.

(35) More specifically, in the exemplary embodiment of FIG. 3, the two transistors Q.sub.A, Q.sub.B (e.g., n-p-n bipolar transistors) have their bases connected to each other, with the collector of transistor Q.sub.B shorted to its base. The output (point C) from the common-mode detector CMD is fed to the emitter of transistor Q.sub.A, while the reference voltage V.sub.REF is applied to the emitter of transistor Q.sub.B. The current intensities through the (emitter-collector) current paths of the transistors Q.sub.A, Q.sub.B (which correspond to the current intensities through the branches M.sub.5-M.sub.7 and M.sub.6-M.sub.8 of the cascode current mirror 12, 16) are denoted I.sub.A and I.sub.B.

(36) The cascode current mirror 12, 16 (MOSFETs M.sub.1 through M.sub.8) may thus produce a current-based feedback path from the comparator including the transistor pair Q.sub.A, Q.sub.B (i.e., from the connection point C of the two resistors R1, R2) to the differential input (transconductor) stage 10.

(37) In one or more embodiments as exemplified in FIGS. 3 to 11, the designation current-based refers primarily to the nature of the signal sensed at the opamp differential output (e.g., at point C, via resistors R1, R2) in view of comparison with the reference V.sub.REF (e.g., via the transistor pair Q.sub.A, Q.sub.B).

(38) That is, in one or more embodiments as exemplified herein the common-mode feedback loop may include a converter (e.g., resistors R1, R2) for converting the common-mode voltage level V.sub.CM sensed at the differential output terminals V.sub.out.sup.+, V.sub.out into a current signal fed to the comparator including, e.g., Q.sub.A, Q.sub.B.

(39) In one or more embodiments as exemplified herein, the converter in question may thus include a pair of resistors R1, R2 each one interposed between a respective one of the differential output terminals (e.g., V.sub.out.sup.+ for resistor R1 and V.sub.out for resistor R2) of the differential output terminals and the comparator Q.sub.A, Q.sub.B.

(40) In one or more embodiments as exemplified herein, the converter may include the common point C of the resistors R1, R2 coupled with the emitter of Q.sub.A. In one or more embodiments as exemplified herein, the voltage at node C may in fact be set by V.sub.REF.

(41) In the exemplary embodiment of FIG. 3 the feedback connection includes:

(42) a first line 18a from the gates of transistors M.sub.5 and M.sub.6 (with the drain of M.sub.5 shorted to its gate) to the gates of transistors M.sub.1 and M.sub.2; and

(43) a second line 18b from the gates of transistors M.sub.7 and M.sub.8 (with the drain of M.sub.7 shorted to its gate) to the gates of transistors M.sub.3 and M.sub.4.

(44) In one or more embodiments, by way of schematic explanation, the cascode current mirror including transistors M.sub.1 through M.sub.8 may be regarded as including:

(45) a portion M.sub.5-M.sub.8 of the cascode current mirror which is controlled by the comparator Q.sub.A, Q.sub.B so as to produce a feedback loop error signal (e.g., lines 18a, 18b), and

(46) a portion M.sub.1-M.sub.4 of the cascode current mirror which controls the transconductor input stage 10 including, e.g., the transistor pair Q.sub.1, Q.sub.2 so that the feedback loop error signal is injected as a current feedback error signal into the transconductor input stage.

(47) In one or more embodiments, the components of the exemplary circuit of FIG. 3 may be designed according to the following relationships:
(I.sub.T/2I.sub.A)=(W/L).sub.1,2/(W/L).sub.5=(W/L).sub.3,4/(W/L).sub.7
I.sub.B/I.sub.A=A.sub.eB/A.sub.eA=(W/L).sub.6/(W/L).sub.5=(W/L).sub.8/(W/L).sub.7

(48) where A.sub.eA and A.sub.eB are the emitter areas of the bipolar transistors Q.sub.A and Q.sub.B, respectively, whereas (W/L).sub.i is the form factor of the i-th MOSFET M.sub.i, for i=1 . . . 8.

(49) According to the latter relationship above, the current densities through Q.sub.A and Q.sub.B may be made equal, which results in the base-emitter voltage V.sub.BEA for Q.sub.A being equal to the base-emitter voltage V.sub.BEB for Q.sub.B (base currents may be neglected here and in the following for simplicity).

(50) Therefore, the voltage V.sub.C at the node C may be expressed as:
V.sub.C=V.sub.REF+V.sub.BEBV.sub.BEA=V.sub.REF

(51) According to Kirchhoff's current law at node C:
I.sub.QA=I.sub.A[(V.sub.out.sup.+V.sub.C)]/R.sub.1,2[(V.sub.out.sup.V.sub.C)]/R.sub.1,2.

(52) where I.sub.QA is the current flowing through transistor Q.sub.A (emitter and collector currents are assumed to be roughly equal since base currents are neglected).

(53) By defining the output common-mode voltage V.sub.CM as (V.sub.out.sup.++V.sub.out.sup.)/2, combining the three last relationships yields:
I.sub.QA=I.sub.A2(V.sub.CMV.sub.REF)/R.sub.1,2.

(54) Because of the cascaded current mirror including transistors M1, M2, M3, M4, M5, and M7:
I.sub.M1=I.sub.M2=I.sub.QA(W/L).sub.1,2/(W/L).sub.5=I.sub.A(W/L).sub.1,2/(W/L).sub.5(2/R.sub.1,2).
[(W/L).sub.1,2/(W/L).sub.5](V.sub.CMV.sub.REF).

(55) where I.sub.M1 and I.sub.M2 are the currents flowing through transistor M.sub.1 and M.sub.2, respectively.

(56) According to Kirchhoff's current law at nodes A and A:
I.sub.T=I.sub.M1+I.sub.M2=2I.sub.A(W/L).sub.1,2/(W/L).sub.5(4/R.sub.1,2).
[(W/L).sub.1,2/(W/L).sub.5](V.sub.CMV.sub.REF).

(57) which, in view of the first relationship in the foregoing, finally gives:
V.sub.CM=V.sub.REF.

(58) This demonstrates that in one or more embodiments the output common-mode voltage V.sub.CM can successfully track the reference voltage V.sub.REF.

(59) By way of possible explanation, dynamically, if V.sub.CM increases, then the current injected into the node C through resistors R1 and R2 will increase as well, thus reducing I.sub.QA. This will in turn decrease I.sub.M1 and I.sub.M2 (i.e., the currents flowing through the transistor M.sub.1 and M.sub.2 in the current mirror 12 coupled with the differential transconductor stage 10) which will result in a reduction of the voltage level at nodes A and A, i.e., the outputs A, A from the differential transconductor stage 10 (high-impedance node). This will bring the opamp output voltage level down again, ultimately compensating the initial increase in V.sub.CM. In a similar (but opposite) manner the feedback loop exemplified herein will be able to compensate a negative variation of the opamp output common-mode voltage.

(60) One or more embodiments as exemplified herein may exhibit at least two advantages.

(61) In the first place, the CMFB loop is based on a current-mode approach with the current flowing through resistors R1 and R2 determining the actual feedback signal. Current-mode circuits exhibit low-impedance nodes, which entails high-frequency poles in the frequency response, and hence a fast CMFB loop.

(62) In the second place, the accuracy in the control of the common-mode voltage may be a function of the matching among transistors Q.sub.A and Q.sub.B (and their base-emitter voltages). These will not be exposed to large signal operating conditions, even if a large differential swing is delivered at the opamp output, which facilitates V.sub.BE matching, and hence reference tracking accuracy.

(63) In FIG. 4 the (differential transconductor) input stage 10 and the gain stage 14 are simply represented by blocks, thus highlighting the possibility of applying the principles underlying the embodiments exemplified in FIG. 2 to one or more embodiments where:

(64) the differential transconductor stage 10 is implemented as any known type of differential transconductor preserving high output impedance level, i.e., not necessarily based on the differential couple Q.sub.1Q.sub.2;

(65) the gain stage 12 including loop compensation is implemented as any known type of (e.g., non-inverting) gain stage preserving high input impedance level not necessarily based on emitter followers Q.sub.3Q.sub.4; and

(66) the cascode current mirror 12, 16 is implemented as any known type of multi-output current mirror 126, preserving high output impedance level, with current gain k towards the input branches and current gain h towards the Q.sub.B branch.

(67) In one or more embodiments as exemplified in FIG. 4 where (by adopting the same symbols introduced in the foregoing):
I.sub.T/2I.sub.A=k
I.sub.B/I.sub.A=A.sub.eB/A.sub.eA=h

(68) the opamp output common-mode voltage V.sub.C may track the reference voltage V.sub.REF, exactly as in the case exemplified in FIG. 3.

(69) In one or more embodiments, the current generator I.sub.T in FIG. 4 may be used to set the common-mode current for the input transconductor stage (I.sub.T=i.sub.O.sup.++i.sub.O.sup.), like the tail current of the input stage in FIG. 2.

(70) It will be appreciated that, throughout the embodiments exemplified herein, this current generator may also be referred to V.sub.CC (instead of V.sub.EE) as in the case of a folded cascade input differential transconductor.

(71) The circuit diagram of FIG. 5 is exemplary of one or more embodiments where the output of the multi-output current mirror, here designated 126, instead of being injected at nodes A-A is injected at the tail node of the input differential transconductor 10. This may be advantageous in those embodiments with a reduced supply headroom, with the CMFB loop functionality maintained.

(72) In one or more embodiments as exemplified in FIG. 5 where (by again adopting the same symbols introduced in the foregoing):
I.sub.T=kI.sub.A+2I.sub.1,2
I.sub.B/I.sub.A=A.sub.eB/A.sub.eA=h

(73) the opamp output common-mode voltage V.sub.C will again track the reference voltage V.sub.REF.

(74) The circuit diagram of FIG. 6 is exemplary of one or more embodiments where the gain stage 14 includes an inverting stage instead of a non-inverting stage.

(75) In such embodiments, the CMFB loop topology may be modified in order to take into account the resulting signal inversion, thus maintaining a negative loop gain.

(76) For instance, a current mirror 16 may include two branches associated with the transistors Q.sub.A and Q.sub.B through with current intensities i.sub.in and h.Math.i.sub.in, respectively, flow.

(77) The common-mode feedback path may include further transistors Q.sub.A1, Q.sub.A2 which mirror the transistor Q.sub.A and inject respective currents into the current paths I.sub.1 and I.sub.2 to the output nodes A-A of the differential transconductor 10.

(78) In one or more embodiments as exemplified in FIG. 6 where (with the same symbols introduced in the foregoing):
A.sub.eB/A.sub.eA=h
I.sub.B/I.sub.A=A.sub.eB/(A.sub.eA+2A.sub.eA1,2)
I.sub.1,2=I.sub.T/2+A.sub.eA1,2I.sub.A/(A.sub.eA+2A.sub.eA1,2)

(79) the opamp output common-mode voltage V.sub.C will track the reference voltage V.sub.REF.

(80) The circuit diagram of FIG. 7 is exemplary of one or more embodiments where, as in the case of FIG. 6, the gain stage 14 may again include an inverting stage instead of a non-inverting stage.

(81) In one or more embodiments as exemplified in FIG. 7, the common-mode feedback path includes at least one further transistor Q.sub.C which mirrors the transistor Q.sub.A and injects a respective feedback current signal (as in the case of those embodiments as exemplified FIG. 5) at the tail node of the input differential transconductor 10 rather than at its output nodes A-A.

(82) In one or more embodiments as exemplified in FIG. 7 where (with the same symbols introduced in the foregoing and with A.sub.eC denotes the emitter area of transistor Q.sub.C):
A.sub.eB/A.sub.eA=h
I.sub.B/I.sub.A=A.sub.eB/(A.sub.eA+A.sub.eC)
2I.sub.1,2=I.sub.T+A.sub.eCI.sub.A/(A.sub.eA+A.sub.eC)

(83) the opamp output common-mode voltage V.sub.C will track the reference voltage V.sub.REF.

(84) Those of skill in the art will appreciate that circuit topologies as exemplified in the figures may be implemented, wholly or partly, in a complementary configuration, e.g., by using p-n-p transistors in the place of n-p-n transistors and viceversa or pMOS transistors instead of nMOS and viceversa. Case-specific bias level compatibility requirements may dictate the choice of the configuration. Similarly, the inverting or non-inverting nature of the gain stage 14 may dictate, e.g., coupling of transistors Q.sub.A1, Q.sub.A2, Q.sub.C to Q.sub.B in the place of Q.sub.A as exemplified herein.

(85) FIGS. 8 to 11 are exemplary of certain features which may be included in any of the circuit topologies exemplified in the foregoing; that is, while shown as possibly applied to the circuit topology of FIG. 3, these features can be applied to any of the other circuit topologies exemplified herein. Also, while shown separately for the sake of simplicity, the features in FIGS. 8 to 11 may be combined with one another and thus co-exist in one or more embodiments.

(86) For instance, FIG. 8 is exemplary of the possibility of adding a (small) start-up current I.sub.SU between the current mirror 16 and V.sub.EE in order to improve turn-on performance of the circuit, e.g., like in a conventional proportional to absolute temperature (PTAT) generator, without appreciably affecting current consumption.

(87) FIG. 9 is exemplary of the possibility of adding a beta helper M.sub.H, I.sub.H to the transistors Q.sub.A-Q.sub.B to improve the matching of their base-emitter voltages.

(88) FIG. 10 is exemplary of the possibility of adding a resistor R3 in series with the input line to the error amplifier EA to which the reference voltage V.sub.REF is applied.

(89) This may improve the accuracy of the common-mode tracking, e.g. by allowing for a voltage drop across resistors R1 and R2 because of a non-zero residual current flowing through them. This may be a (very) small voltage drop, which has been neglected in the previous analysis for the sake of simplicity, and becomes lower for higher CMFB loop gain values.

(90) That source of error may be compensated by adding a resistor R3 such that:
R3=(A.sub.eA/A.sub.eB)(R.sub.1,2/2)

(91) Finally, FIG. 10 is exemplary of the possibility of replacing the current generator I.sub.B with a resistor R.sub.B, so that the reference input V.sub.REF may be allowed to float, e.g. in order that the node V.sub.REF may be self-biased at a default voltage level:
V.sub.REF(default)=(A.sub.eA/A.sub.eB)R.sub.BI.sub.A.

(92) with the opamp output common-mode voltage set accordingly.

(93) Of course, without prejudice to underlying principles of the embodiments, the details of construction and the embodiments may vary, even significantly, with respect to what is illustrated herein purely by way of non-limiting example, without thereby departing from the extent of protection. The extent of protection is defined by the annexed claims.