Signal processing device and signal processing method

Abstract

A signal processing device includes an interface, which includes a demodulation processing unit that executes demodulation processing, a processing unit that executes demux processing or the like, and a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the processing unit, that transmits data signals as two-bit parallel transmission.

Claims

1. A signal processing device comprising: a demodulation processing unit configured to execute demodulation processing; a demultiplex processing unit configured to execute demux processing; and a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the demultiplex processing unit, wherein a fixed length packet and a variable length packet are transmitted between the demodulation processing unit and the demultiplex processing unit using the sync signal line, the valid signal line, the clock signal line, and the data signal line based on a synchronous byte allocated in a header of the fixed length packet and the variable length packet, and wherein the variable length packet includes a Type Length Value (TLV) packet and the fixed length packet includes a Transport Stream (TS) packet of fixed length or a packet obtained by conversion of the variable length packet into a fixed length TS packet.

2. The signal processing device according to claim 1, wherein error information indicates whether or not an error occurs in the variable length packet, and wherein the error information is included in the header of the variable length packet.

3. The signal processing device according to claim 1, wherein error information is included in a region in which information regarding a packet type of the variable length packet is written.

4. The signal processing device according to claim 2, further comprising: an error signal line that transmits the error information.

5. The signal processing device according to claim 2, wherein the error information, included in the header of the variable length packet, is transmitted in error correction code units or variable length packet units.

6. The signal processing device according to claim 1, wherein the data signal line includes one to eight data signal lines, wherein the one to eight data signal lines are wired, and wherein serial transmission or parallel transmission, according to a number of wired data signal lines, is performed.

7. The signal processing device according to claim 1, wherein the data signal line has an arbitrary bit width of one to eight bits.

8. The signal processing device according to claim 1, wherein the data signal line transmits data for an eight-bit bit sequence in order starting from the synchronous byte in the header of the fixed length packet and the variable length packet.

9. The signal processing device according to claim 8, wherein in a case where the data transmitted for the eight-bit bit sequence, from the synchronous byte, is transmitted by two-bit parallel transmission, outputs of seventh bit, fifth bit, third bit, and first bit are allocated to a first signal line of the data signal line and outputs of sixth bit, fourth bit, second bit, and zeroth bit are allocated to a second signal line, of the data signal line, in an output order.

10. The signal processing device according to claim 8, wherein in a case where the data transmitted for the eight-bit bit sequence, from the synchronous byte, is transmitted by two-bit parallel transmission, outputs of first bit, third bit, fifth bit, and seventh bit are allocated to a first signal line of the data signal line and outputs of zeroth bit, second bit, fourth bit, and sixth bit are allocated to a second signal line of the data signal line, in an output order.

11. The signal processing device according to claim 8, wherein in a case where the data transmitted for the eight-bit bit sequence, from the synchronous byte, is transmitted by two-bit parallel transmission, outputs of third bit, second bit, first bit, and zeroth bit are allocated to a first signal line of the data signal line and outputs of seventh bit, sixth bit, fifth bit, and fourth bit are allocated to a second signal line of the data signal line, in an output order.

12. The signal processing device according to claim 8, wherein in a case where the data transmitted for the eight-bit bit sequence, from the synchronous byte, is transmitted by two-bit parallel transmission, outputs of zeroth bit, first bit, second bit, and third bit are allocated to a first signal line of the data signal line and outputs of fourth bit, fifth bit, sixth bit, and seventh bit are allocated to a second signal line of the data signal line, in an output order.

13. The signal processing device according to claim 1, wherein the sync signal line, the valid signal line, the clock signal line, and the data signal line use Low voltage differential signaling (LVDS) for an output interface.

14. The signal processing device according to claim 9, wherein in a case where the two-bit parallel transmission is performed, two data outputs of eight data outputs are allocated as output terminals.

15. The signal processing device according to claim 14, wherein the demodulation processing unit comprises a synthesis unit, and wherein in a system that receives a plurality of carrier waves, a plurality of data outputs, other than the two data outputs used for the two-bit parallel transmission is allocated to an input of the synthesis unit, that synthesizes the plurality of carrier waves, after being demodulated.

16. The signal processing device according to claim 14, wherein the demodulation processing unit comprises a synthesis unit, and wherein in a system that receives a plurality of carrier waves, six data outputs, other than the two data outputs used for the two-bit parallel transmission, of the eight data outputs are allocated to an input of the synthesis unit that synthesizes the plurality of carrier waves, after being demodulated.

17. The signal processing device according to claim 1, wherein the demodulation processing unit comprises a synthesis unit, and wherein in a system that receives a plurality of carrier waves, six data outputs, other than data outputs used for one-bit serial transmission, of eight data outputs are allocated to an input of the synthesis unit that synthesizes the plurality of carrier waves, after being demodulated.

18. A signal processing method comprising: executing, by a demodulation processing unit, demodulation processing; executing, by a demultiplexing processing unit, demultiplexing processing; and transmitting, by the demodulation processing unit to the demultiplexing processing unit, a fixed length packet and a variable length packet, via a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the demultiplexing processing unit, based on a synchronous byte allocated in a header of the fixed length packet and the variable length packet, wherein the variable length packet includes a Type Length Value (TLV) packet and the fixed length packet includes a Transport Stream (TS) packet of fixed length or a packet obtained by conversion of the variable length packet into a fixed length TS packet.

19. The signal processing device according to claim 1, wherein the synchronous byte is allocated in a head of the header, and wherein the synchronous byte is configured to constantly synchronize the fixed length packet and the variable length packet transmitted between the demodulation processing unit and demultiplexer processing unit.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram illustrating a TSMF structure which is a multiplex frame structure of a cable television.

(2) FIG. 2 is a diagram illustrating a configuration of an embodiment of a receiver to which the present technology is applied.

(3) FIG. 3 is a diagram illustrating a configuration of a system regarding digital cable television broadcasting.

(4) FIG. 4 is a diagram illustrating a configuration of a broadcast system in which an equivalent circuit of a substrate wiring is provided between a demodulation processing unit and a processing unit.

(5) FIGS. 5A, 5B, and 5C are diagrams illustrating examples of waveforms input to the processing unit.

(6) FIG. 6 is a diagram for explaining a signal line provided between the demodulation processing unit and the processing unit.

(7) FIG. 7 is a diagram in which an even-numbered bit and an odd-numbered bit are allocated to outputs of data in a case of two-bit parallel transmission.

(8) FIGS. 8A, 8B, 8C, and 8D are timing charts of data output from data lines in a case of the two-bit parallel transmission.

(9) FIG. 9 is a diagram illustrating a configuration that further includes a one-bit signal line for transmitting error information indicating occurrence of an error.

(10) FIG. 10 is a diagram illustrating a configuration using a Low voltage differential signaling (LVDS) signal for an output interface.

(11) FIG. 11 is a diagram illustrating an example indicating a system for dividing large-capacity digital data into a plurality of carrier waves by using the TSMF and performing frequency multiplex transmission.

(12) FIG. 12 is a diagram illustrating positions of three carrier waves with respect to the frequency.

(13) FIG. 13 is a diagram illustrating an example of a system, which is another form of FIG. 11, for performing frequency multiplex transmission by using four carrier waves.

(14) FIG. 14 is a diagram illustrating positions of four carrier waves with respect to the frequency.

(15) FIG. 15 is a schematic system diagram of a receiver that receives four multiple carrier waves by using a frequency multiplex transmission system according to the present technology.

MODE FOR CARRYING OUT THE INVENTION

(16) An embodiment to be described below is a preferable specific example of the present technology, and various technically preferable limitations are applied. However, in the following description, the scope of the present technology is not limited to the embodiment, unless there is a statement to particularly limit the present technology.

Reception System

(17) FIG. 1 is a diagram illustrating a TSMF structure which is a multiplex frame structure of a cable television. The TSMF structure includes 53 slots per frame, and 53 slots include a single header slot and 52 TS arrangement slots. A plurality of channels can be multiplexed by dividing 52 slots. A TSMF header includes information such as information regarding a position (slot) of each TS in synchronous data (0×47) and a frame structure “fixed length (188 bytes)”, a transmission multiplexing signal (Transmission and Multiplexing Configuration and Control: TMCC), or the like.

(18) FIG. 2 illustrates an example of a reception system that receives broadcast waves (carrier wave) of large-capacity/high-speed digital data such as 4K or 8K broadcasting transmitted by a broadcast satellite. The reception system includes an antenna 2, a receiver 1, and a display 6. The receiver 1 includes a tuner 3, a demodulation processing unit 4, and a processing unit 5. The demodulation processing unit 4 includes a demodulation unit 7 and an error correction unit 8. The processing unit 5 includes a demultiplexing unit (Demux) 9 and a decoder 10.

(19) The antenna 2 receives, for example, digital broadcast waves of a TLV system transmitted from a transmitter and supplies a reception signal obtained as a result to the receiver 1. The receiver 1 restores and processes the TLV from the reception signal from the antenna 2, extracts a video and sound, and outputs the extracted video and sound to the display 6.

(20) The error correction unit 8 corrects an error in a demodulation signal from the demodulation unit 7 and supplies a signal such as a TLV obtained as a result to the processing unit 5. The processing unit 5 can include, for example, a System-on-a-chip (SOC). The processing unit 5 executes demux processing, for example, processing for dividing moving image content into a video part, a sound part, a subtitle part, or the like.

(21) A sync signal, a valid signal, a data signal, and a clock signal that are output signals output from the demodulation processing unit 4 are supplied to the processing unit 5. The demultiplexing unit 9 of the processing unit 5 separates, for example, video data and sound data included in the data signal, and the decoder decodes the video data into a video signal or decodes the sound data into a sound signal so as to generate video and sound signals and output the signals to the display 6.

Application to Cable Retransmission

(22) FIG. 3 is a diagram illustrating a configuration of a system regarding digital cable television broadcasting. The system includes an antenna 11 that receives satellite broadcasting, a transmitter 12, and a receiver 1. The satellite broadcasting received by the antenna 11 is supplied to the transmitter (cable television station) 12. The transmitter 12 includes a satellite tuner 13 and a cable retransmission conversion unit 14. The transmitter 12 is a device on a side of a broadcast station that performs digital cable television broadcasting. The transmitter 12 converts broadcast waves of the satellite broadcasting received by the antenna 11 into broadcast waves of digital cable television broadcasting and transmits the converted broadcast wave to the side of the receiver through a transmission path 15 of a cable television.

(23) The receiver 1 has a configuration similar to that of the receiver illustrated in FIG. 2. (Therefore, similar reference numeral is applied, and description thereof is omitted). However, the tuner 3 of the receiver 1 illustrated in FIG. 3 receives and processes the digital broadcast waves transmitted through the transmission path 15.

(24) As described above, the satellite broadcasting is broadcasted as digital broadcast waves of the TLV system and received by the antenna 11. The transmitter 12 converts the digital broadcast waves of the TLV system into the broadcast wave of the digital cable television broadcasting, for example, a fixed length TS packet (divided TLV) and transmits the converted packet. This indicates a case where cable retransmission is performed by using an existing ISDB-C standard using the plurality of carrier waves.

Problems in Receiver

(25) FIG. 4 is a diagram in which an equivalent circuit of a substrate wiring 20 is provided between the demodulation processing unit 4 and the processing unit 5 in a case where the large-capacity/high-speed digital data is transmitted from the demodulation processing unit 4 to the processing unit 5 that executes demux processing and decoding processing at the subsequent stage. Depending on the quality of the material and the substrate of the substrate wiring 20, a parasitic element such as a parasitic resistance (R), a parasitic inductor (L), or a parasitic capacitor capacitance (C) is added to the wiring line. When a signal with a high frequency is transmitted to the substrate wiring 20, an output waveform of the large-capacity/high-speed digital data from the demodulation processing unit 4 is deformed due to an effect of the parasitic elements. Accordingly, a delay occurs, the waveform is deformed, and the processing unit 5 cannot execute processing.

(26) Furthermore, ringing occurs in the output waveform. The ringing generates spurious, the generated spurious affects around a tuner circuit or the like that selects a frequency of a carrier wave as a noise (EMI), and a quality of a signal is deteriorated. An ideal waveform in FIG. 5A is deformed as illustrated in FIG. 5B, and the ringing occurs in the output waveform as illustrated in FIG. 5C. In this way, the waveform input to the processing unit 5 is deformed by the effect of the parasitic element, and a voltage does not increase to a threshold at which high level/low level of the processing unit 5 is recognized. Furthermore, the ringing occurs in the waveform, and the noise is generated in the waveform.

About Signal Line

(27) Meanwhile, as a conventional receiver, for example, there has been a device that processes a fixed length TS packet. Even in such a device, in order to process a variable length TLV packet and in order to process a variable length TLV packet as a new device, processing described below is executed. Of course, the following processing is equally executed as the processing on the fixed length TS packet.

(28) FIG. 6 is a diagram for explaining signal lines provided between the demodulation processing unit 4 and the processing unit 5. The demodulation processing unit 4 can be an LSI that executes demodulation processing. Furthermore, the processing unit 5 can be an LSI that executes the demux processing. It is necessary for the demodulation processing unit 4 to output data so that the processing unit 5 at the subsequent stage can process the data (condition required by processing unit 5 is satisfied).

(29) According to the present technology, the demodulation processing unit 4 can supply the demodulated data while satisfying the condition required by the processing unit 5. In the following description, a case where the demodulation processing unit 4 and the processing unit 5 are formed as different LSIs will be described as an example.

(30) As illustrated in FIG. 6, four signal lines (a case of serial transmission) are disposed between the demodulation processing unit 4 and the processing unit 5. Of the four signal lines, one is a one-bit signal line that transmits a sync (SYNC) signal, one is a one-bit signal line that transmits a valid (VALID) signal, one is a one-bit signal line that transmits a clock (CLK) signal, and one is a one-bit signal line that transmits a data (DATA) signal. There is a possibility that the data signal lines include one to eight signal lines in correspondence with one bit to eight bits.

(31) For example, in a case of the serial transmission, a single data signal line is included, and eight eight-bit data signal lines are included. In a case of parallel transmission, data is not limited to eight-bit data and may be data having any bits, and signal lines depending on the bit depth are wired. As described later, in the present technology, the sync signal, the valid signal, and the clock signal can be controlled according to the number of data signal lines (bit depth transmitted in one cycle of clock signal).

(32) Furthermore, FIG. 7 is a diagram in which an even-numbered bit and an odd-numbered bit are allocated to outputs of DATA in a case of two-bit parallel transmission. Each bit of data is output from the demodulation processing unit 4 at the rising or falling edge of the clock from a MSB to a LSB in order or from the LSB to the MSB in order, and the processing unit 5 receives (latch) the data at the rising or falling edge of the clock.

(33) The two bits are output by using two bits of eight parallel outputs, and an output terminal of other data may be used. Furthermore, a bit configuration of two bits may have an allocation as illustrated in FIGS. 8A, 8B, 8C, and 8D. FIGS. 8A, 8B, 8C, and 8D are timing charts of data output from each data line in a case of the two-bit parallel transmission.

(34) Furthermore, as illustrated in FIG. 9, one-bit signal line that transmits error information indicating occurrence of an error (ERR) may be further included. The signal line illustrated here is an example, and a signal line that transmits other signal may be naturally provided between the demodulation processing unit 4 and the processing unit 5.

(35) Furthermore, in FIG. 10, a Low voltage differential signaling (LVDS) signal is used for an output interface. The LVDS signal can shorten a rising time and is suitable for increasing the speed. Furthermore, since positive and negative signals are simultaneously output, the signals are symmetrical, and there is an advantage that the noise (EMI) hardly occurs.

(36) Table 1 is a diagram for explaining a certain synchronous byte at a head of a head region of each packet.

(37) TABLE-US-00001 TABLE 1 OUTPUT HEXA- BINARY NUMBER PACKET DECIMAL 7 6 5 4 3 2 1 0 FORMAT NUMBER bit bit bit bit bit bit bit bit OUTPUT 7 F 0 1 1 1 1 1 1 1 PACKET FORMAT FIXED LENGTH 4 7 0 1 0 0 0 1 1 1 TS PACKET (DIVIDED TLV)

(38) There are two types of output packet formats, i.e., a variable length TLV packet and a fixed length TS packet (divided TLV).

(39) As allocation of a part of a header of a packet, a synchronous byte is allocated to the head of the header region of the packet to constantly synchronize the plurality of packets.

(40) Expression of this as hexadecimal numbers is “0×7F” in the variable length TLV packet and “0×47” in the fixed length TS packet (divided TLV). Note that (0×) means the hexadecimal number.

(41) Furthermore, expression in binary number is “8′b0111_1111” in the variable length TLV packet and “8′b0100_0111” in the fixed length TS packet (divided TLV). Note that (8′) means the binary number of eight bit.

(42) Tables 2 and 3 are tables indicating an example of two-bit data in a case of the two-bit parallel transmission.

(43) TABLE-US-00002 TABLE 2 EVEN NUMBER bit MSB — — LSB OUTPUT PACKET FORMAT 6 bit 4 bit 2 bit 0 bit VARIABLE LENGTH TLV PACKET 1 1 1 1 FIXED LENGTH TS PACKET 1 0 1 1 (DIVIDED TLV) ODD NUMBER bit MSB — — LSB OUTPUT PACKET FORMAT 7 bit 5 bit 3 bit 1 bit VARIABLE LENGTH TLV PACKET 0 1 1 1 FIXED LENGTH TS PACKET 0 0 0 1 (DIVIDED TLV) FROM 4 bit TO 7 bit MSB — — LSB OUTPUT PACKET FORMAT 7 bit 6 bit 5 bit 4 bit VARIABLE LENGTH TLV PACKET 0 1 1 1 FIXED LENGTH TS PACKET 0 1 0 0 (DIVIDED TLV) FROM 0 bit TO 3 bit MSB — — LSB OUTPUT PACKET FORMAT 3 bit 2 bit 1 bit 0 bit VARIABLE LENGTH TLV PACKET 1 1 1 1 FIXED LENGTH TS PACKET 0 1 1 1 (DIVIDED TLV)

(44) Data in a case of transmission in FIGS. 8A, 8B, 8C, and 8D will be described.

(45) FIG. 8A is a case where each of even-numbered bits and each of odd-numbered bits are simultaneously transmitted from a Most Significant Bit (MSB) to a Least Significant Bit (LSB) in order.

(46) In this case, in the variable length TLV packet, since bits are transmitted from a sixth bit that is the MSB of the even-numbered bits, “1” in the sixth bit is transmitted, and “1” in the fourth bit is transmitted next. This operation is repeated until “1” in the zeroth bit is transmitted.

(47) Since bits are transmitted from the seventh bit that is the MSB of the odd-numbered bits, “0” in the seventh bit is transmitted, and “1” in the fifth bit is transmitted next. This operation is repeated until “1” in the first bit is transmitted.

(48) In the fixed length TS packet (divided TLV), since bits are transmitted from the sixth bit that is the MSB of the even-numbered bits, “1” in the sixth bit is transmitted, and “0” in the fourth bit is transmitted next. This operation is repeated until “1” in the zeroth bit is transmitted.

(49) Since bits are transmitted from the seventh bit that is the MSB of the odd-numbered bits, “0” in the seventh bit is transmitted, “0” in the fifth bit is transmitted next. This operation is repeated until “1” in the first bit is transmitted.

(50) FIG. 8B is a case where the even-numbered bit and the odd-numbered bit are simultaneously transmitted from the LSB to the MSB in order.

(51) This is a case where bits are transmitted in the reverse order of the transmission from the MSB to the LSB and is obvious. Therefore, description thereof is omitted here.

(52) FIG. 8C is a case where the bits from the fourth bit to the seventh bit and from the zeroth bit to the third bit are simultaneously transmitted from the MSB to the LSB in order.

(53) In this case, in the variable length TLV packet, since bits are transmitted from the seventh bit that is the MSB of bits from the fourth bit to the seventh bit, “0” in the seventh bit is transmitted, and “1” in the sixth bit is transmitted next. This operation is repeated until “1” in the fourth bit is transmitted.

(54) Since bits are transmitted from the third bit that is the MSB of bits from the zeroth bit to the third bit, “1” in the third bit is transmitted, and “1” in the second bit is transmitted next. This operation is repeated until “1” in the zeroth bit is transmitted.

(55) In the fixed length TS packet (divided TLV), since bits are transmitted from the seventh bit that is the MSB from the fourth bit to the seventh bit, “0” in the seventh bit is transmitted, and “1” in the sixth bit is transmitted next. This operation is repeated until “0” in the fourth bit is transmitted.

(56) Since bits are transmitted from the third bit that is the MSB of bits from the zeroth bit to the third bit, “0” in the third bit is transmitted, and “1” in the second bit is transmitted next. This operation is repeated until “1” in the zeroth bit is transmitted.

(57) FIG. 8D is a case where the bits from the fourth bit to the seventh bit and from the zeroth bit to the third bit are simultaneously transmitted from the LSB to the MSB in order. This is a case where bits are transmitted in the reverse order of the transmission from the MSB to the LSB and is obvious. Therefore, description thereof is omitted here.

About Plurality of Carrier Waves

(58) FIG. 11 is a diagram illustrating an example of a system for dividing the large-capacity digital data into the plurality of carrier waves by using the TSMF and performing frequency multiplex transmission, and a cable television station 21, a cable television transmission path 24, and a receiver 31 are included. Variable length TLV packet data (8K signal) and fixed length packet TS data (HD signal) are supplied to the cable television station 21, and the supplied data is multiplexed by a division multiplexing circuit 22.

(59) Since an 8K signal at about 100 MHz cannot be transmitted by one channel (6 MHz) of the cable television, the signal is divided into three channels and is transmitted. The variable length TLV packet data is converted into the fixed length TS packet (divided TLV) and frequency-division multiplexed by a combination of 64-QAM or 256-QAM modulation systems of the ISDB-C broadcasting system, and then is transmitted to the receiver through the cable television transmission path. Therefore, the cable television station 21 includes a 256-QAM modulation circuit 23a, a 256-QAM modulation circuit 23b, and a 64-QAM modulation circuit 23c.

(60) In the receiver 31, a plurality of tuners 32a, 32b, and 32c selects an RF signal that is each carrier wave on which frequency division has been performed as illustrated in FIG. 12 and converts the frequency of the RF signal into an IF signal. FIG. 12 illustrates positions of three carrier waves with respect to the frequency and illustrates a case where 8K broadcasting (one broadcast) and HD broadcasting (one broadcast) are frequency-multiplexed.

(61) A demodulation processing unit 33 includes 256-QAM demodulation circuits 35a and 35b and a 64-QAM demodulation circuit 35c, a demodulation output of each demodulation circuit is synthesized by a synthesis circuit 36. The demodulation processing unit 33 demodulates the carrier waves of the 64-QAM and 256-QAM modulation systems of the ISDB-C broadcasting system and synthesizes the demodulated signals. The 8K signal or the HD signal that is the division-multiplexed signal is extracted and is transmitted to a processing unit 34 that executes demux processing by a demultiplexing unit 37 and decoding processing by a decoder 38 at the subsequent stage.

(62) FIG. 13 is a diagram illustrating an example of a system, which is another form of FIG. 11, for performing frequency multiplex transmission by using four carrier waves. Variable length TLV packet data (4K signal) is supplied to a division multiplexing circuit 42 of a cable television station 41, and the variable length TLV packet data is converted into a fixed length TS packet (divided TLV). Outputs of the division multiplexing circuit 42 are supplied to 64-QAM modulation circuits 43a, 43b, 43c, and 43d and frequency-division multiplexed by a combination of 64-QAM modulation systems of the ISDB-C broadcasting system. Then, the outputs are transmitted to a receiver 51 through a cable television transmission path 44.

(63) In the receiver 51, a plurality of tuners 52a, 52b, 52c, and 52d selects an RF signal that is each carrier wave on which frequency division has been performed as illustrated in FIG. 14 and converts the frequency of the RF signal into an IF signal. Outputs of the tuners 52a to 52d are respectively supplied to 64-QAM demodulation circuits 55a, 55b, 55c, and 55d. Demodulation outputs of the demodulation circuits 55a to 55d are supplied to a synthesis circuit 56.

(64) FIG. 14 illustrates a case where three times of broadcast of 4K broadcasting are frequency-multiplexed. The carrier waves of the 64-QAM modulation system of the ISDB-C broadcasting system is demodulated by the 64-QAM demodulation circuits 55a, 55b, 55c, and 55d of the demodulation processing unit 53, and the synthesis circuit 56 synthesizes the demodulated signals. A division-multiplexed 4K signal is extracted and supplied to the processing unit 51 that executes demux processing by a demultiplexing unit 57 and decoding processing by a decoder 58 at the subsequent stage.

Case where Plurality of Carrier Waves is Received by Present Technology

(65) FIG. 15 is a schematic diagram of a system in which the present technology is applied to a receiver that receives four multiple carrier waves by using the frequency multiplex transmission system as illustrated in FIG. 14. In the receiver, four tuners 61a, 61b, 61c, and 61d select RFs that are frequency-divided carrier waves and supply the RFs to a demodulation group 62.

(66) The demodulation group 62 includes a demodulation circuit 63 including a demodulation processing unit 64d, a demodulation processing unit 64a, a demodulation processing unit 64b, and a demodulation processing unit 64c. The demodulation circuit 63 further includes a multi-carrier wave synthesis circuit and an output interface (I/F) 65. The demodulation group 62 demodulates the carrier waves of the modulation system of the ISDB-C broadcasting system, synthesizes the demodulated signals, extracts a signal that is a division-multiplexed signal, and transmits the signal to a processing unit 66 that executes demux processing and decoding processing at the subsequent stage. The processing unit 66 includes a demultiplexing unit 67 and a decoder 68.

(67) An IF signal output from the tuner 61d is input to an A/D converter (ADC) of the demodulation processing unit 64d of the demodulation circuit 63, and is input to the multi-carrier wave synthesis circuit 65 after being demodulated. Furthermore, a plurality of TS signals TS1, TS2, and TS3 before multi-carrier wave synthesis respectively output from the demodulation processing units 64a, 64b, and 64c is input to the multi-carrier wave synthesis circuit and the output I/F 65 of the demodulation circuit 63. A fixed length packet (TS), a variable length packet (TLV), or a single TS is output from the multi-carrier wave synthesis circuit and the output I/F 65.

(68) An output interface of the multi-carrier wave synthesis circuit and the output I/F 65 includes a SYNC, a VALID, a CLK, and two-bit DATA terminals. This is an example where an even-numbered bit and an odd-numbered bit are allocated to the outputs of data in a case of the two-bit parallel transmission. In a case where up to eight bits can be output in parallel by the DATA terminal and eight terminals are prepared, all the terminals can be used for inputs from the demodulation processing units 64a, 64b, and 64c and two-bit parallel output. Furthermore, an output interface format may be one-bit serial output instead of the two-bit parallel output. Furthermore, the allocation of the outputs of DATA in a case of the two-bit parallel transmission is not limited to the even-numbered bit and the odd-numbered bit.

Modification

(69) One embodiment of the present technology has been specifically described above. However, the present technology is not limited to the above-mentioned embodiment, and various kinds of modifications based on technical ideas of the present technology are possible. Furthermore, the configuration, method, process, shape, material, value, and the like described in the embodiment are merely exemplary, and different configurations, methods, processes, shapes, materials, values, and the like may be used as necessary.

(70) Note that, the present technology can have the following configuration.

(71) (1)

(72) A signal processing device including:

(73) a demodulation processing unit configured to execute demodulation processing;

(74) a processing unit configured to execute demux processing; and

(75) a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the processing unit, in which

(76) a fixed length packet and a variable length packet are transmitted between the demodulation processing unit and the processing unit by using the sync signal line, the valid signal line, the clock signal line, and the data signal line.

(77) (2)

(78) The signal processing device according to (1), in which

(79) the variable length packet includes a TLV packet.

(80) (3)

(81) The signal processing device according to (1), in which

(82) the variable length packet includes a TLV packet, and error information indicating whether or not an error occurs in a packet is included in a packet header region of the TLV packet.

(83) (4)

(84) The signal processing device according to (1), in which

(85) the variable length packet includes a TLV packet, and packet error information is included in a region in which information regarding a packet type included in the TLV packet is written.

(86) (5)

(87) The signal processing device according to (3), further including:

(88) an error signal line that transmits the error information.

(89) (6)

(90) The signal processing device according to (3), in which

(91) the error information is transmitted in error correction code units or variable length packet units.

(92) (7)

(93) The signal processing device according to (1), in which

(94) the one to eight data signal lines are wired, and serial transmission or parallel transmission according to the number of wired data signal lines is performed.

(95) (8)

(96) The signal processing device according to (1), in which

(97) the data signal line has an arbitrary bit width of one to eight bits.

(98) (9)

(99) The signal processing device according to (1), in which

(100) the data signal line transmits data for each eight-bit bit sequence in order starting from a synchronous byte in a header part that is a head of a packet including a TLV stream of the variable length TLV packet or a TS stream of a fixed length TS packet or a fixed length TS packet (divided TLV) converted from the variable length TLV packet.

(101) (10)

(102) The signal processing device according (9), in which

(103) in a case where the data transmitted for each eight-bit bit sequence from the synchronous byte is transmitted by two-bit parallel transmission, outputs of seven bits, five bits, three bits, one bit, six bits, four bits, two bits, and zero bit are allocated to the data signal lines in an output order.

(104) (11)

(105) The signal processing device according (9), in which

(106) in a case where the data transmitted for each eight-bit bit sequence from the synchronous byte is transmitted by two-bit parallel transmission, outputs of one bit, three bits, five bits, seven bits, zero bit, two bits, four bits, and six bits are allocated to the data signal lines in an output order.

(107) (12)

(108) The signal processing device according (9), in which

(109) in a case where the data transmitted for each eight-bit bit sequence from the synchronous byte is transmitted by two-bit parallel transmission, outputs of three bits, two bits, one bit, zero bit, seven bits, six bits, five bits, and four bits are allocated to the data signal lines in an output order.

(110) (13)

(111) The signal processing device according (9), in which

(112) in a case where the data transmitted for each eight-bit bit sequence from the synchronous byte is transmitted by two-bit parallel transmission, outputs of zero bit, one bit, two bits, three bits, four bits, five bits, six bits, and seven bits are allocated to the data signal lines in an output order.

(113) (14)

(114) The signal processing device according to any one of (1) to (6), in which

(115) the sync signal line, the valid signal line, the clock signal line, and the data signal line use Low voltage differential signaling (LVDS) for an output interface.

(116) (15)

(117) The signal processing device according to any one of (10) to (14), in which

(118) in a case where two-bit parallel transmission is performed, two of a plurality of data outputs are allocated as output terminals.

(119) (16)

(120) The signal processing device according to any one of (10) to (14), in which

(121) in a case where two-bit parallel transmission is performed, two of eight data outputs are allocated as output terminals.

(122) (17)

(123) The signal processing device according to (15) or (16), in which

(124) in a system that receives a plurality of carrier waves, a plurality of data outputs, other than outputs used for two-bit parallel output, among the plurality of data outputs is allocated to an input to a synthesis unit that synthesizes the plurality of carrier waves.

(125) (18)

(126) The signal processing device according to (15) or (16), in which

(127) in a system that receives a plurality of carrier waves, six data outputs, other than data outputs used for two-bit parallel output, of eight data outputs are allocated to an input to a synthesis unit that synthesizes the plurality of carrier waves.

(128) (19)

(129) The signal processing device according to (15) or (16), in which

(130) in a system that receives a plurality of carrier waves, six data outputs, other than data outputs used for one-bit serial output, of eight data outputs are allocated to an input to a synthesis unit that synthesizes the plurality of carrier waves.

(131) (20)

(132) A signal processing method including:

(133) including a demodulation processing unit that executes demodulation processing, a processing unit that executes demux processing, and

(134) a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the processing unit; and

(135) transmitting a fixed length packet and a variable length packet between the demodulation processing unit and the processing unit by using the sync signal line, the valid signal line, the clock signal line, and the data signal line.

REFERENCE SIGNS LIST

(136) 61a, 61b, 61c, 61d Tuner

(137) 62 Demodulation group

(138) 63 Demodulation circuit

(139) 64a, 64b, 64c, 64d Demodulation processing unit

(140) 65 Multi-carrier wave synthesis circuit and output I/F

(141) 66 Processing unit

(142) 67 Demultiplexing unit

(143) 68 Decoder