TRANSIMPEDANCE AMPLIFIER, AND RELATED INTEGRATED CIRCUIT AND OPTICAL RECEIVER

Abstract

A transimpedance amplifier includes a first and a second power supply terminal for receiving a positive constant supply voltage, wherein the second power supply terminal represents a ground, and an input terminal adapted to be connected to a current source. The transimpedance amplifier further comprises a transistor comprising a control terminal and two further terminals, wherein the input terminal is connected to the control terminal of the first transistor. An inductor is connected between the first of the two further terminals of the transistor and the first power supply terminal, and a bias network is connected between the second of the two further terminals of the transistor and ground. Specifically, the transimpedance amplifier is configured such that the resistance between said first of said two further terminals of said first transistor and said first power supply terminal is small enough, such that said transimpedance amplifier operates as a differentiator.

Claims

1. A transimpedance amplifier comprising: a first and a second power supply terminal for receiving a positive constant supply voltage, wherein said second power supply terminal represents a ground; an input terminal configured to be electrically coupled to a current source, a first transistor including a control terminal and first and second conduction terminals, wherein said input terminal is electrically coupled to the control terminal of said first transistor; a first inductor electrically coupled between the first conduction terminal of said first transistor and said first power supply terminal; and a bias network electrically coupled between the second conduction terminal of said first transistor and the second power supply terminal; wherein said transimpedance amplifier has a resistance between said first conduction terminal of said first transistor and said first power supply terminal that is small enough to make said transimpedance amplifier operate as a differentiator.

2. The transimpedance amplifier according to claim 1, comprising a bias circuit coupled to the control terminal of said first transistor.

3. The transimpedance amplifier according to claim 1, wherein: said first transistor is an npn bipolar junction transistor, wherein said control terminal of said first transistor is a base of said npn bipolar junction transistor, said first conduction terminal of said first transistor is a collector of said npn bipolar junction transistor and said second conduction terminal of said first transistor is an emitter of said npn bipolar junction transistor, or said first transistor is an n-channel field effect transistor, wherein said control terminal of said first transistor is a gate of said field effect transistor, said first conduction terminal of said first transistor is a drain of said field effect transistor and said second conduction terminal of said first transistor is a source of said field effect transistor.

4. The transimpedance amplifier according to claim 1, wherein said first conduction terminal of said first transistor is connected directly to said first power supply terminal via said first inductor.

5. The transimpedance amplifier according to claim 1, comprising a resistor and an electronic switch configured to selectively couple said resistor in series with said first inductor, such that the resistance between said first conduction terminal of said transistor and said first power supply terminal may be increased selectively.

6. The transimpedance amplifier according to claim 1, comprising: a second inductor; and a second transistor having a control terminal and first and second conduction terminals, wherein said control terminal of said second transistor is configured to receive a reference signal, wherein the first conduction terminal of said second transistor is electrically coupled via the second inductor to said first power supply terminal, and wherein the second conduction terminal of said second transistor is electrically coupled via said polarization network to the second power supply terminal.

7. An integrated circuit comprising: a semiconductor chip; and a transimpedance amplifier integrated in the semiconductor chip and including: a first and a second power supply terminal for receiving a positive constant supply voltage, wherein said second power supply terminal represents a ground; an input terminal configured to be electrically coupled to a current source, a first transistor including a control terminal and first and second conduction terminals, wherein said input terminal is electrically coupled to the control terminal of said first transistor; a first inductor electrically coupled between the first conduction terminal of said first transistor and said first power supply terminal; and a bias network electrically coupled between the second conduction terminal of said first transistor and the second power supply terminal; wherein said transimpedance amplifier has a resistance between said first conduction terminal of said first transistor and said first power supply terminal that is small enough to make said transimpedance amplifier operate as a differentiator.

8. The integrated circuit according to claim 7, wherein the current source is a photodiode having a cathode electrically coupled to said control terminal of said first transistor.

9. The integrated circuit according to claim 7, comprising: a voltage regulator configured to generate said positive constant supply voltage for said transimpedance amplifier.

10. The integrated circuit according to claim 7, comprising: one or more amplifiers electrically coupled in cascade with said transimpedance amplifier.

11. The integrated circuit according to claim 7, comprising: a signal shaper circuit configured to compensate said resistance between said first of said first and second conduction terminals of said first transistor and said first power supply terminal in the frequency spectrum.

12. The integrated circuit according to claim 7, comprising: a further transimpedance amplifier; and an electronic switch configured to selectively enable said transimpedance amplifier or said further transimpedance amplifier.

13. The integrated circuit according to claim 7, wherein the transimpedance amplifier includes a resistor and an electronic switch configured to selectively couple said resistor in series with said first inductor, such that the resistance between said first conduction terminal of said transistor and said first power supply terminal may be increased selectively.

14. The integrated circuit according to claim 7, wherein the transimpedance amplifier includes: a second inductor; and a second transistor having a control terminal and first and second conduction terminals, wherein said control terminal of said second transistor is configured to receive a reference signal, wherein the first conduction terminal of said second transistor is electrically coupled via the second inductor to said first power supply terminal, and wherein the second conduction terminal of said second transistor is electrically coupled via said polarization network to the second power supply terminal.

15. An optical receiver comprising: a photodiode; and a transimpedance amplifier including: a first and a second power supply terminal for receiving a positive constant supply voltage, wherein said second power supply terminal represents a ground; a first transistor including a control terminal and first and second conduction terminals, wherein said control terminal is electrically coupled a cathode of the photodiode; a first inductor electrically coupled between the first conduction terminal of said first transistor and said first power supply terminal; and a bias network electrically coupled between the second conduction terminal of said first transistor and the second power supply terminal; wherein said transimpedance amplifier has a resistance between said first conduction terminal of said first transistor and said first power supply terminal that is small enough to make said transimpedance amplifier operate as a differentiator.

16. The optical receiver according to claim 15, comprising: a voltage regulator configured to generate said positive constant supply voltage for said transimpedance amplifier.

17. The optical receiver according to claim 15, comprising: one or more amplifiers electrically coupled in cascade with said transimpedance amplifier.

18. The optical receiver according to claim 15, comprising: a signal shaper circuit configured to compensate said resistance between said first of said first and second conduction terminals of said first transistor and said first power supply terminal in the frequency spectrum.

19. The optical receiver according to claim 15, comprising: a further transimpedance amplifier; and an electronic switch configured to selectively enable said transimpedance amplifier or said further transimpedance amplifier.

20. The optical receiver according to claim 15, wherein the transimpedance amplifier includes a resistor and an electronic switch configured to selectively couple said resistor in series with said first inductor, such that the resistance between said first conduction terminal of said transistor and said first power supply terminal may be increased selectively.

21. The optical receiver according to claim 15, wherein the transimpedance amplifier includes: a second inductor; and a second transistor having a control terminal and first and second conduction terminals, wherein said control terminal of said second transistor is configured to receive a reference signal, wherein the first conduction terminal of said second transistor is electrically coupled via the second inductor to said first power supply terminal, and wherein the second conduction terminal of said second transistor is electrically coupled via said polarization network to the second power supply terminal.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0039] Embodiments of the present disclosure will now be described with reference to the annexed drawings, which are provided purely by way of non-limiting example and in which:

[0040] FIGS. 1 to 7 have already been described in the foregoing;

[0041] FIG. 8 shows a first embodiment of the frontend of an optical receiver in accordance with the present disclosure;

[0042] FIG. 9 shows a circuit schematic of a small signal model of the optical frontend of FIG. 8;

[0043] FIG. 10 shows a second embodiment of the frontend of an optical receiver in accordance with the present disclosure;

[0044] FIG. 11 shows an embodiment of an optical receiver in accordance with the present disclosure; and

[0045] FIGS. 12 to 16 show further embodiments of optical receivers in accordance with the present disclosure.

DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or several specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0047] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases in one embodiment or in an embodiment in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0048] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0049] In the following FIGS. 8 to 15 parts, elements or components which have already been described with reference to FIGS. 1 to 7 are denoted by the same references previously used in such Figures; the description of such previously described elements will not be repeated in the following in order not to overburden the present detailed description.

[0050] As mentioned in the foregoing, the present disclosure provides a novel transimpedance amplifier, which may be used to convert an input current into a output voltage, and which is suitable for high speed applications, such as above 25 GHz.

[0051] Accordingly, the transimpedance amplifiers of the present disclosure may be used in high-speed optical receivers.

[0052] FIG. 8 shows in this respect the basic architecture of the front end of an optical receiver in accordance with one embodiment of the present disclosure.

[0053] Specifically, also in this case, a photodiode PD is connected to a transimpedance amplifier 32a.

[0054] For example, in the embodiment considered, the photodiode PD is biased as in FIG. 2, i.e., by means of a resistor or active impedance R.sub.bias connected between the cathode of the photodiode PD and a positive constant bias voltage +V.sub.bias. For example, a resistor R.sub.bias with a resistance between 1 and 20 kOhm, e.g., 3 to 5 kOhm, may be used for this purpose. However, also other circuits may be used to bias the photodiode PD.

[0055] Accordingly, also in the present optical front end, which is based on a transimpedance amplifier 32a, associated with the photodiode is a parasitic capacitance C.sub.PD. Similarly, also the transimpedance amplifier 32a exhibits an input capacitance C.sub.BE, which both influence negatively the bandwidth of the system.

[0056] In this respect, the inventors have observed that the capacitances C.sub.PD and C.sub.BE constitute a low pass filter, which represents an analog integrator I.

[0057] However, instead of trying to compensate the influence of this low-pass filter by a suitable filter structure at the input of the transimpedance amplifier 32a (e.g., series inductive peaking as shown in FIGS. 6 and 7), the present disclosure proposes the use of a transimpedance amplifier amplification stage, which operates as an analog differentiator D.

[0058] Specifically, in the embodiment shown in FIG. 8, the differentiator D is implemented with a npn bipolar transistor Q3 and a loading inductor L.sub.C. In the embodiment considered, the base of the transistor Q3 is connected (e.g., directly) to the cathode of the photodiode PD, the collector is connected (e.g., directly) to a supply voltage VDD by means of an inductor L.sub.C, and the emitter is connected (e.g., directly) to ground GND by means of a bias network BN.

[0059] For example, in the single ended configuration considered, the bias network BN may be implemented with a resistor R.sub.E and an optional capacitor C.sub.PN connected both in parallel between the emitter of the transistor Q3 and ground GND. For example, the capacitance of the capacitor C.sub.PN may be selected from the range of 5 to 50 pF (picofarad), e.g., 10 to 20 pF.

[0060] Accordingly, in the embodiment considered, only the inductor L.sub.C is connected between the supply voltage VDD and the collector C of the transistor Q3. Generally, the supply voltage VDD may be any constant positive voltage, such as a voltage selected between 1 and 5 VDC with respect to ground GND. For example, such a supply voltage VDD may be obtained through a voltage regulator, which should exhibit a rather low output impedance at high frequencies.

[0061] Thus, generally, also the embodiment shown in FIG. 8 comprises an inductor connected to the collector of a transistor. However, contrary to the inductive shunt peaking technique shown in FIG. 5, this inductor L.sub.C is not used to compensate the output capacitance C.sub.out, but implements a differentiator D, which thus permits to compensate the integrator behavior of the capacitances at the input (C.sub.PD and C.sub.BE).

[0062] FIG. 9 shows in this respect a possible small signal model of the circuit shown in FIG. 8.

[0063] Specifically, as mentioned in the foregoing, the photodiode PD may be modelled with a current generator 100. For example, typical photodiodes provide a current variation in the range between 10 and 150 A (microampere), e.g., 20-50 A.

[0064] This current generator 100 is connected between the base of an (ideal) npn bipolar junction transistor Q4 having the gain g.sub.m of the transistor Q3.

[0065] Between the base of the transistor Q4 and ground GND is connected a capacitance C.sub.in, which models the capacitance C.sub.PD of the photodiode PD and the capacitance C.sub.BE of the bipolar transistor Q3. For example, for typical photodiodes and BJT transistors, the value of C.sub.1r, may be in the range of 10 to 100 fF (femtofarad), e.g., 20 to 50 fF.

[0066] Similarly, a capacitance C.sub. is connected between the base and the collector of the transistor Q4. This capacitance C.sub. models the base-collector capacitance of the transistor Q3. Finally, the inductor L.sub.C is connected between the collector of the transistor Q4 and the supply voltage VDD.

[0067] Accordingly, by resolving the related circuit equations, the output voltage may be approximated as:

[00001]$V_{\mathrm{out}}=\left(\frac{g_m}{s\left(C_{\mathrm{in}}+C_{}\right)}\right).Math.I_s\left(s\right)*\left(\mathrm{sL}//g_m\left(\frac{C_{\mathrm{in}}}{C_{}}\right)\right)$

where the operator // indicates that these components are connected in parallel (with A//B=(AB)/(A+B)). Accordingly, based on typical values of the above components, the term g.sub.m(C.sub.in/C.sub.) may be neglected.

[0068] From the above equation may thus be observed that the output impedance fully compensates the input impedance. In fact, merely the gain of the transimpedance amplifier 32a is decreases with increasing input capacitance values.

[0069] In the embodiment considered, the circuit operates without a feedback resistor, i.e., in an open loop configuration, which is significantly faster than the closed loop approach. Those of skill in the art will appreciate that the lack of feedback resistor also removes the associated noise. At high frequency, where the inductance is a high impedance, a further minor reducing effect may still be obtained by the feedback coupling of the parasitic capacitance C.sub. between the base and the collector of the transistor Q3. Accordingly, the circuit in accordance with the present disclosure has significant advantages over the usual closed loop configuration with feedback-resistor, in particular with regards to the operation speed.

[0070] FIG. 10 shows an embodiment of a differential implementation of a transimpedance amplifier 32b in accordance with the present description.

[0071] In the embodiment considered, the transimpedance amplifier 32b is again coupled to a photodiode PD, which is in some way biased. For example, in the embodiment considered, the photodiode PD is biased via a resistor R.sub.bias connected between the cathode of the photodiode and a positive bias voltage V.sub.bias.

[0072] Similarly, to the single-ended configuration shown in FIG. 8, the photodiode PD is connected (e.g., directly) to the base of a npn bipolar junction transistor Q3.sub.1, which corresponds to the transistor in FIG. 8. Accordingly, also in this configuration, the collector of the transistor Q3.sub.1 is connected (e.g., directly) via an inductor L.sub.C1 to a constant positive supply voltage, e.g., VDD, and the emitter of the transistor Q3.sub.1 is connected (e.g., directly) via a bias network BN to ground.

[0073] For example, in a differential configuration, the bias network BN may be implemented with a current generator 102 and an optional capacitor C.sub.PN connected in parallel. For example, in the embodiment considered, the current generator 102 may provide a current selected between 100 A (microampere) and 10 mA (milliampere), e.g., between 400 A and 4 mA.

[0074] The capacitance of the capacitor C.sub.PN may again be selected from the range of 5 to 50 pF (picofarad), e.g., 10 to 20 pF.

[0075] Accordingly, in the embodiment considered, the emitter of the transistor Q3.sub.1 is connected via the current generator 102 to ground GND.

[0076] In order to implement a differential configuration, the transimpedance amplifier 32b comprises a complementary branch. Specifically, in the embodiment considered, the transimpedance amplifier 32b comprises a second npn bipolar junction transistor Q3.sub.2, wherein the collector of the transistor Q3.sub.2 is connected (e.g., directly) via a second inductor L.sub.C2 to a constant positive supply voltage, e.g., VDD, and the emitter of the transistor Q3.sub.1 is connected (e.g., directly) via the bias network BN to ground GND. The inductors L.sub.C1 and L.sub.C2 may have the same inductance and/or the inductance may be selected based on the value of the input capacitance C.sub.in, e.g., in the range between 500 pH (picohenry) and 5 nH (nanohenry), e.g., 1 to 2 nH.

[0077] Different solutions may be used to obtain a reference signal REF at the base of the transistor Q3.sub.2. For example, in the embodiment considered, the base of transistor Q3.sub.2 is connected via a resistor R.sub.Set to a constant positive voltage, such as VDD.

[0078] However, also more complex solutions may be used, such as a second photodiode (with associated bias circuit). In this case, the second photodiode is not illuminated and merely provides the reference signal REF for the base of the transistor Q3.sub.2.

[0079] In various embodiments, the transimpedance amplifiers 32a and 32b may comprise also a load resistor R.sub.L connected (e.g., directly) in parallel with the inductor L.sub.C or two load resistors R.sub.L1 and R.sub.L2 connected respectively in parallel with the inductors L.sub.C1 and L.sub.C2. These resistors may be suitable to damp the resonance peak given by the inductors and the load capacitance C.sub.out.

[0080] For example, the resistance of these load resistors may be selected from the range between 50 Ohm and 500 Ohm, e.g., 100 to 300 Ohm.

[0081] Generally, as already mentioned with respect to FIG. 4, the npn bipolar junction transistors Q3, Q3.sub.1 and Q3.sub.2 of a transimpedance amplifier 32a/32b may also be replaced with a FET (field effect transistor), such as an n-channel MOSFET (metal-oxide-semiconductor field-effect transistor).

[0082] Accordingly, as shown in FIG. 11, an optical receiver circuit 3a in accordance with the present disclosure comprises a photodiode PD, a transimpedance amplifier 32a/32b and a processing circuit 36.

[0083] For example, the optical receiver circuit 3a may be integrated in an integrated circuit that is integrated in a semiconductor chip. Generally, the photodiode PD and/or the processing circuit 36 may be integrated with the transimpedance amplifier 32a or 32b or provided on a separate chip.

[0084] The optical receiver circuit 3a may also comprise one or more voltage regulator 38a and 38b configured to generate the voltages VDD and V.sub.bias for the transimpedance amplifier 32a or 32b. As mentioned in the foregoing, the voltage regulator 32a used to generate the voltage VDD should exhibit a rather low output impedance at high frequencies.

[0085] Finally, between the transimpedance amplifier 32a/32b and the processing circuit 36 may be provided also further analog and/or digital signal processing stages 34a, such as one or more amplifier stages and/or filters, such as bandpass filters.

[0086] For example, FIG. 12 shows an embodiment, in which the output of a differential transimpedance amplifier 32b is fed to one or more further amplifiers CH.sub.1, CH2. For example, these amplifiers CH.sub.1, CH2 may implement a Cherry-Hooper chain.

[0087] Between the various stages may also be provided filters, such as low pass RC filters comprising a resistor R.sub.CH and a capacitor C.sub.CH.

[0088] FIG. 14 shows an embodiment, in which the signal processing block 34a comprises at least one signal shaper circuit 342.

[0089] Specifically, as shown in FIG. 13, indeed also the inductor Lc will exhibit an equivalent series parasitic resistance R.sub.par.

[0090] However, compared to a conventional resistor R.sub.C as shown, e.g., in FIG. 5, this resistance R.sub.par is usually smaller than 20 Ohm, e.g., smaller than 10 Ohm, and represents merely the parasitic resistance of the inductor L.sub.C and possible line losses.

[0091] However, at very low frequencies, the transimpedance gain of the amplifier will be affected by this parasitic resistance R.sub.par. Specifically, at low frequencies, the gain Z.sub.DC of the transimpedance amplifier may be approximated by:

Z.sub.DC=R.sub.ing.sub.mR.sub.par

where R.sub.in represents the input resistance, which, e.g., corresponds to the bias resistance R.sub.bias and the photodiode resistance R.sub.PD in case of the photodiode PD is biased as shown in FIG. 2b.

[0092] Accordingly, as shown in FIG. 14, the low frequency gain of the amplifier 32a/32b is usually smaller than the high frequency gain (up to the cut off frequency of the amplifier). Accordingly, a shaper circuit 342, such as a zero pole equalizer, may be added in order to render the frequency gain again flat.

[0093] Finally, in order to handle different value ranges of optical power, i.e., different ranges of currents provided by the phododiode PD, the optical front end may comprise a plurality of transimpedance amplifiers, which may be enabled selectively.

[0094] For example, FIG. 15 shows an embodiment, in which the optical receiver comprises in addition to a transimpedance amplifier 32a or 32b described in the foregoing a second transimpedance amplifier 32c. For example, the optical receiver 3a may be configured to enable (e.g., by means of an electronic switch S.sub.1) the transimpedance amplifier 32a/32b for small currents I.sub.S, e.g., below 50 A, and enable (e.g., by means of an electronic switch S.sub.2) the transimpedance amplifier 32c for higher currents I.sub.S, e.g., above 50 A. In this case, the transimpedance amplifier 32c may also be implemented with a conventional transimpedance amplifier, such as a closed loop TIA, because the signal to noise ratio is in this case sufficiently high.

[0095] In various embodiments, the gain of the transimpedance amplifier 32a or 32b may be variable.

[0096] For example, as shown in FIG. 16, the amplifier 32a (and similarly also the amplifier 32b) may comprise a resistor R.sub.C and an electronic switch S.sub.3. Specifically, the electronic switch S.sub.3 may be used to short circuit the resistor R.sub.C or connect the resistor R.sub.C in series with the inductor L.sub.C, thereby transforming the transimpedance amplifier 32a or 32b of the present disclosure in a conventions transimpedance amplifier with inductive shunt peaking as shown, e.g., in FIG. 5.

[0097] Specifically, when the switch S.sub.3 is closed, the resistance between the collector of the transistor Q3 and the supply voltage VDD will again be so small that the transimpedance amplifier operates as a differentiator in the spectrum region where most of signal energy is located.

[0098] Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure.

[0099] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.