Method for fabricating miniature structures or devices such as RF and microwave components
09620834 ยท 2017-04-11
Assignee
Inventors
- Elliott R. Brown (Glendale, CA, US)
- John D. Evans (Alexandria, VA, US)
- Christopher A. Bang (Northridge, CA, US)
- Adam L. Cohen (Dallas, TX, US)
- Michael S. Lockard (Lake Elizabeth, CA, US)
- Dennis R. Smalley (Newhall, CA)
- Morton Grosser (Menlo Park, CA, US)
Cpc classification
B33Y10/00
PERFORMING OPERATIONS; TRANSPORTING
Y10T29/49002
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
C25D1/003
CHEMISTRY; METALLURGY
H01P11/00
ELECTRICITY
Y10T29/49018
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
H05K3/4647
ELECTRICITY
Y10T29/49016
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
H01P5/18
ELECTRICITY
H01P11/00
ELECTRICITY
Abstract
Multi-layer, multi-material fabrication methods include depositing at least one structural material and at least one sacrificial material during the formation of each of a plurality of layers wherein deposited materials for each layer are planarized to set a boundary level for the respective layer and wherein during formation of at least one layer at least three materials are deposited with a planarization operation occurring before deposition of the last material to set a planarization level above the layer boundary level and wherein a planarization occurs after deposition of the last material level above the layer boundary level and wherein a planarization occurs after deposition of the last material whereby the boundary level for the layer is set. Some formation processes use electrochemical fabrication techniques (e.g. including selective depositions, bulk depositions, etching operations and planarization operations) and post-deposition processes (e.g. selective etching operations and/or back filling operations).
Claims
1. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; a substrate to which the outer conductor connects; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor.
2. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor, and wherein the outer conductor comprises a plurality of stacked planar layers.
3. A coaxial waveguide, comprising: a center conductor; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the outer conductor is monolithic and comprises a plurality of planar layers.
4. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor, wherein the outer conductor further comprises a conductive base to which the walls connect and wherein the conductive base is located below the central conductor.
5. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor, wherein the outer conductor further comprises a conductive top to which the walls connect and wherein the conductive top is located above the central conductor.
6. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor, wherein a dielectric support member extends only from one side of the outer conductor to the central conductor but not to an opposite side of the outer conductor.
7. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor, wherein the waveguide is functionally coupled to an active electronic device.
8. A three-dimensional microstructure, comprising: a first microstructural element formed of a first material; and a second microstructural element formed of a second material different from the first material; a third microstructural element formed of a third material that is different from the second material; wherein the second microstructural element comprises an anchoring portion embedded in the first microstructural element and contacting the third microstructural element for mechanically locking the first microstructural element to third microstructural element via the second microstructural element, wherein each of the first and third microstructural elements comprises a conductor and the second microstructural element comprises a dielectric, and wherein at least one of the first and third microstructural elements is a monolithic structure comprising a plurality of adhered planar layers of a conductor.
9. The microstructure of claim 8 wherein the anchoring portion includes a change in cross-section.
10. The microstructure of claim 8 configured to function as a coaxial microwave or RF component.
11. A three-dimensional microstructure, comprising: a first microstructural element formed of a first material; and a second microstructural element formed of a second material different from the first material; a third microstructural element formed of a third material that is different from the second material; wherein the second microstructural element comprises an anchoring portion embedded in the first microstructural element and contacting the third microstructural element for mechanically locking the first microstructural element to third microstructural element via the second microstructural element wherein one of the first-third microstructural elements contains a patterned locking portion that mechanically locks the respective element to another of the first to third elements.
12. The microstructure of claim 11 wherein the patterned locking portion comprises an opening through at least one of the first-third elements.
13. The microstructure of claim 11 wherein the first material comprises a metal, the second material comprises a dielectric, and the third material comprises a metal.
14. A three-dimensional microstructure formed by a sequential build process, comprising: a first microstructural element formed of a first material; and a second microstructural element formed of a second material different from the first material; wherein the first or second microstructural element comprises an anchoring portion embedded in the other of the first or second microstructural element for mechanically locking the first microstructural element to the second microstructural element, wherein the anchoring portion includes a change in cross-section so as to provide locking.
15. The microstructure of claim 14 wherein the first material comprises a metal, the second material comprises a dielectric, and the third material comprises a metal.
16. A coaxial waveguide, comprising: a center conductor having a length; an outer conductor comprising one or more walls, spaced apart from and disposed around the center conductor; one or more dielectric support members for supporting the center conductor in contact with the center conductor and partially embedded within the outer conductor; and a core volume between the center conductor and the outer conductor, wherein the core volume is under vacuum or in a gas state, wherein the core volume completely surrounds at least portions of the length of the central conductor and wherein the core volume defines a passage having a length, at least one conductive spoke extending between the central conductor and the outer conductor at each of a plurality of locations where successive locations along the length of the passage are spaced by approximately one-half of a propagation wavelength, or an integral multiple thereof, within the passage for a frequency to be passed by the component, wherein one or more of the following conditions are met: (1) the central conductor, the conductive structure, and the conductive spokes are monolithic; (2) a cross-sectional dimension of the passage perpendicular to a propagation direction of the radiation along the passage is less than about 1 mm, more preferably less than about 0.5 mm, and most preferably less than about 0.25 mm; (3) more than about 50% of the passage is filled with a gaseous medium, more preferably more than about 70% of the passage is filled with a gaseous medium, and most preferably more than about 90% of the passage is filled with a gaseous medium; (4) at least a portion of the conductive portions of the component are formed by an electrodeposition process; (5) at least a portion of the conductive portions of the component are formed from a plurality of successively deposited layers; (6) at least a portion of the passage has a generally rectangular shape; (7) at least a portion of the central conductor has a generally rectangular shape; (8) the passage extends along a two-dimensional non-linear path; (9) the passage extends along a three-dimensional path; (10) the passage comprises at least one curved region and a side wall of the passage in the curved region has a nominally smaller radius than an opposite side of the passage in the curved region and is provided with a plurality of surface oscillations having smaller radii; (11) the conductive structure is provided with channels at one or more locations where the electrical field at a surface of the conductive structure, if it were there, would have been less than about 20% of its maximum value within the passage, more preferably less than 10% of its maximum value within the passage, even more preferably less than 5% of its maximum value within the passage, and most preferably where the electrical field would have been approximately 0% of its maximum value; (12) the conductive structure is provided with patches of a different conductive material at one or more locations where the electrical field at the surface of the conductive structure, if it were there, would have been less than about 20% of its maximum value within the passage more preferably less than about 10% of its maximum value within the passage, even more preferably less than about 5% of its maximum value within the passage, and most preferably where the electrical field would have been approximately 0% of its maximum value; (13) mitered corners are used at least some junctions for segments of the passage that meet at angles between 60 and 120; and/or (14) the conductive spokes are spaced at an integral multiple of one-half the wavelength and bulges on the central conductor or bulges extending from the conductive structure extend into the passage at one or more locations spaced from the conductive spokes by an integral multiple of approximately one-half the wavelength.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
(46) A basic process of electrochemically forming layers of multilayer three-dimensional structures was presented in
(47) For example, in some embodiments, process variations may be used to yield cavities within the conductive structures that are filled completely or partially with a dielectric material, a conductive material embedded in a dielectric, or a magnetic material (e.g. a powdered ferrite material embedded in a dielectric binder or sintered after placement). The dielectric material(s) may be used as support structures to hold conducting elements separate from one another and/or they may be used to modify the microwave transmission or absorption properties of particular devices. A dielectric may be incorporated into the structures during a layer-by-layer buildup of the structures or may be back-filled in bulk or selectively into the structures after all layers have been formed.
(48) As a further example, in other embodiments, it may be desirable to have a structure composed of more than one conductive material (e.g. nickel and gold or copper and gold) and as such the process variations may be implemented to accomplish this result.
(49) Some preferred embodiments of the invention provide microminiature RF or microwave transmission lines. Such transmission lines may be used as building blocks for RF and microwave components. A preferred transmission line has a rectangular coaxial structure that includes a rectangular solid-metal center conductor and a solid metal outer conductor. When used herein, a microminiature coaxial component or line shall mean a component having a minimum cross-sectional dimension from one inside wall of the outer conductor to the opposite inside wall of the outer conductor is less than about 200 m. Coaxial transmission line is well suited to such microminiaturization because it supports a transverse electromagnetic (TEM) fundamental mode. From fundamental electromagnetic theory, a TEM mode is known to have a zero cut-off frequency. So the TEM mode continues to propagate at any practical frequency no matter how small the dimensions of the structure.
(50) Three benefits of microminiaturized coaxial line are size, microwave bandwidth, and phase linearity. In general, the physical length of passive transmission-line components must be of the order of one free-space wavelength at the operating frequency which is, for example, 30 cm at 1 GHz. With conventional coaxial transmission line or waveguide, this results in a component having a linear dimension of this order. With microminiature coaxial line, the component can be made much shorter by wrapping the line back and forth in a serpentine fashion and even by stacking the multiple serpentine levels of the line.
(51) A second benefit of microminiature coax is excellent bandwidth performance. In any coaxial transmission line this is defined maximally by the cut-on frequency of the first higher-order mode, which is usually a transverse-electric (TE) mode. From fundamental electromagnetics, it is known that this cut-on frequency scales inversely with the largest dimension of the outer conductor. In conventional coax this cut-on generally occurs between 10 and 50 GHz. In microminiature coax this cut-on can easily be extended to well above 100 GHz, giving it the bandwidth to handle the highest frequencies in near-term analog systems and the sharpest pulses in digital systems.
(52) A third benefit of microminiature coax is its degree of phase linearity. From fundamental electromagnetics, it is known that the TEM mode is the only mode on a transmission line that can propagate with zero dispersion. In other words, all frequencies within the operational bandwidth have the same phase velocity, so the dependence of relative phase between two arbitrary points on the line is perfectly linear with frequency. Because of this property, sharp non-sinusoidal features, such as sharp digital edges or short digital pulses propagate without distortion. All of the other known transmission line media at the size scale of microminiature coax (i.e., less than 200 m) do not propagate a pure TEM mode but rather a quasi-TEM mode. A good example is the strip line commonly used in Si digital ICs or the microstrip commonly used in GaAs or InP MMICs (monolithic microwave integrated circuits).
(53) Beside the dimension, another feature of some preferred microminiature coaxial lines is their rectangular shape cross-sectional shape. Conventional coaxial lines are generally made of circular center and outer conductors because of the relative simplicity in fabricating a circular shape (e.g., round wire) for the center conductor and a hollow tube (e.g., catheter) as the outer conductor. Fundamental electromagnetic theory shows that rectangular coax can provide very similar performance to circular coax, although analytic methods of design are lacking. Fortunately, numerical tools (e.g., high-frequency structure simulator, or HFSS, software) are now readily available which can aid in the design of components such as rectangular microminiature coax of any shape or size.
(54) In some preferred embodiments microminiature coaxial line is used in producing ultra-compact microwave components by, at least in part, utilization of the electrochemical fabrication techniques and particularly electrochemical fabrications techniques using conformable contact masks. There is an entire family of passive microwave functions that cannot be realized in semiconductor ICs, or that can be realized only with a significant penalty in performance. A good example of a function that cannot be realized on a semiconductor IC is circulationi.e., the nonreciprocal transmission of microwave power between neighboring ports around a loop. An example of a function with inferior IC performance is frequency multiplexingi.e., the routing of microwave power from one input port into a number of different output ports depending on frequency. Microminiature coaxial lines may be used in forming components that can provide such functionality particularly when combined with the versatility of electrochemical fabrication processes.
(55) In some preferred embodiments, microminiature coaxial line is integrated with active semiconductor devices, particularly RF and high-speed digital ICs. Such integration addresses a growing problem in the IC industry which is the interconnecting and routing of high-frequency analog and digital signals within chips. A good example of where such integration would be useful is in clock distribution in high speed microprocessors. Transmission of very sharp edges down conventional (stripline) transmission lines on Si invariably distorts, or spreads out, the edge because of dispersion and losses on the line. With microminiature coaxial lines, the clock signal could be coupled immediately into a single-mode coaxial structure in which the fundamental and all Fourier components of the clock pulse would propagate for long distances with the same velocity. As such, the clock pulse distortion, and associated clock skew, could be mitigated.
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(57) TABLE-US-00002 TABLE 1 Reference Dimension Reference Dimension Reference Dimension 122 520 m 124 400 m 126 520 m 128 400 m 130 116 m 132 116 m 134 180 m 136 168 m 138 40 m 140 168 m 142 40 m 144 180 m 146 60 m 148 60 m 150 40 m 152 40 m 154 40 m 156 .sub.o/2 158 .sub.o/2
(58) In other embodiments the dimensions may be varied to change the insertion loss of the filter in the pass band, the attenuation in the stop band, and the characteristics in the transition region. In other embodiments various parameters may also be modified by varying the material or materials from which the filter and/or filter components are made. For example, the entire filter may be formed from nickel or copper, or it may be partially or entirely plated with silver or gold.
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(60) In alternative embodiments other numbers of poles may be used in forming the filter (e.g. three poles or five or more poles).
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(62) TABLE-US-00003 TABLE 2 Reference Dimension Reference Dimension Reference Dimension 222 920 m 224 800 m 226 320 m 228 200 m 230 316 m 232 59 m 234 80 m 236 88 m 238 40 m 240 168 m 242 76 m 244 362 m 246 60 m 248 60 m
(63) As with the square coaxial filter of
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(66) As an example, the embodiment of
(67) TABLE-US-00004 TABLE 3 Reference Dimension Reference Dimension Reference Dimension 222 720 m 224 600 m 226 420 m 228 300 m 230 175 m 232 87 m 234 130 m 236 125 m 238 40 m 240 250 m 246 60 m 248 60 m
(68) In alternative embodiments, other spoke numbers (e.g. three or five) and configurations (e.g. multiple spokes extending from a single side of the conductor, not all spokes extending radically outward from the inner conductor to the outer conductor) may exist.
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(73) In further embodiments other configurations of spokes, protrusions, and/or indentations are possible. In some embodiments, it may be acceptable to space the successive filter elements (e.g. spokes, protrusions, and/or indentations) at integral multiples of o/2.
(74) In the embodiments of
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(79) TABLE-US-00005 TABLE 4 Reference Dimension Reference Dimension Reference Dimension 502 300 m 504 300 m 506 25 m 508-S0 245 m 508-S1 165 m 508-S2 25 m 512 .sub.o/4 514 .sub.o/4 516 .sub.o/4 (250 mm) (250 mm) (250 mm) 522 3.00 mm 524 1.64 mm 526 200 m 528 100 m
(80) Each pair of stubs 522 and 524 provide a capacitive and an inductive reactance, respectively, whose combination provides a pole of the filter. Each stub is shorted to the outside conductor 556 at the end of its side channel 552 and 554 respectively. The spacing between the poles preferably approximates one-quarter of the wavelength (.sub.o/4) of the central frequency of the desired pass band of the filter. The lengths of the stubs are selected to provide a capacitive reactance (e.g. something longer than .sub.o/4) and an inductive reactance (something shorter than .sub.o/4). In alternative embodiments it is believed that spacing between the poles may be expanded to an integral multiple of .sub.o/4, other filtering elements may be added into the component (e.g. spokes, protrusions, and the like).
(81) In other embodiments the dimensions may be varied to change the insertion loss of the filter in the pass band, the attenuation in the stop band, and the characteristics in the transition region as well as in the pass band regions. In this other embodiments various parameters may also be modified by varying the material or materials from which the filter and/or filter components are made. For example, the entire filter may be formed from nickel or copper, or it may be partially or entirely plated with silver or gold.
(82) In alternative embodiments it may be possible to form each pole from one shorted stub (providing a shunt inductance) and one open stub (providing a shunt capacitance) that terminates short of the end of the channel (e.g. into a dielectric) wherein the capacitive stub may be able to be shortened due to its open configuration.
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(86) TABLE-US-00006 TABLE 5 Feature Dimension Inside width of the outer conductor 600 m Inside Height of the outer conductor 300 m Width of the central (i.e. inner) conductor 250 m Height of the central (i.e. inner) conductor 75 m Height of the horizontally extending spokes 40 m Thickness (i.e. dimension into the page) of 100 m he horizontally extending spokes Spacing between successive sets of spokes ~5-5.5 mm
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(90) The process of
(91) After setting the current layer number, the process moves forward to decision block 704 where an inquiry is made as to whether or not the surface of the substrate is entirely conductive or at least sufficiently conductive to allow electrodeposition of a conductive material in desired regions of the substrate. If material is only going to be deposited in a region of the substrate that is both conductive and has continuity with a portion of the substrate that receives electrical power, it may not be necessary for the entire surface of the substrate to be conductive. In the present embodiment, the term substrate is intended to refer to the base on which a layer of material will be deposited. As the process moves forward the substrate is modified and added to by the successive deposition of each new layer.
(92) If the answer to the inquiry is yes, the process moves forward to block 708, but if the answer is no the process first moves to block 706 which calls for the application of a seed layer of a first conductive material on to the substrate. The application of the seed layer may occur in many different ways. The application of the seed layer may be done in a selective manner (e.g. by first masking the substrate and then applying the seed layer and thereafter removing the mask and any material that was deposited thereon) or in a bulk or blanket manner. A conductive layer may be deposited, for example, by a physical or chemical vapor deposition process. Alternatively it may take the form of a paste or other flowable material that can be solidified or otherwise bonded to the substrate. In a further alternative it may be supplied in the form of a sheet that is adhered or otherwise bonded to the substrate. The seed layer is typically very thin compared to the thickness of electrodeposition that will be used in forming the bulk of a layer of the structure.
(93) After application of the seed layer, the process moves forward to block 708 which calls for the deposition of a second conductive material. The most preferred deposition process is a selective process that uses a dielectric CC mask that is contacted to the substrate through which one or more openings exist and through which openings the conductive material can be electrodeposited on to the substrate (e.g. by electroplating). Other forms of forming a net selective deposit of material may also be used. In various alternatives of the process, the first and second conductive materials may be different or they may be the same material. If they are the same the structure formed may have more isotropic electrical properties, whereas if they are different a selective removal operation may be used to separate exposed regions of the first material without damaging the second material.
(94) The process then moves forward to block 710 which calls for removing the portion of the seed layer that is not covered by the just deposited conductive material. This is done in preparation for depositing the dielectric material. In some embodiments, it may be unnecessary to remove the seed layer in regions where it overlays the conductive material deposited on an immediately preceding layer but for simplicity in some circumstances a bulk removal process may still be preferred. The seed layer may be removed by an etching operation that is selective to the seed layer material (if it is different from the second conductive material). In such an etching operation, as the seed layer is very thin, as long as reasonable etching control is used, little or no damage should result to the seed layer material that is overlaid by the second conductive material. If the seed layer material (i.e. the first conductive material) is the same as the second conductive material, controlled etching parameters (e.g. time, temperature, and/or concentration of etching solution) should allow the very thin seed layer to be removed without doing any significant damage to the just deposited second conductive material.
(95) Next the process moves forward to block 712 which calls for the deposition of a dielectric material. The deposition of the dielectric material may occur in a variety of ways and it may occur in a selective manner or in a blanket or bulk manner. As the process of the present embodiment forms planarized composite layers that include distinct regions of conductive material and distinct regions of the dielectric material, and as any excess material will be planed away, it does no harm (other than that associated with potential waste) to blanket deposit the dielectric material and in fact will tend to offer broader deposition possibilities. The deposition of the dielectric material may occur by spraying, sputtering, spreading, jetting or the like.
(96) Next, the process proceeds to block 714 which calls for planarization of the deposited material to yield an nth layer of the structure having desired net thickness. Planarization may occur in various manners including lapping and/or CMP.
(97) After completion of the layer by the operation of block 714, the process proceeds to decision block 716. This decision block inquires as to whether the nth layer (i.e. the current layer is the last layer of the structure (i.e. the Nth layer), if so the process moves to block 720 and ends, but if not, the process moves to block 718.
(98) Block 718 increments the value of n, after which the process loops back to block 704 which again inquires as to whether or not the substrate (i.e. the previous substrate with the addition of the just formed layer) is sufficiently conductive.
(99) The process continues to loop through blocks 704-718 until the formation of the Nth layer is completed.
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(104) Various alternatives to the embodiment of
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(106) The process starts with block 802 where a current layer number is set to one (n=1). The process then moves to decision block 804 where the inquiry is made as to whether the surface of the substrate is entirely or at least sufficiently conductive. If the answer to this inquiry is yes the process moves forward to block 808. On the other hand if the answer is no, the process moves to block 806 which calls for the application of a seed layer of a conductive material on to the substrate. The process then loops to decision block 808.
(107) In block 808, the inquiry is made as to whether or not a first conductive material will be deposited on the nth layer (i.e. on the current layer). If the answer to this inquiry is no the process moves forward to block 812. On the other hand if the answer is yes, the process moves to block 810 which calls for the selective deposition of the first conductive material. The process then loops to decision block 812.
(108) In block 812, the inquiry is made as to whether or not a second conductive material will be deposited on the nth layer (i.e. on the current layer). If the answer to this inquiry is no the process moves forward to block 816. On the other hand if the answer is yes, the process moves to block 814 which calls for the deposition of the second conductive material (which may be done selectively or in bulk). The process then loops to decision block 816.
(109) In block 816, the inquiry is made as to whether or not a third conductive material will be deposited on the nth layer (i.e. on the current layer). If the answer to this inquiry is no the process moves forward to block 828. On the other hand if the answer is yes, the process moves to decision block 818.
(110) In block 818 the inquiry is made as to whether or not a second conductive material was deposited on the nth layer (i.e. on the current layer). If the answer to this inquiry is no the process moves forward to block 826. On the other hand if the answer is yes, the process moves to block 822 which calls for the planarization of the partially formed layer at a desired level which may cause an interim thickness of the layer to be slightly more than the ultimate desired layer thickness for the final layer. The process then moves to block 824 which calls for selectively etching into the deposited material(s) to form one or more voids into which the third material will be deposited. The process then completes the loop to block 826.
(111) Block 826 calls for the deposition of the third conductive material. The deposition of the third conductive material may occur selectively or in bulk. The process then loops to block 828.
(112) Block 828 calls for planarization of the deposited materials to obtain a final smoothed nth layer of desired thickness.
(113) After completion of the formation of the nth layer by the operation of block 828, the process proceeds to decision block 830. This decision block inquires as to whether the nth layer (i.e. the current layer) is the last layer of the structure (i.e. the Nth layer), if so the process moves to block 834 and ends, but if not, the process loops to block 832.
(114) Block 832 increments the value of n, after which the process loops back to block 808 which again inquires as to whether or not a first conductive material is to be deposited on the nth layer. The process then continues to loop through blocks 808-832 until the formation of the Nth layer is completed.
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(123) In alternative embodiments, the processes of
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(125) The process of
(126) In blocks 906 and 908, the same inquiry is made as to whether a first conductive material (FCM) will be deposited on the nth layer (i.e. the first layer). If the answer to the inquiry of block 906 is yes, the process proceeds to block 914 and if it is no, the process proceeds to block 916. If the answer to the inquiry of block 908 is yes, the process proceeds to block 910 and if it is no, the process proceeds to block 916.
(127) Block 910 calls for application of a primary seed layer (PSL) of a conductive material on to the substrate. This seed layer may be applied in a variety of ways some of which have been discussed previously herein. From Block 910 the process proceeds to block 912 where the primary seed layer parameter is set to one, PSLP=1, which indicates that a primary seed layer has been deposited on the current layer.
(128) From block 912 and from a yes answer from block 906 the process proceeds to block 914 which calls for the selectively deposition of the FCM. In some alternatives, the preferential deposition is via a CC mask. From block 914, from a no answer in block 908, and from a no answer in block 906 the process proceeds to decision block 916.
(129) In decision block 916 an inquiry is made as to whether a second conductive material (SCM) will be deposited on the nth layer (i.e. the first layer in this case). If the answer to the inquiry of block 916 is yes, the process proceeds to block 924 and if it is no, the process proceeds to block 918.
(130) In blocks 924 and 918, the same inquiry is made as to whether a primary seed layer has been deposited on the first layer (i.e. Does PSLP=1?). If the answer to the inquiry of block 924 is yes, the process proceeds to block 926 and if it is no, the process proceeds to block 934. If the answer to the inquiry of block 918 is yes, the process proceeds to block 922 and if it is no, the process proceeds to block 966.
(131) In decision block 926 an inquiry is made as to whether the existence of the PSL is compatible with an SCM that will be deposited. If the answer to the inquiry of block 924 is yes, the process proceeds to block 928 and if it is no, the process proceeds to block 932.
(132) Blocks 932 and 922 call for the removal of any portion of the PSL that is not covered by the FCM. From block 932 the process proceeds to block 934, as did a no response in block 924, and from block 922 the process proceeds to block 966. In decision block 934 an inquiry is made as to whether the surface of the substrate is entirely or sufficiently conductive. Though this question was asked previously, the answer may have changed due to a different pattern of conductive material to be deposited or due to the removal of a previously supplied seed layer because it is incompatible with the second conductive material that is to be deposited. If the answer to the inquiry of block 934 is yes, the process proceeds to block 928 and if it is no, the process proceeds to block 936.
(133) Block 936 calls for application of a secondary seed layer (SSL) which will allow a second conductive material to be deposited in a subsequent operation. After which the process proceeds to block 938 where SSLP is set to one, thereby indicating that the present layer received the secondary seed layer which information will be useful in subsequent operations.
(134) Block 928 is reached by a yes response to either of block 926 or 934, or via block 938. Block 928 calls for the deposition of the second conductive material (SCM). This deposition operation may be a selective operation or a blanket operation.
(135) From block 928 the process proceeds to decision block 942 where an inquiry is made as to whether a dielectric will be deposited on the nth layer (i.e. the first layer). If the answer to the inquiry of block 942 is yes, the process proceeds to block 944 and if it is no, the process proceeds to block 968.
(136) Block 944 calls for planarizing the deposited materials to obtain a partially formed nth layer having a desired thickness which may be different from the final thickness of the layer. After planarization the process proceeds to block 946 which calls for the selectively etching into one or both of the deposited conductive materials to form one or more voids into which the dielectric may be located after which the process proceeds to block 948. If the answer to the inquiry of block 948 is yes, the process proceeds to block 952 and if it is no, the process proceeds to block 956.
(137) Decision block 952 inquires as whether the etching of block 946 resulted in the removal of all exposed SSL? If the answer to the inquiry of block 952 is yes, the process proceeds to block 956 and if it is no, the process proceeds to block 954.
(138) Block 954 calls for the removal of the portion of the SSL that is exposed by the voids formed in block 946. After the operation of block 954, the process proceeds to decision block 956.
(139) Decision block 956 inquires as whether PSLP is equal to one. If the answer to the inquiry of block 956 is yes, the process proceeds to decision block 962 and if it is no, the process proceeds to block 966.
(140) Decision block 962 inquires as to whether the etching of the SCM removed all the exposed PSL. If the answer to the inquiry of block 956 is yes, the process proceeds to decision block 966 and if it is no, the process proceeds to block 964.
(141) Block 964 calls for the removal of the portion of the PSL that is exposed by the voids created in block 946. After the operation of block 964 the process proceeds to block 966.
(142) Block 966 calls for the deposition of the dielectric material. The deposition process may be selective or of a blanket nature and various processes are possible some of which were discussed elsewhere herein.
(143) Block 968 calls for planarization of the deposited materials to obtain a final smoothed nth layer of desired thickness.
(144) After completion of the formation of the nth layer by the operation of block 968, the process proceeds to decision block 970 where PSLP and SSLP are both set to zero, after which the process proceeds to decision block 972. This decision block inquires as to whether the nth layer (i.e. the current layer) is the last layer of the structure (i.e. the Nth layer), if so the process moves to block 978 and ends, but if not, the process proceeds to block 974.
(145) Block 974 increments the value of n, after which the process loops back to block 904 which again inquires as to whether or not surface of the substrate (i.e. the substrate surface as modified by the formation of the immediately preceding layer) is sufficiently conductive. The process then continues to loop through blocks 904-974 until the formation of the Nth layer is completed.
(146) As with the processes of
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(149) TABLE-US-00007 TABLE 6 FIGS. 25 FIGS. 26 Layers L Operation Comments 25A, C, E, I, P, V 1, 2, 3, 4, 6, 7 914 The 1.sup.st material 992 is deposited 26C 25B, D, F, X 1, 2, 6, 7 936 & 968 The 2.sup.nd material 994 is deposited and 26F planarized to complete formation of the layer 25F, K, R 3, 4, 6 928 & 944 The 2.sup.nd material 994 is deposited and -- planarized to form an incomplete layer 25G, L, S 3, 4, 6 946 The deposited material is etched to form -- voids 990 25H, N U 3, 4, 6 966 & 968 The 3.sup.rd material 996 is deposited and -- planarized to complete formation of the layer 25J, Q, W 4, 6, 7 936 A secondary seed layer 1000 is applied 26E -- A primary seed layer 998 is applied 26B 25M, T 4, 6 Exposed portions of the secondary seed -- layer are removed --- Exposed portions of the primary seed layer 26D are removed (o) 5 All operations performed for layer 4 --
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(158) In other embodiments, the inductors of
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(162) In still further embodiments, resistive losses associated with current carrying conductors such as the spacers of
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(165) In some embodiments, it is possible to build a number of similar components on a single substrate where the multiple components may be used together on the substrate or they may be diced from one another and applied to separate secondary substrates as separate components for use on different circuit/component boards. In other embodiments the electrochemical processes of various embodiments set forth herein may be used in a generic way to form various distinct components simultaneously on a single substrate where the components may be formed in their final positions and with many if not all of their desired interconnections. In some embodiments single or multiple identical or distinct components may be formed directly onto integrated control circuits or other substrates that include premounted components. In some embodiments, it may be possible to form entire systems from a plurality of monolithically formed and positioned components.
(166) In still further embodiments, the devices or groups of devices may be formed along with structures that may be used for packaging the components. Such packaging structures are set forth in U.S. Patent Application No. 60/379,182 which is described in the table of patent application set forth hereafter. This incorporated application teaches several techniques for forming structures and hermetically sealable packages. Structures may be formed with holes that allow removal of a sacrificial material. After removal of the sacrificial material, the holes may be filled in a variety of ways. For example, adjacent to or in proximity to the holes a meltable material may be located which may be made to flow and seal the holes and then resolidify. In other embodiments the holes may be plugged by locating a plugging material in proximity to but spaced from the openings and after removal of sacrificial material then causing the plugging material to bridge the gaps associated with the holes and seal them either via a solder like material or other adhesive type material. In still other embodiments, it may be possible to perform a deposition to fill the holes, particularly if such a deposition is essentially a straight line deposition process and if underneath the holes a structural element is located that can act as a deposition stop and build up point from which the deposit can build up to plug the holes.
(167) Though the application has focused the bulk of its teachings on coaxial transmission lines and coaxial filters, it should be understood that these structures may be used as fundamental building blocks of other structures. As such, RF and microwave components of various embodiments may include one or more of a microminiature coaxial component, a transmission line, a low pass filter, a high pass filter, a band pass filter, a reflection-based filter, an absorption-based filter, a leaky wall filter, a delay line, an impedance matching structure for connecting other functional components, one of a class of antennas, a directional coupler, a power combiner (e.g., Wilkinson), a power splitter, a hybrid combiner, a magic TEE, a frequency multiplexer, or a frequency demultiplexer. The antennas include pyramidal (i.e., smooth wall) and scalar (corrugated wall) feedhornscomponents that can efficiently transfer microwave power from the microminiature transmission line into free space. EFAB produced microminiature coax will also enable new components with multiple functionalities. The combination of power combining (or splitting) and frequency multiplexing (or demultiplexing) could readily be combined in a single microminiature-coax structure having multiple input and output ports.
(168) Other embodiments of the present invention may involve the formation and use of waveguides and waveguide components. Some embodiments may involve the formation of discrete components that may be combined manually or automatically while may involve the formation of entire systems such as signal distribution networks and the like.
(169) The patent applications in the following table are hereby incorporated by reference herein as if set forth in full. The gist of each patent application is included in the table to aid the reader in finding specific types of teachings. It is not intended that the incorporation of subject matter be limited to those topics specifically indicated, but instead the incorporation is to include all subject matter found in these applications. The teachings in these incorporated applications can be combined with the teachings of the instant application in many ways. For example, the various apparatus configurations disclosed in these referenced applications may be used in conjunction with the novel features of the instant invention to provide various alternative apparatus that include the functionality disclosed herein:
(170) TABLE-US-00008 U.S. patent application No., Filing Date U.S. application Pub No., Pub Date Inventor, Title 09/493,496 - Jan. 28, 2000 Cohen, Method For Electrochemical Fabrication U.S. Pat. No. 6,790,377 - Sep. 14, 2004 10/677,556 - Oct. 1, 2003 Cohen, Monolithic Structures Including Alignment and/or 2004-0134772 - Jul. 15, 2004 Retention Fixtures for Accepting Components 10/830,262 - Apr. 21, 2004 Cohen, Methods of Reducing Interlayer Discontinuities in 2004-0251142A - Dec. 16, 2004 Electrochemically Fabricated Three-Dimensional Structures U.S. Pat. No. 7,198,704 - Apr. 3, 2007 10/271,574 - Oct. 15, 2002 Cohen, Methods of and Apparatus for Making High Aspect 2003-0127336A - Jul. 10, 2003 Ratio Microelectromechanical Structures U.S. Pat. No. 7,288,178 - Oct. 30, 2007 10/697,597 - Dec. 20, 2002 Lockard, EFAB Methods and Apparatus Including Spray 2004-0146650A - Jul. 29, 2004 Metal or Powder Coating Processes 10/677,498 - Oct. 1, 2003 Cohen, Multi-cell Masks and Methods and Apparatus for 2004-0134788 - Jul. 15, 2004 Using Such Masks To Form Three-Dimensional Structures U.S. Pat. No. 7,235,166 - Jun. 26, 2007 10/724,513 - Nov. 26, 2003 Cohen, Non-Conformable Masks and Methods and 2004-0147124 - Jul. 29, 2004 Apparatus for Forming Three-Dimensional Structures U.S. Pat. No. 7,368,044 - May 6, 2008 10/607,931 - Jun. 27, 2003 Brown, Miniature RF and Microwave Components and 2004-0140862 - Jul. 22, 2004 Methods for Fabricating Such Components U.S. Pat. No. 7,239,219 - Jul. 3, 2007 10/841,100 - May 7, 2004 Cohen, Electrochemical Fabrication Methods Including Use 2005-0032362 - Feb. 10, 2005 of Surface Treatments to Reduce Overplating and/or U.S. Pat. No. 7,109,118 - Sep. 19, 2006 Planarization During Formation of Multi-layer Three- Dimensional Structures 10/387,958 - Mar. 13, 2003 Cohen, Electrochemical Fabrication Method and 2003-022168A - Dec. 4, 2003 Application for Producing Three-Dimensional Structures Having Improved Surface Finish 10/434,494 - May 7, 2003 Zhang, Methods and Apparatus for Monitoring Deposition 2004-0000489A - Jan. 1, 2004 Quality During Conformable Contact Mask Plating Operations 10/434,289 - May 7, 2003 Zhang, Conformable Contact Masking Methods and 20040065555A - Apr. 8, 2004 Apparatus Utilizing In Situ Cathodic Activation of a Substrate 10/434,294 - May 7, 2003 Zhang, Electrochemical Fabrication Methods With 2004-0065550A - Apr. 8, 2004 Enhanced Post Deposition Processing 10/434,295 - May 7, 2003 Cohen, Method of and Apparatus for Forming Three- 2004-0004001A - Jan. 8, 2004 Dimensional Structures Integral With Semiconductor Based Circuitry 10/434,315 - May 7, 2003 Bang, Methods of and Apparatus for Molding Structures 2003-0234179 A - Dec. 25, 2003 Using Sacrificial Metal Patterns U.S. Pat. No. 7,229,542 - Jun. 12, 2007 10/434,103 - May 7, 2004 Cohen, Electrochemically Fabricated Hermetically Sealed 2004-0020782A - Feb. 5, 2004 Microstructures and Methods of and Apparatus for U.S. Pat. No. 7,160,429 - Jan. 9, 2007 Producing Such Structures 10/841,006 - May 7, 2004 Thompson, Electrochemically Fabricated Structures Having 2005-0067292 - May 31, 2005 Dielectric or Active Bases and Methods of and Apparatus for Producing Such Structures 10/434,519 - May 7, 2003 Smalley, Methods of and Apparatus for Electrochemically 2004-0007470A - Jan. 15, 2004 Fabricating Structures Via Interlaced Layers or Via Selective U.S. Pat. No. 7,252,861 - Aug. 7, 2007 Etching and Filling of Voids 10/724,515 - Nov. 26, 2003 Cohen, Method for Electrochemically Forming Structures 2004-0182716 - Sep. 23, 2004 Including Non-Parallel Mating of Contact Masks and U.S. Pat. No. 7,291,254 - Nov. 6, 2007 Substrates 10/841,347 - May 7, 2004 Cohen, Multi-step Release Method for Electrochemically 2005-0072681 - Apr. 7, 2005 Fabricated Structures 60/533,947 - Dec. 31, 2003 Kumar, Probe Arrays and Method for Making 10/841,300 - May 7, 2004 Cohen, Methods for Electrochemically Fabricating 2005 0032375 - Feb. 10, 2005 Structures Using Adhered Masks, Incorporating Dielectric Sheets, and/or Seed layers That Are Partially Removed Via Planarization 60/534,183 - Dec. 31, 2003 Cohen, Method and Apparatus for Maintaining Parallelism of Layers and/or Achieving Desired Thicknesses of Layers During the Electrochemical Fabrication of Structures 11/733,195 - Apr. 9, 2007 Kumar, Methods of Forming Three-Dimensional Structures 2008-0050524 - Feb. 28, 2008 Having Reduced Stress and/or Curvature 11/506,586 - Aug. 8, 2006 Cohen, Mesoscale and Microscale Device Fabrication 2007-0039828 - Feb. 22, 2007 Methods Using Split Structures and Alignment Elements U.S. Pat. No. 7,611,616 - Nov. 3, 2009 10/949,744 - Sep. 24, 2004 Lockard, Three-Dimensional Structures Having Feature 2005-0126916 - Jun. 16, 2005 Sizes Smaller Than a Minimum Feature Size and Methods U.S. Pat. No. 7,498,714 - Mar. 3, 2009 for Fabricating
(171) Various other embodiments of the present invention exist. Some of these embodiments may be based on a combination of the teachings herein with various teachings incorporated herein by reference. Some embodiments may not use any blanket deposition process and/or they may not use a planarization process. Some embodiments may involve the selective deposition of a plurality of different materials on a single layer or on different layers. Some embodiments may use blanket deposition processes that are not electrodeposition processes. Some embodiments may use selective deposition processes on some layers that are not conformable contact masking processes and are not even electrodeposition processes. Some embodiments may use the non-conformable contact mask or non-contact masking techniques set forth in the above referenced US Provisional Application corresponding to P-US042-B-MG.
(172) Some embodiments may use nickel as a structural material while other embodiments may use different materials such as copper, gold, silver, or any other electrodepositable materials that can be separated from the a sacrificial material. Some embodiments may use copper as the structural material with or without a sacrificial material. Some embodiments may remove a sacrificial material while other embodiments may not. In some embodiments the sacrificial material may be removed by a chemical etching operation, an electrochemical operation, or a melting operation. In some embodiments the anode may be different from the conformable contact mask support and the support may be a porous structure or other perforated structure. Some embodiments may use multiple conformable contact masks with different patterns so as to deposit different selective patterns of material on different layers and/or on different portions of a single layer. In some embodiments, the depth of deposition will be enhanced by pulling the conformable contact mask away from the substrate as deposition is occurring in a manner that allows the seal between the conformable portion of the CC mask and the substrate to shift from the face of the conformal material to the inside edges of the conformable material.
(173) In view of the teachings herein, many further embodiments, alternatives in design and uses of the instant invention will be apparent to those of skill in the art. As such, it is not intended that the invention be limited to the particular illustrative embodiments, alternatives, and uses described above but instead that it be solely limited by the claims presented hereafter.