Method for forming a circuit board via structure for high speed signaling

Abstract

One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the PCB, and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.

Claims

1. A method for forming a via, comprising: forming a second conductive cylinder within a first conductive cylinder in a circuit board, wherein the first conductive cylinder is coupled to a first conductive layer in the circuit board, wherein the second conductive cylinder is coupled to a second conductive layer in the circuit board, wherein the first and second conductive layers are spaced from one another at a spaced distance, and wherein the first cylinder and the second cylinder extend respectively from the first and second conductive layers toward the other conductive layer, and neither extends for the entire spaced distance between the first and second conductive layers; forming a first dielectric layer on the first conductive layer, and a second dielectric layer on the second conductive layer; forming a third conductive layer on the first dielectric layer, and a fourth conductive layer on the second dielectric layer; and forming a via within the second conductive cylinder, wherein the via is coupled to the third and fourth conductive layers.

2. The method of claim 1, wherein the first conductive layer is coupled to one of a power supply voltage or a ground voltage, and wherein the second conductive layer is coupled to the other of the power supply voltage or the ground voltage.

3. The method of claim 1, wherein the first, second, third and fourth conductive layers are parallel.

4. The method of claim 3, wherein the first and second conductive layers are between the third and fourth conductive layers.

5. The method of claim 1, wherein the first and second conductive cylinders are separated by a dielectric.

6. The method of claim 1, wherein the first and second conductive cylinders are concentric with the via.

7. The method of claim 1, wherein power and ground planes are coupled to the first and second conductive cylinders to form a power cylinder and a ground cylinder.

8. The method of claim 7, wherein the power cylinder is formed within the ground cylinder.

9. The method of claim 7, wherein the ground cylinder is formed within the power cylinder.

10. The method of claim 7, wherein forming the via comprises forming the via with a mechanical or laser drill.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the inventive aspects of this disclosure will be best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which:

(2) FIG. 1A illustrates a perspective view of two prior art vias both switching signal planes through power and ground planes.

(3) FIG. 1B illustrates a cross section of one of the vias of FIG. 1A.

(4) FIG. 2 illustrates signal loss (via S-parameters) as a function of frequency for both the prior art via of FIG. 1B and the disclosed via of FIG. 4.

(5) FIG. 3 illustrates via coupling (in dB) as a function of frequency for both the prior art via of FIG. 1B and the disclosed via of FIG. 4.

(6) FIG. 4 illustrates a cross section of the disclosed improved via structure.

(7) FIGS. 5A-5N illustrate sequential steps for the construction of the via of FIG. 4.

DETAILED DESCRIPTION

(8) FIG. 4 shows an improved via structure 50 which alleviates the problem of signals switching signal planes through power planes. As shown, and similar to FIG. 1B, a signal 60 switches from the top (60t) to the bottom (60b) of the PCB 66 through via 60. Also similarly to FIG. 1B, power and ground planes 62 and 64 are present. However, in distinction to FIG. 1B, the power and ground planes 62 and 64 are coupled to concentric cylinders 62a and 64a (i.e., shields) around the via 60. Through this configuration, the cylinders 62a, 64a substantially encompasses the via in directions perpendicular to its axis 61, such that the cylinders are positioned in a dielectric perpendicularly to the plane of the PCB 66.

(9) This via structure 50 facilitates signal transitioning from one plane to another by reducing the disturbances cause by return path discontinuities, particularly at high frequencies. Moreover, the via structure 50 suppresses via-to-via coupling otherwise caused by resonance between the ground and power planes 62, 64 at high frequencies, thereby improving signal integrity and reducing cross-talk from aggressor signals. The approach provides more efficient via shielding than the use of shielding vias, discussed in the background. Moreover, the disclosed approach performs better at high frequency than do approaches using decoupling capacitors, which otherwise suffer from relatively high effective series inductances that exist in decoupling capacitors, again as discussed in the background. As compared to prior art seeking to minimize the impedance discontinuity caused by the via, also discussed in the background, the disclosed approach is more flexible and realistic. In that prior art approach, both of the planes transgressed must be held at the same potential (i.e., ground or power). In short, that prior technique has no pertinence when signals have to change through both power and ground planes, as that technique would require shorting those planes together, which is not possible in a real working PCB. In short, it provides no solution for the problem addressed here of switching through power and ground planes. In short, the disclosed via structure has improved applicability to high-speed/high-frequency PCB designs, where signals have reduced timing and noise margins and increased energies.

(10) The improved performance is shown in FIGS. 2 and 3, which as discussed previously shows computer simulation results indicative of the magnitude of the EM disturbance caused by signal plane switching and cross-talk. Thus, referring again to FIG. 2, it is seen that the disclosed via structure 50 has an improved transmission coefficient (i.e., S-parameter), and does not generally suffer large dips in the transmission coefficient resulting from unwanted resonance in the cavity between the power planes. Moreover, and referring again to FIG. 3, it can be seen that cross-talk is greatly minimized, especially at higher frequencies. As modeled, the core via of FIG. 4 had the same core dimensions and materials of the via of FIG. 1 as discussed in the background, and had the following additional parameters: an inner power diameter 56 of 20 mils; an inner ground diameter 58 of 23 mils; cylinder wall thicknesses of 2 mils; a 1 mil dielectric thickness 57 between the cylinders; and a 3 mil vertical distance 55 between the top of the power cylinder 64a and the ground plane 62. (As such, it should be understood that the cross section of FIG. 4 is not drawn to scale). Of course, these values for the improved via structure 50 are merely exemplary, and can be changed depending on the environment in which the vias will operate. For example, the core via 60 can be made of a smaller diameter, and the cylinders 62a, 64a can be further spaced from core via 60.

(11) As shown in FIG. 4, it is preferable to place the power and ground cylinders 62a, 64a as close as together to maximize the coupling between them. Preferably, the dielectric thickness 57 between the cylinders would not exceed 3 mils for the materials discussed herein.

(12) Although the via structure 50 is shown in FIG. 4 with the power cylinder 62a within the ground cylinder 64a, it should be understood that the cylinders can be reversed with the same effect, i.e., with the ground cylinder 64a within the power cylinder 62a.

(13) Manufacture of the disclosed via structure 50 can take place as illustrated in the sequential cross-sectional views of FIG. 5A-5N. Most of the individual steps involve common techniques well known in the PCB arts, and so are only briefly discussed. Further information on such steps are disclosed in PCB/Overview (Apr. 11, 2004), which is published at www.ul.ie/rinne/ee6471/ee6471%20wk11.pdf, which is incorporated herein by reference in its entirety, and which is submitted with the Information Disclosure Statement filed with this application.

(14) Starting with FIG. 5A, the starting substrate comprises a dielectric layer 66 which has been coated on both sides with a conductive material 62, 64, which comprises the power and ground planes. In a preferred embodiment, dielectric 66 is FR4, but could comprise any dielectric useable in a PCB. The conductive materials 62, 64 can also comprise standard PCB conductive materials.

(15) In FIG. 5B, a hole 70 that will eventually encompass the cylinders is formed. Such a hole 70 can be formed by mechanical or laser drilling. Note that the hole 70 does not proceed through the entirety of the dielectric 66, but instead leaves a thickness akin to the thickness 55 (FIG. 4) in the finished via.

(16) In FIG. 5C, the resulting structure is electrically plated to form line 71 the hole 70. Processes for electrical plating are well known in the art, and hence are not further discussed. Note that through this process the plating 71 couples to the ground plane 64. In FIG. 5D, the horizontal portion of the plating 71 is removed, which can occur using plasmas or wet chemical etchants. In this regard, it may be useful to employ a removable masking layer (not shown) over conductors 62, 64 to protect them against the etch step of FIG. 5D, which would then allow an anisotropic plasma etch to be used to remove only the horizontal portion of the plating 71. The resulting structure defines the outer cylinder 64a.

(17) In FIG. 5E, the hole 70 is filled with another dielectric material 72. This dielectric material can be deposited either by chemical vapor deposition, or spun on to the substrate in liquid form and then hardened. Either way, the bottom side of the substrate might need to be planarized to remove unwanted portions of the dielectric material 72 from the surface of the ground plane 64.

(18) FIGS. 5F-5I essentially mimic the steps of FIGS. 5B-5E (drilling, plating, etching, and dielectric filling), but occur on the top of the substrate and are relevant to the formation of the inner cylinder (i.e., 62a). As these steps are the same, they are not again discussed.

(19) In FIG. 5J, sheets of a dielectric prepreg material 78 are adhered to the top and bottom of the substrate. The prepreg sheets 78 are heated and hardened to adhere them to the remaining substrate, which can occur in a hydraulic press. Once adhered, the prepreg forms the dielectric between the power planes/associated cylinders and the signal traces, as will become evident in the following Figures.

(20) In FIG. 5K, a conductive material 80 for the signal traces is formed on both the top and bottom of the substrate. Again, plating and/or chemical vapor deposition can be used to form the conductive material 80.

(21) In FIG. 5L, a hole 82 for the via is formed. Such hole may be mechanically drilled or formed by laser drilling.

(22) In FIG. 5M, another conductive material 84 is placed on the sides of the hole 84 to form via 80, e.g., by plating and/or chemical vapor deposition. In so doing, the conductive material 84 contacts the top and bottom conductive material 80 deposited in FIG. 5K.

(23) In FIG. 5N, the conductive material 80 is masked and etched using standard PCB techniques to form the necessary conductors on the top and bottom of the substrate. In particular, and as shown, top and bottom conductors 80t, 80b are formed, thus forming, in conjunction with the via 80, a signal which switches signal planes through the power planes, i.e., the problematic configuration discussed above. However, the dual-shield configuration minimizes the effects of EM disturbance.

(24) The disclosed via structure 50 is susceptible to modifications. It is preferable that the shields 62a, 64a are circular and concentric, as this geometry is easiest to manufacture. However, useful embodiments of the invention need not be either circular or concentric. For example, the shields 62a, 64a can take the form of squares, rectangles, ovals, etc., and additionally need not be perfectly concentric to achieve improved performance. The dielectric material (72; FIG. 5E) between the cylinders 62a, 64a need not be FR4, but could comprise other high dielectric constant materials other than those mentioned. Finally, the number of shields can be increased. Thus, there could be three shields (e.g., with a ground shield nested between two power shields or vice versa), four shield (with alternating power and ground shields), or more.

(25) Although particularly useful in the context of a printed circuit board, the disclosed technique could also be adapted to the formation of shielded vias for integrated circuits.

(26) In short, it should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.