SIC EPITAXIAL WAFER, MANUFACTURING APPARATUS OF A SIC EPITAXIAL WAFER, FABRICATION METHOD OF A SIC EPITAXIAL WAFER, AND SEMICONDUCTOR DEVICE

Abstract

The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.

Claims

1. A silicon carbide epitaxial wafer comprising: a substrate; and an SiC epitaxial growth layer disposed on the substrate, wherein a surface-roughness defect density including particles on a surface of the SiC epitaxial growth layer is less than 1.0 cm.sup.2.

2. The silicon carbide epitaxial wafer according to claim 1, wherein the surface-roughness defect density is less than approximately 0.07 cm.sup.2.

3. The silicon carbide epitaxial wafer according to claim 1, wherein an off angle of the SiC epitaxial wafer is equal to or less than 4 degrees.

4. The silicon carbide epitaxial wafer according to claim 1, wherein the SiC epitaxial growth layer comprises one selected from the group consisting of 4HSiC, 6HSiC, 2HSiC and 3SiC.

5. The silicon carbide epitaxial wafer according to claim 1, wherein the substrate comprises one selected from the group consisting of 4HSiC, 6HSiC, BN, AlN, Al.sub.2O.sub.3, Ga.sub.2O.sub.3, diamond, carbon, and graphite.

6. A fabrication method of a silicon carbide epitaxial wafer comprising: preparing an SiC ingot, cutting the prepared SIC ingot with an off angle, and polishing the cut SiC ingot to form an SiC bare wafer; removing a cut surface of the SiC bare wafer to form an SiC substrate; and crystal-growing an SiC epitaxial growth layer on the SiC substrate, wherein a material gas to be supplied at the time of the epitaxial growth comprises an Si compound gas used as a supply source of Si, and Carbon (C) compound gas used as a supply source of C, wherein any one or both of the Si compound gas and the C compound gas comprises a compound gas containing Fluorine (F), wherein a surface-roughness defect density including particles on a surface of the SiC epitaxial growth layer is controlled to be less than 1.0 cm.sup.2.

7. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the Si compound comprises one selected from the group consisting of SiF.sub.4, SiH.sub.3F, SiH.sub.2F.sub.2, and SiHF.sub.3.

8. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the Si compound is expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2).

9. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the C compound comprises one selected from the group consisting of CF.sub.4, C.sub.2F.sub.6, C.sub.3F.sub.8, C.sub.4F.sub.6, C.sub.4F.sub.8, C.sub.5F.sub.5, CHF.sub.3, CH.sub.2F.sub.2, CH.sub.3F, and C.sub.2HF.sub.5.

10. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the C compound is expressed with C.sub.mH.sub.aCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

11. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the SiC epitaxial growth layer comprises one selected from the group consisting of 4HSiC, 6HSiC, 2HSiC and 3CSiC.

12. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein in a temperature profile of the crystal growth of the SiC epitaxial growth layer, a predetermined temperature of hydrogen etching immediately before depositing the SiC epitaxial growth layer is not the same as a predetermined temperature of depositing the SiC epitaxial growth layer.

13. The fabrication method of the silicon carbide epitaxial wafer according to claim 6, wherein the temperature profile of the crystal growth of the SiC epitaxial growth layer is controlled to be a hydrogen etching temperature in accordance with a hydrogen flow rate.

14. A manufacturing apparatus of a silicon carbide epitaxial wafer, the manufacturing apparatus comprising: a gas injection port; a gas exhaust port; a heating unit; and a reactor, wherein a material gas to be supplied at the time of the epitaxial growth comprises an Si compound gas used as a supply source of Si, and Carbon(C) compound gas used as a supply source of C, wherein any one or both of the Si compound gas and the C compound gas comprises a compound gas containing Fluorine(F), wherein the silicon carbide epitaxial wafer is formed so that a surface-roughness defect density including particles on a surface of the SiC epitaxial growth layer is less than 1.0 cm.sup.2.

15. The manufacturing apparatus of the silicon carbide epitaxial wafer according to claim 14, wherein the Si compound is expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

16. The manufacturing apparatus of the silicon carbide epitaxial wafer according to claim 14, wherein the reactor comprises a vertical-type reactor, wherein a plurality pieces of the SiC epitaxial wafers can be disposed so as to be parallel to the flow of the gas, in the vertical-type reactor.

17. The manufacturing apparatus of the silicon carbide epitaxial wafer according to claim 14, wherein the reactor comprises a horizontal-type reactor, wherein a plurality pieces of the SiC epitaxial wafers can be vertically arranged in an upward direction stand so as to be opposite to the flow of gas, in the horizontal-type reactor.

18. The manufacturing apparatus of the silicon carbide epitaxial wafer according to claim 14, wherein at least one of H.sub.2, Ar, HCl, and F.sub.2 is applicable as a carrier gas.

19. The manufacturing apparatus of a silicon carbide epitaxial wafer according to claim 14, wherein N.sub.2 or Trimethylaluminium is applicable as a material of dopant.

20. The manufacturing apparatus of the silicon carbide epitaxial wafer according to claim 14, wherein a temperature of the reactor can be control to be a hydrogen etching temperature in accordance with a hydrogen flow rate.

21. A semiconductor device comprising a silicon carbide epitaxial wafer, the semiconductor device comprising: a substrate; and an SiC epitaxial growth layer disposed on the substrate, wherein a surface-roughness defect density including particles on a surface of the SiC epitaxial growth layer is less than 1.0 cm.sup.2.

22. The semiconductor device according to claim 21, wherein the semiconductor device comprises: one selected from the group consisting of an SiC Schottky barrier diode, an SiC-MOSFET, an SiC bipolar junction transistor, an SiC diode, an SiC thyristor, and an SiC insulated gate bipolar transistor.

23. The semiconductor device according to claim 21, wherein an electrode is formed on a surface of the substrate, and a circuit element is formed on a front surface side of the SiC epitaxial growth layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a diagram for summarizing Si, C, N, and F bonding energies.

[0016] FIG. 2 is a diagram showing temperature dependencies of growth rates, in an Si epitaxial growth according to a comparative example.

[0017] FIG. 3 is a diagram for summarizing growth conditions, i.e., materials, growth rates, temperature ranges, and allowed oxidizers, in the Si epitaxial growth according to the comparative example.

[0018] FIG. 4 is a diagram showing temperature dependency of growth rates, in an SiC epitaxial growth of an SiC epitaxial wafer according to an embodiment.

[0019] FIG. 5 is a schematic bird's-eye view configuration diagram showing the SiC epitaxial wafer according to the embodiment.

[0020] FIG. 6A is a schematic bird's-eye view configuration diagram showing a unit cell of a 4HSiC crystal applicable to the SiC epitaxial wafer according to the embodiment.

[0021] FIG. 6B is a schematic configuration diagram showing a two layer portion of the 4HSiC crystal applicable to the SiC epitaxial wafer according to the embodiment.

[0022] FIG. 6C is a schematic configuration diagram showing the unit cell of the 4HSiC crystal applicable to an SiC epitaxial wafer according to the embodiment.

[0023] FIG. 7 is a schematic configuration diagram showing the unit cell of the 4HSiC crystal shown in FIG. 6A observed from directly above a (0001) surface.

[0024] FIG. 8A is a process chart of: preparing a hexagonal-crystal SiC ingot; cutting the SiC ingot with an off angle with respect to the (0001) surface; and then polishing the cut SIC ingot to form a plurality pieces of SiC bare wafers, in a schematic bird's-eye view structure diagram showing a fabrication method of the SiC epitaxial wafer according to the embodiment.

[0025] FIG. 8B is a process chart of removing the cut surfaces ((0001) surface) of the SiC bare wafer by equal to or greater than 500 nm, after a machining process, in the schematic bird's-eye view structure diagram showing the fabrication method of the SiC epitaxial wafer according to the embodiment.

[0026] FIG. 8C is a process chart of forming an oxide film on a principal surface of the SiC substrate by applying an oxidation treatment to the principal surface (0001) surface of the SiC substrate, in the schematic bird's-eye view structure diagram showing the fabrication method of the SiC epitaxial wafer according to the embodiment.

[0027] FIG. 8D is a process chart of forming an SiC epitaxial growth layer on the SiC substrate, in the schematic bird's-eye view structure diagram showing the fabrication method of the SiC epitaxial wafer according to the embodiment.

[0028] FIG. 9 shows an example of an epitaxial quality image of the SiC epitaxial wafer according to the embodiment, in a case where a surface-roughness defect density including particles on the wafer is approximately 0.07 cm.sup.2 (the number of defects is 12 (in a case of a wafer having a diameter of 150 mm)).

[0029] FIG. 10 shows an example of an epitaxial quality image of the SiC epitaxial wafer according to the comparative example in a case where a surface-roughness defect density including particles on the wafer is approximately 1 cm.sup.2 (the number of defects is 173 (in a case of a wafer having a diameter of 150 mm)).

[0030] FIG. 11 is a diagram showing a relationship between growth temperature and time (example 1 of chemical-vapor deposition (CVD) temperature profile), in the SiC epitaxial growth according to the embodiment.

[0031] FIG. 12 is a diagram showing a relationship between growth temperature and time (example 2 of CVD temperature profile), in the SiC epitaxial growth according to the embodiment.

[0032] FIG. 13 is a diagram showing a relationship between growth temperature and time (example 3 of CVD temperature profile), in the SiC epitaxial growth according to the embodiment.

[0033] FIG. 14 is a schematic configuration diagram showing a first manufacturing apparatus applicable to the SiCepitaxial growth according to the embodiment.

[0034] FIG. 15 is a schematic configuration diagram showing a second manufacturing apparatus applicable to the SiC epitaxial growth according to the embodiment.

[0035] FIG. 16 is a schematic configuration diagram showing a third manufacturing apparatus applicable to the SiC epitaxial growth according to the embodiment.

[0036] FIG. 17 is a schematic configuration diagram showing a fourth manufacturing apparatus applicable to the SIC epitaxial growth according to the embodiment.

[0037] FIG. 18 is a schematic cross-sectional structure diagram showing a Schottky barrier diode fabricated with the SiC epitaxial wafer according to the embodiment.

[0038] FIG. 19 is a schematic cross-sectional structure diagram showing a trench-gate type MOSFET fabricated with the SiC epitaxial wafer according to the embodiment.

[0039] FIG. 20 is a schematic cross-sectional structure diagram showing a planar-gate type MOSFET fabricated with the SiC epitaxial wafer according to the embodiment.

DESCRIPTION OF EMBODIMENTS

[0040] Next, the embodiment will be described with reference to drawings. In the description of the following drawings, the identical or similar reference numeral is attached to the identical or similar part. However, it should be noted that the drawings are schematic and therefore the relation between thickness and the plane size and the ratio of the thickness differs from an actual thing. Therefore, detailed thickness and size should be determined in consideration of the following explanation. Of course, the part from which the relation and ratio of a mutual size differ also in mutually drawings is included.

[0041] Moreover, the embodiment shown hereinafter exemplifies the apparatus and method for materializing the technical idea; and the embodiment does not specify the material, shape, structure, placement, etc. of each component part as the following. The embodiment may be changed without departing from the spirit or scope of claims.

Comparative Example

[0042] FIG. 2 shows temperature dependencies of growth rates, in an Si epitaxial growth according to a comparative example. In FIG. 2, the dashed line SL indicates a boundary between a Diffusion Control region DC and a Kinetic Control region KC in the Si epitaxial growth.

[0043] FIG. 3 shows growth conditions, i.e., materials, growth rates, temperature ranges, and allowed oxidizers, in the Si epitaxial growth according to the comparative example. In this case, the oxidizer is vapor etc. which is supplied from a reactor or a susceptor, and is necessary to be reduced to equal to or less than an allowed amount.

[0044] In the Si epitaxial growth according to the comparative example, SiN.sub.4, SiHCl.sub.3, SiH.sub.2Cl.sub.2, SiCl.sub.4, etc. are applied as supply sources of Si used as materials.

[0045] In the Si epitaxial growth according to the comparative example: the growth rate is 0.4 to 1.5 (m/min) and the growth temperature is 1150 degrees C (Celsius) to 1250 degrees C. when using SiCl.sub.4; the growth rate is 0.4 to 3.0 (m/min) and the growth temperature is 1100 degrees C. to 1200 degrees C. when using SiHCl.sub.3; the growth rate is 0.3 to 2.0 (m/min) and the growth temperature is 1050 degrees C. to 1150 degrees C. when using SiH.sub.2Cl.sub.2; and the growth rate is 0.1 to 0.3 (m/min) and the growth temperature is 950 degrees C. to 1050 degrees C. when using SiH.sub.4.

[0046] Si, C, N, F, and Cl bonding energies D (kJ/mol) are respectively and generally expressed, as shown in FIG. 1. For example, SiSi bonding energy is 222 (kJ/mol). On the other hand, SiC bonding energy is 318 (kJ/mol), SiN bonding energy is 355 (kJ/mol), SiCl bond energy is 381 (kJ/mol), and SiF bonding energy is 565 (kJ/mol).

[0047] Moreover, CN bonding energy is 305 (kJ/mol), CSi bonding energy is 318 (kJ/mol), CC bonding energy is 346 (kJ/mol), CH bonding energy is 411 (kJ/mol), CF bonding energy is 485 (kJ/mol), CC bonding energy is 602 (kJ/mol), and CC bond energy is 835 (kJ/mol).

[0048] Moreover, NN bonding energy is 167 (kJ/mol), NF bonding energy is 283 (kJ/mol), NC bonding energy is 305 (kJ/mol), NCl bonding energy is 313 (kJ/mol), NSi bonding energy is 355 (kJ/mol), NH bonding energy is 386 (kJ/mol), NN bonding energy is 418 (kJ/mol), and NN bonding energy is 942 (kJ/mol).

[0049] On the other hand, FF bonding energy is 155 (kJ/mol), ClCl bonding energy is 240 (kJ/mol), FN bonding energy is 283 (kJ/mol), ClN bonding energy is 305 (kJ/mol), ClN bonding energy is 313 (kJ/mol), ClC bonding energy is 327 (kJ/mol), ClSi bonding energy is 381 (kJ/mol), FC bonding energy is 485 (kJ/mol), FC bonding energy is 485 (kJ/mol), FH bonding energy is 565 (kJ/mol), and FSi bonding energy is 565 (kJ/mol).

[0050] In this case, if it is assumed that the SiC epitaxial growth temperature is approximately 1600 degrees C., for example, the SiH bond dissociates more excessively than the SiCl bond at the SiC epitaxial growth temperature since the SiH bonding energy is lower than the SiCl bonding energy. As a result of the SiH bond excessively dissociates, it reacts in a vapor phase before materials are reached to a substrate for epitaxial growth, thereby generating particles. Consequently, since the generated particles generate defects, e.g. particles, downfall, and triangular defects, on the epitaxial wafer surface, a region which can be used as a device is limited as a result, thereby reducing the quality of the epitaxial wafers.

[0051] Although dissociation temperature using the SiCl bond becomes higher than that of the SiH bond, the SiCl bond will also excessively dissociate at the SiC epitaxial growth temperature equal to or greater than 1600 degrees C.

[0052] Similarly, also in a case where all bonds contained in compounds bonds using materials of C expressed with CH bond, CC bond, and CCl bond, it is not enough to reduce the vapor phase reaction, at the SiC epitaxial growth temperature. It is also similar also when applying compound materials simultaneously containing Si and C.

[0053] In addition, there is a further problem in such an excessive vapor phase reaction. A rate of the dissociated materials and unreacted materials is always changed, during the materials flow. Thereby effecting a thickness distribution and a density distribution, it becomes difficult to supply wafers excellent in uniformity.

Embodiment

[0054] FIG. 4 shows temperature dependency of growth rates, in an SiC epitaxial growth of an SiC epitaxial wafer according to an embodiment. In FIG. 4, the dashed line CL indicates a boundary between a mass transport rate-controlled (Diffusion Control) region DC and a surface kinetic rate-controlled (Kinetic Control) region KC in the SiC epitaxial growth. In FIG. 4, a region indicated with the arrow TR is a temperature range applicable to the SiC epitaxial growth, and the temperature range is equal to or greater than approximately 1600 degrees C., for example. An upper limit to the temperature range is approximately 2700 degrees C. near a melting point, for example. The temperature range applicable to the SiC epitaxial growth is preferable within a range from approximately 1600 degrees C. to approximately 2200 degrees C.

[0055] As shown in FIG. 5, the SiC epitaxial wafer 1 according to the embodiment includes a substrate 2, and an SiC epitaxial growth layer 3 disposed on the substrate 2. In the embodiment, an Si compound is used for a supply source of Si, and a Carbon(C) compound is used as a supply source of C, for the SiC epitaxial growth layer. Moreover, any one or both of the Si compound and the C compound is provided with a compound containing Fluoride (F), as the supply source.

[0056] The Si compound may contain any one material of SiF.sub.4, SiH.sub.3F, SiH.sub.2F.sub.2, or SiHF.sub.3, for example. SiF bond exists in the materials, e.g. SiF.sub.4, SiH.sub.3F, SiH.sub.2F.sub.2, and SiHF.sub.3. Other compounds containing chlorine (Cl) may be used as the Si compound.

[0057] Moreover, the Si compound generally can be expressed with the following equation: namely, the Si compound may contain materials expressed with Si.sub.nH.sub.xCl.sub.yF.sub.z (where n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2).

[0058] Moreover, the C compound may contain any one material of CF.sub.4, C.sub.2F.sub.6, C.sub.3F.sub.6, C.sub.4F.sub.6, C.sub.4F.sub.8, C.sub.5F.sub.8, CHF.sub.3, CH.sub.2F.sub.2, CH.sub.3F, or C.sub.2HF.sub.5. CF bond exists in the materials, e.g. CF.sub.4, C.sub.2F.sub.6, C.sub.3F.sub.8, C.sub.4F.sub.6, C.sub.4F.sub.8, C.sub.5F.sub.8, CH.sub.3F, CH.sub.2F.sub.2, CHF.sub.3, and C.sub.2HF.sub.5. Other compounds containing chlorine (Cl) may be used as the C compound.

[0059] Moreover, the C compound generally can be expressed with the following equation: namely, the C compound may contain materials expressed with C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

[0060] Moreover, the SIC epitaxial growth layer 3 may contain any one material of 4HSiC, 6HSiC, 2HSiC, or 3CSiC.

[0061] The substrate may contain material expressed with any one of 4HSiC, 6HSiC, BN, AlN, Al.sub.2O.sub.3, Ga.sub.2O.sub.3, diamond, carbon, or graphite.

[0062] In the SiC epitaxial growth for the SiC epitaxial wafer according to the embodiment, at least one of H.sub.2, Ar, HCl, and the F.sub.2 is applicable as carrier gas.

[0063] Since the SiF bonding energy is higher than the SiH bonding energy or SiCl bonding energy, the SiF bond is suitable for the SiC epitaxial growth. There is a feature that the vapor phase reaction can be reduced since the SiF bond is not easily dissociated even at a high temperature equal to or greater than 1600 degrees C. As a result of the vapor phase reaction being reduced, generation of defects, e.g. particles, downfall, and triangular defects, is suppressed. Accordingly, a manufacturing yield can be improved, a region which cannot be utilized for a device formation due to defects can be reduced, and thereby a wafer having improved quality can be provided.

[0064] Since the reaction rate is limited in a temperature on the substrate surface, it is not affected by distribution of the supply concentration, and therefore temperature uniformity affects film thickness uniformity and carrier density uniformity. Thereby, the SiC epitaxial growth excellent in controllability can be realized.

[0065] In the state where the reaction rate is limited in the temperature, many pieces (e.g., several tens or more pieces) of the SiC epitaxial wafers can easily be grown, and thereby the productivity enhancement of the epitaxial wafers can be improved.

[0066] In the SiC epitaxial growth, it is a surface kinetic rate-controlled region KC at a relatively low temperature side (right-hand side of the border line CL in FIG. 4), and it is set a mass transport rate-controlled (diffusion control) region DC at a relatively high temperature side (left-hand side of the border line CL in FIG. 4). A temperature for switching from the surface kinetic rate-control to the mass transport rate-control becomes higher, as the bonding energy of materials becomes higher. For example, SiH.sub.4 is composed of only SiH bond having a relatively low bonding energy.

[0067] SiH.sub.4 is in a relatively low temperature side, and SiH.sub.2Cl.sub.2 and SiCl.sub.4 containing SiCl bond (SiCl bonding energy is higher than SiH bonding energy) is contained are in a temperature side relatively higher than SiH.sub.4.

[0068] Moreover, SiH.sub.2F.sub.2 and SiF.sub.4 containing SiF bond (SiF bonding energy is higher than SiCl bonding energy) are in a relatively high temperature side. A temperature region required for the SiC epitaxial growth corresponds to a region indicated by the arrow TR on the left-hand side apart from 0.6 in the horizontal axis shown in FIG. 4. Accordingly, as the materials for the surface kinetic rate-controlled, materials containing the SiF bond are preferable in this temperature region.

SiC Epitaxial Wafer

[0069] FIG. 5 shows a schematic bird's-eye view configuration of the SiC epitaxial wafer according to the embodiment.

[0070] The SiC epitaxial wafer 1 contains 4HSiC, for example, and includes an SiC substrate 2, and an SiC epitaxial growth layer 3 stacked on the SiC substrate 2. A thickness t1 of the SiC substrate 2 is approximately 200 m to approximately 500 m, for example, and a thickness t2 of the SiC epitaxial growth layer 3 is approximately 4 m to approximately 100 m, for example.

Crystal Structure

[0071] FIG. 6A shows a schematic bird's-eye view configuration of a unit cell in a 4HSiC crystal applicable to the SiC epitaxial wafer 1 according to the embodiment, FIG. 6B shows a schematic configuration of a two layer portion of the 4HSiC crystal, and FIG. 6C shows a schematic configuration of four layer portion of the 4HSiC crystal.

[0072] Moreover, FIG. 7 shows a schematic configuration of the unit cell of the 4HSiC crystal structure of shown in FIG. 6A observed from directly above a (0001) surface.

[0073] As shown in FIGS. 6A to 6C, the crystal structure of the 4HSiC can be approximated with a hexagonal system, and four C atoms are bound with respect to one Si atom. Four C atoms are positioned at four vertexes of a regular tetrahedron in which the Si atom is disposed at a center thereof. In the four C atoms, one Si atom is positioned in [0001] axis direction with respect to the C atom, and other three C atoms are positioned at a [000-1] axis side with respect to the Si atom.

[0074] The [0001] axis and [000-1] axis are along the axial direction of the hexagonal prism, and a surface (top surface of the hexagonal prism) using the [0001] axis as a normal line is (0001) surface (Si surface). On the other hand, a surface (bottom surface of the hexagonal prism) using the [000-1] axis as a normal line is (000-1) surface (C surface).

[0075] Moreover, directions vertical to the [0001] axis, and passing along the vertexes not adjacent with one another in the hexagonal prism observed from directly above the (0001) surface are respectively a1 axis [2-1-10], a2 axis [-12-10], and a3 axis [-1-120].

[0076] As shown in FIG. 7, a direction passing through the vertex between the a1 axis and the a2 axis is [11-20] axis, a direction passing through the vertex between the a2 axis and the a3 axis is [-2110] axis, and a direction passing through the vertex between the a3 axis and the al axis is [1-210] axis.

[0077] The axes which are incline at an angle of 30 degrees with respect to each axis of the both sides, and used as the normal line of each side surface of the hexagonal prism, between each of the axes of the above-mentioned six axes passing through the respective vertexes of the hexagonal prism, are respectively [10-10] axis, [1-100] axis, [0-110] axis, [-1010] axis, [-1100] axis, and [01-10] axis, in the clockwise direction sequentially from between the a1 axis and the [11-20] axes. Each surface (side surface of the hexagonal prism) using these axes as the normal line is a crystal surface right-angled to the (0001) surface and the (000-1) surface.

Fabrication Method of SiC Epitaxial Wafer

[0078] A fabrication method of the SiC epitaxial wafer according to the embodiment includes: preparing an SiC ingot, cutting the prepared SiC ingot with an off angle, and polishing the cut SiC ingot to form an SiC bare wafer; removing a cut surface of the SiC bare wafer to form an SiC substrate; forming an oxide film on a principal surface of the SiC substrate; removing the oxide film; and crystal-growing an SiC epitaxial growth layer on the SiC substrate. In the embodiment, a material gas to be supplied contains an Si compound gas used as a supply source of Si, and C compound gas used as a supply source of C. Moreover, any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing F.

[0079] The SiC bare wafer was obtained by cutting the 4HSiC ingot with an off angle of 4 degrees in the [11-20] axis direction with respect to the (0001) surface. A diameter of the wafer is approximately 150 mm.

[0080] Subsequently, the surface where the SiC bare wafer is cut out is subjected to the polishing process, and then a suitable surface for the epitaxial wafer was obtained. In the polishing process, including a bevel process of the wafer edge, etc., the polished surface was finished by utilizing a chemical effect since it is not sufficiently able to remove processing damage merely by mechanical processes.

[0081] Before the epitaxial growth, the polished surface is sufficiently washed in order to clean the surface. In the embodiment, RCA washing, brush washing, functional-water washing, megasonic washing, etc. can be used, as a washing method.

[0082] A pressure in a reactor after disposing the wafer is kept at approximately 1 kPa to approximately 100 kPa, for example. H.sub.2 used as a carrier gas of the materials is supplied into the reactor. An Ar gas may be supplied thereinto instead of H.sub.2.

[0083] By mixing HCl or HF to the carrier gas, a vapor phase reaction can be reduced, generation of particles on the epitaxial wafer can be suppressed, and thereby a high quality wafer can be supplied.

[0084] FIG. 8A shows the processing step of preparing a hexagonal-crystal SiC ingot 13, and cutting the SiC ingot 13 with an off angle with respect to the (0001) surface, and polishing the cut SiC ingot 13 to form a plurality pieces of SiC bare wafers 14, in a schematic bird's-eye view configuration showing the fabrication method of the SiC epitaxial wafer according to the embodiment. Moreover, FIG. 8B shows the processing step of removing the cut surface 15 of the SiC bare wafer 14 after the machining process. Furthermore, FIG. 8C shows the processing step of forming an oxide film on the principal surface 4 of the SiC substrate 2 by applying an oxidation treatment to the principal surface 4 of the SiC substrate 2. Still further, FIG. 8D shows the processing step of forming an SiC epitaxial growth layer 3 on the SiC substrate 2.

(a) Firstly, as shown in FIG. 8A, the hexagonal-crystal SiC ingot 13 is prepared. Subsequently, a plurality pieces of the SiC bare wafers 14 are obtained by cutting the SiC ingot 13 with the off angle A of equal to or less than 4 degrees in the [11-20] axis direction with respect to the (0001) surface. Next, the cut surface 15 ((0001) surface) of the SiC bare wafer 14 is polished by a machining process, such as lap processing etc.
(b) Subsequently, as shown in FIG. 8B, the cut surface 15 ((0001) surface) is removed by equal to or greater than approximately 500 nm, for example. As a removing method, Chemical Mechanical Polishing (CMP) technology, plasma etching technology, etc. are applicable, for example. Preferably, plasma etching may be applied. Although it is required for several hours for CMP with less damage to remove the surface by equal to or greater than 500 nm since the SiC is an extremely hard material, the removing process will be completed in a short time, e.g., approximately 20 minutes, if the plasma etching is used. On the other hand, with regard to the cut surface 15 of the SiC bare wafer 14, the damage received by the plasma etching is small since the SiC is extremely hard. The damaged layer on the cut surface 15 of the SiC bare wafer 14 generated by the machining process after the cutting process is sufficiently removed by the above-mentioned removing process, and thereby the SiC substrate 2 having a thickness t1 of approximately 200 m to approximately 500 m is obtained.
(c) Subsequently, as shown in FIG. 10C, an oxidation treatment is applied on the principal surface 4 ((0001) surface) of the SiC substrate 2, and thereby the oxide film 16 is formed on the principal surface 4 of the SiC substrate 2. The oxidation treatment may be performed with a dry oxidation method or a wet oxidation method. Although illustration is omitted, the aforementioned oxide film 16 is formed also in a back side surface and a peripheral surface of the SiC substrate 2. Then, the oxide film 16 is removed using a fluoric acid (HF). By applying the formation process and the removing process of the oxide film 16, the damaged layer which cannot be removed by neither the CMP nor the plasma etching, and an altered layer (damaged layer) generated at the time of applying the CMP or plasma etching can be certainly removed from the cut surface 15 of the SiC bare wafer 14. The formation process and the removing process for the oxide film 16 may be performed only after the removing treatment of the cut surface 15 by equal to or greater than 500-nm thickness, but also only before the removing treatment or also before and after the removing treatment.
(d) Subsequently, as shown in FIG. 10D, the SiC epitaxial growth layer 3 is crystal-grown on the SiC substrate 2.

[0085] As the materials, SiF.sub.4 and C.sub.3F.sub.8 are supplied thereinto, for example. SiF.sub.4 and C.sub.3F.sub.8 are respectively diluted with H.sub.2 gas, and then are supplied into the reactor. A dilution concentration is 10%, but it is not limited to such a concentration value.

[0086] The epitaxial growth temperature may be approximately 1600 degrees C., for example, and may properly be approximately 1750 degrees C.

[0087] As a result of inspecting the epitaxially-grown wafer surface, a surface-roughness defect density containing particles on the wafer was equal to or less than 0.07 cm.sup.2. Namely, only approximately ten defects are generated on a 150 mm wafer (wafer having a diameter of 150 mm), and thereby a high quality wafer with few surface unevenness defects can be obtained.

[0088] The off angle of the wafer may be smaller than 4 degrees. Moreover, the growth surfaces may be the C surface, the (11-20) surface, or the (10-10) surface.

[0089] 6HSiC can also be used therefor instead of 4HSiC. The wafer is heated at a temperature equal to or greater than 1600 degrees C., and the C.sub.3H.sub.a diluted with hydrogen is supplied into the reactor, in order to perform the SiC homoepitaxial growth. SiHF.sub.3 can also be used for the materials instead of SiF.sub.4.

[0090] CHF.sub.3 is used therefor instead of C.sub.3H.sub.8, in order to perform the epitaxial growth at a high temperature equal to or greater than 1800 degrees C.

[0091] SiF bonding energy is higher than SiH bonding energy or SiCl bonding energy. The bond having such a high bonding energy is not easily dissociated even at the high temperature, thereby reducing the excessive reaction.

[0092] In the SiC epitaxial wafer according to the embodiment and the manufacturing apparatus, the dissociation of bonding for the materials containing the SiF bond begins at a temperature suitable for the SiC epitaxial growth. As a result, the vapor phase reaction is reduced, and thereby generation of defects, e.g. particles, downfall, and triangular defects, is suppressed. Accordingly, a manufacturing yield can be improved, a region which cannot be utilized for a device formation due to defects can be reduced, and thereby a wafer having improved quality can be provided.

[0093] Furthermore, since the reaction rate is limited to the substrate concentration rather than the supply concentration, temperature uniformity is directly led to film thickness uniformity and carrier density uniformity. Accordingly, the high quality SiC epitaxial wafer excellent in the uniformities can be obtained.

[0094] Similarly, CF bonding energy is higher than CH bonding energy, CCl bonding energy, and CC bonding energy. Accordingly, a still higher effect is produced by using in combination with compounds containing the SiF bond.

Growth Temperature Range

[0095] A lower limit of the growth temperature range is approximately 1400 degrees C. The lower limit of the temperature of the apparatus is strictly dependent on a flow rate and a flow velocity of hydrogen in the reactor. The lower limit is increased, since hydrogen takes heat from the SiC epitaxial wafer, as the flow rate and the flow velocity of hydrogen become larger. Conversely, the heat taken by hydrogen from the SiC epitaxial wafer becomes smaller, as the flow rate and the flow velocity of hydrogen become smaller. Accordingly, the lower limit is decreased since the surface temperature of the SiC epitaxial wafer is increased compared with the case where the flow rate and the flow velocity of hydrogen relatively large. Since stacking faults will be easily generated during the SiC epitaxial growth if the growth temperature is relatively low, a stacking fault density of the SIC epitaxial wafer surface will also be increased. The stacking fault density can be estimated by photoluminescence (PL) imaging, for example.

[0096] The upper limit of the growth temperature range can be allowed up to near the melting point, in physical properties. As a problem at the apparatus side, if the upper limit of the temperature is increased, a cost and structure of the apparatus will be varied. Moreover, since time required for increasing the temperature is also increased, it is not preferable that the temperature is too high also in terms of cost. Accordingly, it is preferable to grow up at a relatively low temperature in the light of a balance of a fabricating cost. However, there is a problem peculiar to SIC that the stacking fault density becomes higher at a relatively low temperature, and the temperature during the epitaxial growth is increased in order to reduce the stacking fault density. Accordingly, the optimal temperature range may be approximately 1600 degrees C. to approximately 1750 degrees C.

[0097] More preferably, the optimal temperature is approximately 1750 degrees C. which is a temperature where the stacking fault density can be sufficiently reduced. However, such an optimal temperature also depends on the flow rate and the flow velocity of hydrogen in the reactor, for the above-mentioned reason.

[0098] FIG. 9 shows an example of an epitaxial quality image of the SIC epitaxial wafer according to the embodiment. In the SiC epitaxial wafer according to the embodiment, a surface-roughness defect density (approximately 0.07 cm.sup.2) containing particles on the wafer is obtained.

[0099] This value is equivalent to an example where the number of defects is 12 in a wafer having a diameter of 150 mm.

[0100] FIG. 10 shows an example of an epitaxial quality image of the SiC epitaxial wafer according to the comparative example. In the SiC epitaxial wafer according to the comparative example, a surface-roughness defect density containing particles on the wafer is approximately 1.00 cm.sup.2. This value is equivalent to an example where the number of defects is 173 in a wafer having a diameter of 150 mm.

CVD Temperature Profile

Profile Example 1

[0101] FIG. 11 shows an example 1 of a CVD temperature profile showing a relationship between growth temperature T.sub.G (degrees C.) and time t, in the SiC epitaxial growth according to the embodiment.

[0102] The example 1 of the CVD temperature profile corresponds to a case where a predetermined temperature of the hydrogen etching (in-situ Etching) immediately before depositing the SiC epitaxial growth layer is lower than a predetermined temperature of depositing the SiC epitaxial growth layer. In FIG. 11, the straight line H expresses a period of temperature rise, the straight line E expresses a period of hydrogen etching, the straight line D expresses a period of SiC epitaxial growth, and the straight line C expresses a period of temperature fall.

[0103] When the hydrogen gas is used as the carrier gas, a value of specific heat and a coefficient of thermal conductivity of the hydrogen gas are larger than those of other gases. Therefore, the hydrogen gas has properties, i.e., a capacitance of heat is larger and the heat is easily conducted. When the flow rate of hydrogen is varied, the temperature of the wafer surface is also varied even if a predetermined temperature of a susceptor is the same as each other. Since the hydrogen flow rate and the temperature of the wafer surface are correlated with each other, the optimal hydrogen etching temperature varies in accordance with the hydrogen flow rate.

[0104] The example 1 of the CVD temperature profile shows an example where the predetermined temperature T.sub.2 of the hydrogen etching immediately before the deposition of SiC epitaxial growth layer is set so as to be lower than the predetermined temperature T.sub.3 of the deposition of SiC epitaxial growth layer, as shown in FIG. 11.

Profile Example 2

[0105] FIG. 12 shows an example 2 of the CVD temperature profile showing the relationship between growth temperature T.sub.G (degrees C.) and time t, in the SiC epitaxial growth according to the embodiment.

[0106] The example 2 of the CVD temperature profile corresponds to a case where the predetermined temperature of the hydrogen etching immediately before depositing the SiC epitaxial growth layer is equal to the predetermined temperature of depositing the SiC epitaxial growth layer. In FIG. 12, the straight line H expresses a period of temperature rise, the straight lines E+D express a period of hydrogen etching and a period of SiC epitaxial growth, and the straight line C expresses a period of temperature fall.

[0107] As mentioned above, when the flow rate of hydrogen is varied, the temperature of the wafer surface is also varied even if a predetermined temperature of a susceptor is the same as each other. Since the hydrogen flow rate and the temperature of the wafer surface are correlated with each other, the optimal hydrogen etching temperature varies in accordance with the hydrogen flow rate.

[0108] The example 2 of the CVD temperature profile shows an example where the predetermined temperature of the hydrogen etching immediately before the deposition of SiC epitaxial growth layer is set so as to be equal to the predetermined temperature T.sub.3 of the deposition of SiC epitaxial growth layer, as shown in FIG. 12.

Profile Example 3

[0109] FIG. 13 shows an example 3 of the CVD temperature profile showing the relationship between growth temperature T.sub.G (degrees C.) and time t, in the SiC epitaxial growth according to the embodiment.

[0110] The example 3 of the CVD temperature profile corresponds to a case where the predetermined temperature of the hydrogen etching immediately before depositing the SiC epitaxial growth layer is higher than the predetermined temperature of depositing the SiC epitaxial growth layer. In FIG. 13, the straight line H expresses a period of temperature rise, the straight line E expresses a period of hydrogen etching, the straight line D expresses a period of SiC epitaxial growth, and the straight line C expresses a period of temperature fall.

[0111] As mentioned above, when the flow rate of hydrogen is varied, the temperature of the wafer surface is also varied even if a predetermined temperature of a susceptor is the same as each other. Since the hydrogen flow rate and the temperature of the wafer surface are correlated with each other, the optimal hydrogen etching temperature varies in accordance with the hydrogen flow rate.

[0112] The example 3 of the CVD temperature profile shows an example where the predetermined temperature T.sub.2 of the hydrogen etching immediately before the deposition of SiC epitaxial growth layer is set so as to be higher than the predetermined temperature T.sub.3 of the deposition of SiC epitaxial growth layer, as shown in FIG. 13.

Manufacturing Apparatus

[0113] A manufacturing apparatus of the SiC epitaxial wafer according to the embodiment includes a gas injection port, a gas exhaust port, a heating unit, and a reactor. In the embodiment, a material gas to be supplied contains an Si compound gas used as a supply source of Si, and C compound gas used as a supply source of C. Moreover, any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing F.

First CVD Apparatus

[0114] As shown in FIG. 14, in the manufacturing apparatus of the SiC epitaxial wafer according to the embodiment, a schematic configuration example of a first CVD apparatus applicable to the SiC epitaxial growth includes a gas injection port 140, a gas exhaust port 160, a heating unit 100, and a vertical-type reactor 120.

[0115] As a heating method of the heating unit 100, resistance heating, induction heating using a coil, lamp heating, etc. are adoptable. In the case of the induction heating method, a structural member made from carbon (not shown in FIG. 14) disposed near the wafer, the structural member made from carbon produces heat, and then the wafer in contact with the structural member is heated or the wafer is heated with radiation from the structural member made from carbon.

[0116] In the vertical-type reactor 120, a plurality pieces of the SiC epitaxial wafers 1 can be disposed in a face up manner or face down manner.

[0117] While the material gas is supplied from the gas injection port 140 at a lower portion of the vertical-type reactor 120 and then is exhausted from the gas exhaust port 160 at an upper portion of the vertical-type reactor 120, the materials which flows on the surface of the plurality pieces of the SiC epitaxial wafers 1 react, thereby forming the SiC epitaxial growth layer.

[0118] The material gas to be supplied generally can be expressed with the following equation: namely, Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2) and/or C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

[0119] As the carrier gas, at least one of H.sub.2, Ar, HCl, and F.sub.2 is applicable.

[0120] As materials for dopant, N.sub.2 or Trimethylaluminium (TMA: (CH.sub.3).sub.3Al) is applicable.

Second CVD Apparatus

[0121] As shown in FIG. 15, in the manufacturing apparatus of the SiC epitaxial wafer according to the embodiment, a schematic configuration example of a second CVD apparatus applicable to the SiC epitaxial growth includes a gas injection port 140, a gas exhaust port 160, a heating unit 100, and a vertical-type reactor 120.

[0122] As a heating method of the heating unit 100, resistance heating, induction heating using a coil, lamp heating, etc. are adoptable. In the case of the induction heating method, a structural member made from carbon (not shown in FIG. 14) disposed near the wafer, the structural member made from carbon produces heat, and then the wafer in contact with the structural member is heated or the wafer is heated with radiation from the structural member made from carbon.

[0123] In the vertical-type reactor 120, the plurality pieces of the SiC epitaxial wafers 1 are disposed so as to be parallel to the flow of the gas.

[0124] While the material gas is supplied from the gas injection port 140 at a lower portion of the vertical-type reactor 120 and then is exhausted from the gas exhaust port 160 at an upper portion of the vertical-type reactor 120, the materials which flows on the surface of the plurality pieces of the SiC epitaxial wafers 1 react, thereby forming the SiC epitaxial growth layer.

[0125] The material gas to be supplied generally can be expressed with the following equation: namely, Si.sub.aH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2) and/or C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

[0126] As the carrier gas, at least one of H.sub.2, Ar, HCl, and F.sub.2 is applicable.

[0127] As the materials for dopant, N.sub.2 or TMA is applicable.

Third CVD Apparatus

[0128] As shown in FIG. 16, in the manufacturing apparatus 200 of the

[0129] SiC epitaxial wafer according to the embodiment, a schematic configuration example of a third CVD apparatus applicable to the SiC epitaxial growth includes a gas injection port 140, a gas exhaust port 160, a heating unit 100, and a horizontal-type reactor 130.

[0130] As a heating method of the heating unit 100, resistance heating, induction heating using a coil, lamp heating, etc. are adoptable. In the case of the induction heating method, a structural member made from carbon (not shown in FIG. 14) disposed near the wafer, the structural member made from carbon produces heat, and then the wafer in contact with the structural member is heated or the wafer is heated with radiation from the structural member made from carbon.

[0131] In the horizontal-type reactor 130, the plurality pieces of the SiC epitaxial wafers 1 can be vertically arranged in the upward direction stand so as to be opposite to the flow of gas.

[0132] While the material gas is supplied from the gas injection port 140 of the horizontal-type reactor 130, passes through the plurality pieces of the SiC epitaxial wafers 1, and then is exhausted from the gas exhaust port 160, the materials which flows on the surface of the plurality pieces of the SiC epitaxial wafers 1 react, thereby forming the SiC epitaxial growth layer.

[0133] The material gas to be supplied generally can be expressed with the following equation: namely, Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2) and/or C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

[0134] As the carrier gas, at least one of H.sub.2, Ar, HCl, and F.sub.2 is applicable.

[0135] As the materials for dopant, N.sub.2 or TMA is applicable.

Fourth CVD Apparatus

[0136] As shown in FIG. 17, in the manufacturing apparatus 200 of the SiC epitaxial wafer according to the embodiment, a schematic configuration example of a fourth CVD apparatus applicable to the SiC epitaxial growth includes a gas injection port 140, a gas exhaust port 160, a heating unit 100, and a horizontal-type reactor 130.

[0137] As a heating method of the heating unit 100, resistance heating, induction heating using a coil, lamp heating, etc. are adoptable. In the case of the induction heating method, a structural member made from carbon (not shown in FIG. 14) disposed near the wafer, the structural member made from carbon produces heat, and then the wafer in contact with the structural member is heated or the wafer is heated with radiation from the structural member made from carbon.

[0138] In the horizontal-type reactor 130, a plurality pieces of the SiC epitaxial wafers 1 can be disposed in a face up manner or face down manner.

[0139] While the material gas is supplied from the gas injection port 140 of the horizontal-type reactor 130, passes through the plurality pieces of the SiC epitaxial wafers 1, and then is exhausted from the gas exhaust port 160, the materials which flows on the surface of the plurality pieces of the SiC epitaxial wafers 1 react, thereby forming the SiC epitaxial growth layer.

[0140] The material gas to be supplied generally can be expressed with the following equation: namely, Si.sub.nH.sub.xCl.sub.yF.sub.z (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2) and/or C.sub.mH.sub.qCl.sub.rF.sub.s (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2).

[0141] As the carrier gas, at least one of H.sub.2, Ar, HCl, and F.sub.2 is applicable.

[0142] As the materials for dopant, N.sub.2 or TMA is applicable.

[0143] The above-mentioned SiC epitaxial wafer is applicable to fabricating of various kinds of SiC semiconductor elements, for example. Hereinafter, there will be shown examples of an SiC Schottky Barrier Diode (SiC-SBD), an SiC Trench-gate type Metal Oxide Semiconductor Field Effect Transistor (Sic-TMOSFET), and an SiC planar-gate type MOSFET, as those examples.

SiC-SBD

[0144] FIG. 18 shows a schematic cross-sectional structure of SiC-SBD 21 fabricated using the SiC epitaxial wafer according to the embodiment.

[0145] As shown in FIG. 18, the SiC-SBD 21 fabricated using the SiC epitaxial wafer according to the embodiment includes an SiC epitaxial wafer 1. The SiC epitaxial wafer 1 includes: an n.sup.+ type SiC substrate 2 (of which an impurity concentration is approximately 110.sup.18 cm.sup.3 to approximately 110.sup.21 cm.sup.3, for example); and an n.sup. type SiC epitaxial growth layer 3 (of which an impurity concentration is approximately 510.sup.14 cm.sup.3 to approximately 510.sup.16 cm.sup.3, for example). As an n-type doping impurities, nitrogen (N), phosphorus (P), arsenic (As), etc. are applicable, for example.

[0146] A back side surface ((000-1) C surface) of the SiC substrate 2 includes a cathode electrode 22 so as to cover the whole region of the backside surface, and the cathode electrode 22 is connected to a cathode terminal K.

[0147] A surface 10 ((0001) Si surface) of the SiC epitaxial growth layer 3 includes a contact hole 24 to which a part of the SiC epitaxial growth layer 3 is exposed as an active region 23, and a field insulating film 26 is formed at a field region 25 which surrounding the active region 23.

[0148] Although the field insulating film 26 includes silicon oxide (SiO.sub.2), the field insulating film 26 may include other insulating materials, e.g. silicon nitride (SiN). An anode electrode 27 is formed on the field insulating film 26, and the anode electrode 27 is connected to an anode terminal A.

[0149] Near the surface 10 (surface portion) of the SiC epitaxial growth layer 3, a p-type Junction Termination Extension (JTE) structure 28 is formed so as to be contacted with the anode electrode 27. The JTE structure 28 is formed along an outline of the contact hole 24 so as to extend from the outside to inside of the contact hole 24 of the field insulating film 26.

[0150] According to the SiC-SBD 21 fabricated using the SiC epitaxial wafer according to the embodiment, a leakage current can be reduced.

SiC-TMOSFET

[0151] FIG. 19 shows a schematic cross-sectional structure of the SiC-TMOSFET 31 fabricated using the SiC epitaxial wafer according to the embodiment.

[0152] As shown in FIG. 19, the SiC-TMOSFET 31 fabricated using the SiC epitaxial wafer according to the embodiment includes an SiC epitaxial wafer 1. The SiC epitaxial wafer 1 includes: an n.sup.+ type SiC substrate 2 (of which an impurity concentration is approximately 110.sup.18 cm.sup.3 to approximately 110.sup.21 cm.sup.3, for example); and an n.sup. type SiC epitaxial growth layer 3 (of which an impurity concentration is approximately 510.sup.14 cm.sup.3 to approximately 510.sup.16 cm.sup.3, for example). As an n-type doping impurities, nitrogen (N), phosphorus (P), arsenic (As), etc. are applicable, for example.

[0153] A back side surface ((000-1) C surface) of the SiC substrate 2 includes a drain electrode 32 so as to cover the whole region of the back side surface, and the drain electrode 32 is connected to a drain terminal D.

[0154] Near the surface 10 ((0001) Si surface) (surface portion) of the SiC epitaxial growth layer 3, a p-type body region 33 (of which an impurity concentration is approximately 110.sup.16 cm.sup.3 to approximately 110.sup.19 cm.sup.3, for example) is formed. In the SiC epitaxial growth layer 3, a portion at a side of the SiC substrate 2 with respect to the body region 33 is an n.sup. type drain region 34 where a state after the epitaxial growth is still kept.

[0155] A gate trench 35 is formed in the SIC epitaxial growth layer 3. The gate trench 35 passes through the body region 33 from the surface 10 of the SIC epitaxial growth layer 3, and a deepest portion of the gate trench 35 extends to the drain region 34.

[0156] A gate insulating film 36 is formed on an inner surface of the gate trench 35 and the surface 10 of the SiC epitaxial growth layer 3 so as to cover the whole of the inner surface of the gate trench 35. Moreover, a gate electrode 37 is embedded in the gate trench 35 by filling up the inside of the gate insulating film 36 with polysilicon, for example. A gate terminal G is connected to the gate electrode 37.

[0157] An n.sup.+ type source region 38 forming a part of a side surface of the gate trench 35 is formed on a surface portion of the body region 33.

[0158] Moreover, a p.sup.+ type body contact region 39 (of which an impurity concentration is approximately 110.sup.18 cm.sup.3 to approximately 110.sup.21 cm.sup.3, for example) which passes through the source region 38 from the surface 10 and is connected to the body region 33 is formed on the SiC epitaxial growth layer 3.

[0159] An interlayer insulating film 40 including SiO.sub.2 is formed on the SiC epitaxial growth layer 3. A source electrode 42 is connected to the source region 38 and the body contact region 39 through a contact hole 41 formed in the interlayer insulating film 40. A source terminal S is connected to the source electrode 42.

[0160] A predetermined voltage (voltage equal to or greater than a gate threshold voltage) is applied to the gate electrode 37 in a state where a predetermined potential difference is generated between the source electrode 42 and the drain electrode 32 (between the source and the drain). Thereby, a channel can be formed by an electric field from the gate electrode 37 near the interface between the gate insulating film 36 and the body region 33. Thus, an electric current can be flowed between the source electrode 42 and the drain electrode 32, and thereby the SiC-TMOSFET 31 can be turned ON state.

[0161] The SiC-TMOSFET 31 fabricated using the SiC epitaxial wafer according to the embodiment can improve a carrier mobility and can offer enhanced speed.

SiC Planar-Gate Type MOSFET

[0162] FIG. 20 shows a schematic cross-sectional structure of the planar-gate type SiC-MOSFET fabricated using the SiC epitaxial wafer according to the embodiment.

[0163] As shown in FIG. 20, the planar-gate type SiC-MOSFET 51 fabricated using the SiC epitaxial wafer according to the embodiment includes an SiC epitaxial wafer 1. The SiC epitaxial wafer 1 includes: an n.sup.+ type SiC substrate 2 (of which an impurity concentration is approximately 110.sup.18 cm.sup.3 to approximately 110.sup.21 cm.sup.3, for example); and an n.sup. type SiC epitaxial growth layer 3 (of which an impurity concentration is approximately 510.sup.14 cm.sup.3 to approximately 510.sup.16 cm.sup.3, for example).

[0164] A back side surface ((000-1) C surface) of the SiC substrate 2 includes a drain electrode 52 so as to cover the whole region of the back side surface, and the drain electrode 52 is connected to a drain terminal D.

[0165] Near the surface 10 ((0001) Si surface) (surface portion) of the SiC epitaxial growth layer 3, a p-type body region 53 (of which an impurity concentration is approximately 110.sup.16 cm.sup.3 to approximately 110.sup.19cm.sup.3, for example) is formed in a well shape. In the SiC epitaxial growth layer 3, a portion at a side of the SiC substrate 2 with respect to the body region 53 is an n.sup. type drain region 54 where a state after the epitaxial growth is still kept.

[0166] An n.sup.+ type source region 55 is formed on a surface portion of the body region 53 with a certain space from a periphery of the body region 53.

[0167] A p.sup.+ type body contact region 56 (of which an impurity concentration is approximately 110.sup.18 cm.sup.3 to approximately 110.sup.21 cm.sup.3, for example) is formed inside of the source region 55. The body contact region 56 passes through the source region 55 in a depth direction, and is connected to the body region 53.

[0168] A gate insulating film 57 is formed on the surface 10 of the SiC epitaxial growth layer 3. The gate insulating film 57 covers the portion surrounding the source region 55 in the body region 53 (peripheral portion of the body region 53), and an outer peripheral portion of the source region 55.

[0169] A gate electrode 58 including polysilicon, for example, is formed on the gate insulating film 57. The gate electrode 58 is opposed to the peripheral portion of the body region 53 by sandwiching the gate insulating film 57. A gate terminal G is connected to the gate electrode 58.

[0170] An interlayer insulating film 59 including SiO.sub.2 is formed on the SiC epitaxial growth layer 3. A source electrode 61 is connected to the source region 55 and the body contact region 56 through a contact hole 60 formed in the interlayer insulating film 59. A source terminal S is connected to the source electrode 61.

[0171] A predetermined voltage (voltage equal to or greater than a gate threshold voltage) is applied to the gate electrode 58 in a state where a predetermined potential difference is generated between the source electrode 61 and the drain electrode 52 (between the source and the drain). Thereby, a channel can be formed by an electric field from the gate electrode 58 near the interface between the gate insulating film 57 and the body region 53. Thus, an electric current can be flowed between the source electrode 61 and the drain electrode 52, and thereby the planar-gate type MOSFET 51 can be turned ON state.

[0172] The planar-gate type MOSFET 51 also can improve a carrier mobility and can offer enhanced speed, similarly to the SiC-TMOSFET 31 shown in FIG. 19.

[0173] Although the embodiment has been explained above, the embodiment can also be implemented with other configurations.

[0174] For example, the principal surface 4 (substrate surface) of the SiC substrate 2 may be inclined in the OFF direction of [-1100] axis with respect to the (0001) surface by the off angle equal to or less than 4 degrees. Although illustration is omitted, MOS capacitors can also be fabricated using the SiC epitaxial wafer according to the embodiment. According to the MOS capacitors, a yield and reliability can be improved. Moreover, with regard to the reliability, initial failures can be reduced.

[0175] Although illustration is omitted, bipolar junction transistors can also be fabricated using the SiC epitaxial wafer according to the embodiment. In addition, the SiC epitaxial wafer according to the embodiment can also be used for fabricating of SiC-pn diodes, SiC Insulated Gate Bipolar Transistor (IGBT), SiC complementary MOSFET, etc,

[0176] According to the SiC epitaxial wafer according to the embodiment, defect regions on the surface or interface of the SiC epitaxial growth layer can be reduced. Therefore, a leakage current, ununiformity of the oxide film thickness, interface state density, surface recombination, etc. are reduced, and thereby field effect mobility can be improved. Accordingly, there can be provided the high quality SIC semiconductor device having high reliability.

[0177] According to the embodiment, there can be provided the high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, the manufacturing apparatus of the SiC epitaxial wafer, the fabrication method of the SiC epitaxial wafer, and the semiconductor device.

Other Embodiments

[0178] As mentioned above, although the SiC epitaxial wafer, the manufacturing apparatus of the SiC epitaxial wafer, the fabrication method of the SiC epitaxial wafer, and the semiconductor device have been described, as a disclosure including associated description and drawings to be construed as illustrative, not restrictive. This disclosure makes clear a variety of alternative embodiment, working examples, and operational techniques for those skilled in the art.

[0179] Such being the case, the embodiments cover a variety of embodiments, whether described or not.

INDUSTRIAL APPLICABILITY

[0180] The semiconductor device to which the SiC epitaxial wafer according to the embodiment is applied can be applied to wide applicable fields, e.g., power modules for inverter circuits for driving electric motors utilized as sources of power of electric vehicles (including hybrid cars), trains, industrial robots; and power modules for inverter circuits for transforming electric power generated by electric generators (e.g., solar cells, wind power generators, and the like (in particular private electric generators)) into electric power for commercial power sources, etc.