Combined RF equalizer and I/Q imbalance correction

Abstract

Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Claims

1. An apparatus of a user equipment (UE) comprising: a digital front end arranged to perform signal processing on signals for transmission from the UE and received at the UE, the digital front end comprising: a combined system comprising radio frequency (RF) equalizer circuitry and in-phase/quadrature-phase (IQ) imbalance correction (IQIC) stage circuitry in a single stage, the combined system implemented as a first and second complex finite impulse response (FIR) filter disposed in parallel and an adder to sum outputs of the first and second complex FIR filters, the first and second complex FIR filters respectively comprising coefficients c and d, where c is the convolution of a and h, and d is the convolution of b and h, h is an impulse response of the RF equalizer circuitry alone, and a and b are linear combinations of IQ correction coefficients of real and imaginary components of the IQIC stage circuitry alone, and an output of the combined system is: $y_{\mathrm{IQE},n}=f\left(x\right)=\underset{k=1}{\overset{M}{.Math.}}{c}_k.Math.x_{n-k}+\underset{k=1}{\overset{M}{.Math.}}{d}_k.Math.x_{n-k}^{*}$ where M is a filter length of the first and second complex FIR filters and x, x* are complex conjugates of an input signal and are respectively supplied to the first and second complex FIR filter.

2. The apparatus of claim 1, wherein the digital front end further comprises: a channel filter and digital up conversion (DUC) stage arranged to convert a baseband transmit signal to an intermediate frequency (IF) signal and filter the IF signal to produce a filtered IF signal; and a crest factor reduction (CFR) stage arranged to limit a peak-to-average ratio of the filtered IF signal.

3. The apparatus of claim 2, wherein the digital front end further comprises: a digital pre-distortion (DPD) stage arranged to linearize a signal from the CFR stage and provide an output to the combined system.

4. The apparatus of claim 1, further comprising: an antenna configured to transmit the output of the combined system or receive an input signal to be supplied to the digital front end.

5. The apparatus of claim 1 wherein: the first and second complex FIR filters comprise a plurality of taps at a sampling rate of 307.2 million samples per second (MSPS).

6. The apparatus of claim 5 wherein: each tap implements f(x) using a plurality of multiply-accumulate (MAC) operations.

7. The apparatus of claim 6 wherein: four MAC operations are used per tap.

8. The apparatus of claim 5 wherein: each of the first and second complex FIR filters comprises 32 taps.

9. An apparatus comprising: a digital front end arranged to perform signal processing on signals transmitted to user equipment (UE) and received from the UE, the digital front end comprising: a combined system comprising radio frequency (RF) equalizer circuitry and in-phase/quadrature-phase (IQ) imbalance correction (IQIC) stage circuitry in a single stage, the combined system arranged to compensate for dispersion in a transmitter or receiver RF path and for a frequency dependent linear response of a power amplifier along the RF path and RF circuits in a transmitter chain and arranged to compensate for an imbalance between an IQ ratio of an input RF signal, the combined system comprising a plurality of parallel finite impulse response (FIR) filters whose outputs are combined to provide a combined output, the first and second FIR filters respectively comprising coefficients that are different convolutions of an impulse response of the RF equalizer circuitry alone and linear combinations of IQ correction coefficients of real and imaginary components of the IQIC stage circuitry alone, and the combined output is: $y_{\mathrm{IQE},n}=f\left(x\right)=\underset{k=1}{\overset{M}{.Math.}}{c}_k.Math.x_{n-k}+\underset{k=1}{\overset{M}{.Math.}}{d}_k.Math.x_{n-k}^{*}$ where M is a filter length of the first and second complex FIR filters and x, x* are complex conjugates of the input RF signal and are respectively supplied to the first and second complex FIR filter, and c and d are respectively the first and second FIR filter components.

10. The apparatus of claim 9, wherein the digital front end further comprises: a channel filter and digital up conversion (DUC) stage arranged to upconvert a baseband transmit signal and filter the upconverted signal to produce a filtered signal; and a crest factor reduction (CFR) stage arranged to limit a peak-to-average ratio of the filtered signal.

11. The apparatus of claim 10, wherein the digital front end further comprises: a digital pre-distortion (DPD) stage arranged to linearize a signal from the CFR stage and provide an output to the combined system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates portions of an exemplary transmitter in which aspects of the present invention may be employed;

(2) FIG. 2 illustrates an FIR filter implementation of the equalization stage and an IQ Imbalance Correction stage of FIG. 1;

(3) FIG. 3 illustrates portions of the exemplary transmitter of FIG. 1 in accordance with aspects of the invention;

(4) FIG. 4 illustrates an FIR filter implementation of the combined RF equalizer and IQ imbalance correction (IQIC) stage of FIG. 3; and

(5) FIG. 5 illustrates exemplary pseudo code for joint IQ imbalance correction and equalization.

DETAILED DESCRIPTION

(6) FIG. 1 illustrates portions of an exemplary transmitter 100 in which aspects of the present invention may be employed. As shown in FIG. 1, the exemplary transmitter portion 100 comprises a channel filter and digital up conversion (DUC) stage 110, a crest factor reduction

(7) (CFR) stage 120, a digital pre-distortion (DPD) stage 130, an equalization stage 140 and an IQ Imbalance Correction stage 150. Generally, the channel filter and digital up conversion stage 110 performs channel filtering using, for example finite impulse response (FIR) filters and digital up conversion to convert a digitized baseband signal to an intermediate frequency (IF). As indicated above, the crest factor reduction stage 120 limits the peak-to-average ratio (PAR) of the transmitted signal. The digital pre-distortion stage 130 linearizes the power amplifier to improve efficiency. The equalization stage 140 employs RF channel equalization to mitigate channel impairments. The equalization stage 140 can be implemented, for example, as an FIR filter having 27 taps at a sampling rate of 307.2 MSPS.

(8) The present invention can be applied in handsets, base stations and other network elements.

(9) The IQ Imbalance Correction stage 150 corrects for amplitude and phase mismatch in an 1/Q (in-phase/quadrature-phase) signal pair, to avoid unwanted spectral components at the negative signal frequency. For a more detailed discussion of IQ Imbalance Correction, see for example, Lei Ding et al., Compensation of Frequency-Dependent Gain/Phase Imbalance in Predistortion Linearization Systems, IEEE Transactions on Circuits and Systems, Vol. 55, No. 1, 390-97 (February 2008), incorporated by reference herein.

(10) As previously indicated, RF equalization 140 and IQ imbalance correction 150 are typically performed using two separate hardware modules (as shown in FIG. 1). Aspects of the present invention provide joint techniques for IQ imbalance correction and RF equalization.

(11) IQ Imbalance Correction

(12) IQ imbalance correction (without frequency dependence) is typically expressed as follows:
y=(.sub.0x.sub.r+.sub.1x.sub.i)+j(.sub.2x.sub.r+.sub.3x.sub.i)(1)
where x is the input signal, and the 's are the IQ correction coefficients. Thus, IQ imbalance correction can be implemented using equation (1) as four real multipliers.

(13) Equation (1) can be restated as two complex filters x and x*, where the expression x* indicates x indicates a conjunction of x. Thus, IQ imbalance correction also be computed (with frequency dependence) using complex multiplications, as follows:
=a.Math.x+b.Math.x*(2)
=((a.sub.r+b.sub.r)x.sub.r(a.sub.ib.sub.i)x.sub.i)+j((a.sub.i+b.sub.i)x.sub.r(a.sub.rb.sub.r)x.sub.i)
where:
a.sub.r+b.sub.r=.sub.0
a.sub.rb.sub.r=.sub.3
a.sub.i+b.sub.i=.sub.2
a.sub.ib.sub.i=.sub.1, and

(14) $a_r=\frac{{}_0+{}_3}{2},a_i=\frac{{}_2+{}_1}{2},b_r=\frac{{}_0-{}_3}{2},b_i=\frac{{}_2-{}_1}{2},$

(15) Thus, for the case of frequency-dependent IQ imbalance compensation, IQ imbalance correction can be implemented using equation (2) as real FIR filters. The exemplary IQ Imbalance Correction stage 150 can be embodied as an FIR filter having five taps at a sampling rate of 307.2 MSPS. The exemplary IQ Imbalance Correction stage 150 implements equation (2) using four real multiply-accumulate (MACs) operations per tap.

(16) FIG. 2 illustrates an FIR filter implementation of the equalization stage 140 and an IQ Imbalance Correction stage 150 of FIG. 1. As shown in FIG. 2, the IQ Imbalance Correction stage 150 of FIG. 1 can be implemented as two parallel FIR filters 150-1, 150-2 in accordance with equation (2) as follows:
y.sub.IQIC(n)=.sub.k+0.sup.N1a.sub.kx(nk)+.sub.k=0.sup.N1b.sub.kx*(nk).(3)

(17) Combined Equalization and IQ Imbalance Correction (IQE)

(18) FIG. 3 illustrates portions of the exemplary transmitter 100 of FIG. 1 in accordance with aspects of the invention. In FIG. 2, the digital pre-distortion (DPD) stage 130 is an optional element that can be omitted. As shown in FIG. 3, the independent equalization stage 140 and an IQ Imbalance Correction stage 150 from FIG. 1 have been combined into a single RF equalizer and IQ imbalance correction (IQIC) stage 300.

(19) FIG. 4 illustrates an FIR filter implementation of the combined RF equalizer and IQ imbalance correction (IQIC) stage 300 of FIG. 3. As shown in FIG. 4, the combined RF equalizer and IQ imbalance correction (IQIC) stage 300 can be implemented as two parallel FIR filters 400-1, 400-2 as follows:

(20) $\begin{array}{cc}{y}_{\mathrm{IQE},n}=\underset{k=1}{\overset{M}{.Math.}}{c}_k.Math.x_{n-k}+\underset{k=1}{\overset{M}{.Math.}}{d}_k.Math.x_{n-k}^{*}& \left(4\right)\end{array}$
where h if the impulse response of the equalizer, c is the convolution of a and h and d is the convolution of b and h.

(21) For example, each FIR filter 400 can be implemented as an FIR filter having 32 taps at a sampling rate of 307.2 MSPS. The two parallel FIR filters 400-1, 400-2 can have complex inputs and complex coefficients. In the exemplary embodiment of FIG. 4, the input signal x is applied to the first FIR filter 400-1 and the conjugate x* of the input signal x is applied to the second FIR filter 400-2. Thus, IQ imbalance correction can be represented as 2 complex filters 400 with outputs combined by an adder 410. The equalizer 140 which precedes the IQ imbalance correction 150 in FIG. 1 can be combined with the IQ imbalance correction 150 by combining its impulse response with each of these two complex coefficient FIR filters.

(22) Thus, frequency-dependent I/Q imbalance correction is performed using two FIR filters with input x and conjugate of x where x is the input to I/Q imbalance correction processing.

(23) The combined RF equalizer and IQ imbalance correction (IQIC) stage 300 can be implemented in hardware or in software using a convolution instruction in a vector processor. For a more detailed discussion of a convolution instruction for a vector processor, see, for example, International Patent Application Serial No. PCT/US12/62182, entitled Vector Processor Having Instruction Set With Vector Convolution Function for FIR Filtering, filed contemporaneously herewith and incorporated by reference herein. The vector processors described in International Application Serial No. PCT/US12/62182 provide an enhanced instruction set that supports vector convolution functions and have a vector architecture that processes one or more vector inputs each comprised of a plurality of real or complex scalar numbers that are processed in parallel. If the vector processor is processing software code that includes a predefined instruction keyword corresponding to a vector convolution function and the appropriate operands for the function (i.e., the input samples), the instruction decoder must trigger an appropriate vector convolution functional unit(s) that processes the vector convolution instruction.

(24) FIG. 5 illustrates exemplary pseudo code 500 for joint IQ imbalance correction and equalization. The IQ imbalance correction portion is only used in zero-IF architectures, as would be apparent to a person of ordinary skill in the art. As shown in FIG. 5, the coefficients, c and d, are loaded into memory and the resultant filters are applied to the input data using the convolution function.

CONCLUSION

(25) While exemplary embodiments of the present invention have been described with respect to digital logic blocks and memory tables within a digital processor, as would be apparent to one skilled in the art, various functions may be implemented in the digital domain as processing steps in a software program, in hardware by circuit elements or state machines, or in combination of both software and hardware. Such software may be employed in, for example, a digital signal processor, application specific integrated circuit or micro-controller. Such hardware and software may be embodied within circuits implemented within an integrated circuit.

(26) Thus, the functions of the present invention can be embodied in the form of methods and apparatuses for practicing those methods. One or more aspects of the present invention can be embodied in the form of program code. for example, whether stored in a storage medium, loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a processor, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a device that operates analogously to specific logic circuits. The invention can also be implemented in one or more of an integrated circuit, a digital processor, a microprocessor, and a micro-controller.

(27) It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.