Low-power high-swing PAM4/PAM8 fast driver

Abstract

A driver for performing efficient low-power high-swing modulation, which comprises a first plurality of N controllable switching elements and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each divider consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of which jointly controlling the control inputs of a different pair; and a common output connecting between all N common points of all pairs of serially connected resistors forming the N voltage dividers.

Claims

1. A driver for performing efficient low-power high-swing modulation, comprising: a) a first plurality of N controllable switching elements having a common contact and a free contact and introducing low impedance between said contacts in response to a low control level and vice versa; b) a second plurality of N controllable switching elements having a common contact and a free contact and introducing high impedance between said contacts in response to a low control level and vice versa; c) a DC power supply (V.sub.DD) for feeding said driver, the positive port of which is connected to the common contact of said first plurality and the negative port of which is connected to the common contact of said second plurality; d) a plurality of N voltage dividers, each of which consisting of two serially connected resistors connecting between a free contact of a controllable switching element from said first plurality and a free contact of a controllable switching element from said second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; e) a plurality of N control inputs, each of which jointly controlling the control inputs of a different pair; and f) a common output connecting between all N common points of all pairs of serially connected resistors forming said N voltage dividers.

2. A driver according to claim 1, being implemented in a differential arrangement, such that the complimentary half of the driver receives the inverted version of the input signal.

3. A driver according to claim 1, being implemented as a single ended arrangement.

4. A driver according to claim 1, being implemented as a single ended PAM-4 modulation scheme, where N=2.

5. A driver according to claim 1, being implemented as a single ended PAM-8 modulation scheme, where N=3.

6. A driver according to claim 1, in which the resistance of each resistor forming a voltage divider is selected to maintain a predetermined total output resistance.

7. A driver according to claim 1, in which the output voltage swing ranges from 0 to V.sub.DD.

8. A driver according to claim 1, in which the controllable switching elements belong to a combination of P-type and N-type FET or bipolar transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other characteristics and advantages of the invention will be better understood through the following illustrative and non-limitative detailed description of preferred embodiments thereof, with reference to the appended drawings, wherein:

(2) FIG. 1 (prior art) illustrates an example of a traditional current mode PAM-4 driver;

(3) FIG. 2 shows a single ended PAM-4 driver circuit according to an embodiment of the invention;

(4) FIG. 3 shows a differential version of the PAM-4 driver of FIG. 2, according to an embodiment of the invention;

(5) FIG. 4 shows a single ended version of a PAM-8 driver, according to an embodiment of the invention;

(6) FIG. 5 shows eye diagram simulation results using the single ended PAM-4 driver of FIG. 2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(7) The present invention discloses a novel a fast driver for modulating data carrying sources, such as laser sources, which save DC power and efficiently exploits a given voltage swing. The proposed driver comprises a first plurality of N controllable switching elements having a common contact and a free contact and introducing low impedance between the contacts in response to a low control level and vice versa; a second plurality of N controllable switching elements having a common contact and a free contact and introducing high impedance between the contacts in response to a low control level and vice versa; a DC power supply (of voltage level V.sub.DD) for feeding the driver, the positive port of which is connected to the common contact of the first plurality and the negative port of which is connected to the common contact of the second plurality; a plurality of N voltage dividers, each of which consisting of two serially connected resistors connecting between a free contact of a controllable switching element from the first plurality and a free contact of a controllable switching element from the second plurality, where each two controllable switching elements connected by a voltage divider forming a pair; a plurality of N control inputs, each of which jointly controlling the control inputs of a different pair; and a common output connecting between all N common points of all pairs of serially connected resistors forming the N voltage dividers.

(8) FIG. 2 shows a single ended PAM-4 driver circuit according to an embodiment of the invention. Modulation is achieved by presenting different output voltage levels at the driver's output O, according to the binary combination value of the inputs D.sub.0 and D.sub.1. The driver circuit comprises of a supply voltage V.sub.DD, two P-Channel MOSFET transistors, M.sub.2 and M.sub.3, (which function as controllable switches) that enter a conducting state when low voltage (0 logic level) is applied to their gates, two N-Channel MOSFET transistors, M.sub.0 and M.sub.1 (controllable switches) that enter a conducting state when high voltage (1 logic level) is applied to their gates. The drains of two pairs of MOSFET transistors are connected by two pairs of series resistors (R1, R2) and (R3, R4), while the two pairs function as a voltage divider with a common point, from which the driver's output O is taken. The two P-Channel MOSFET transistors, M.sub.2 and M.sub.3 are fed by the supply voltage V.sub.DD and the sources of the two N-Channel MOSFET transistors, M.sub.0 and M.sub.1 are connected to ground.

(9) The resistors' values are determined so that in any modulation state, the driver will maintain an output resistance which will be essentially 50. An additional constraint on the resistors' values is the need of a voltage divider that will allow uniform distribution of the voltage range over the different output levels.

(10) The resulting voltage level at the output O can be calculated as a function of the inputs D.sub.0 and D.sub.1:

(11) If R.sub.0=R.sub.2=150 and R.sub.1=R.sub.3=75, the resulting output voltage is given by:

(12) TABLE-US-00002 D0 D1 M0 M1 M2 M3 O 0 0 OFF OFF ON ON V.sub.DD 0 1 ON OFF OFF ON V.sub.DD * 2/3 1 0 OFF ON ON OFF V.sub.DD * 1/3 1 1 ON ON OFF OFF GND
In the first state, when both input signals are in low state (logic 0), the two N-Channel MOSFET transistors M.sub.0 and M.sub.1 are in cutoff mode (OFF), effectively disconnecting the output from GND. The two P-Channel MOSFETs M.sub.2 and M.sub.3 are in saturation mode (ON). This causes connection of the output O to the power source V.sub.DD with no current flowing through the resistors. The output resistance in this case is the total resistance in the parallel connection of R.sub.2 and R.sub.3, which is 50.

(13) In the second state, D.sub.0 is in low state (logic 0), which causes M.sub.1 to be OFF (cutoff mode) and M.sub.3 to be ON, while D.sub.1 is in high state (logic 1) causing M.sub.0 to be ON and M.sub.2 to be OFF. The MOSFETs' states allow current to flow from V.sub.DD through M.sub.3, R.sub.3, R.sub.0 and M.sub.0 to GND. This presents the output with the voltage drop over R.sub.0 which is equal to V.sub.DD* due to the voltage divider the consists of R.sub.3 and R.sub.0. The output resistance in this state is the total resistance of the parallel connection of R.sub.3 and R.sub.0, which is 50.

(14) Similarly, in the third state D.sub.0 is in high state causing M.sub.1 to be ON and M.sub.3 to be OFF, while D.sub.1 is in low state causing M.sub.0 to be OFF and M.sub.2 to be ON. The MOSFETs' states cause current to flow from V.sub.DD through M.sub.2, R.sub.2, R.sub.1, and M.sub.1 to GND. The output voltage is the voltage drop over R.sub.1 which is equal to V.sub.DD* due to the voltage division of R.sub.2 and R.sub.1. The output resistance in this state is the total resistance of the parallel connection of R.sub.2 and R.sub.1, which is 50.

(15) In the fourth state both D.sub.0 and D.sub.1 are in high state (logic 1), causing the two N-Channel MOSFETs, M.sub.1 and M.sub.0, to be ON and the two P-Channel MOSFETs, M.sub.3 and M.sub.2 to be OFF. This causes the output to be electrically connected to the GND, and the output resistance to be 50.

(16) The driver implementation illustrated in FIG. 2 does not require any current sources, causing high efficiency and low power consumption for the same output swing. Also, the proposed driver has low common mode noise, since it does not depend on current sources linearity.

(17) The whole power supply voltage range is utilized for output levels, thereby improving efficiency and allowing uniform distribution of the output voltage levels over the overall voltage range V.sub.DD. Also, two (out of 4) states consume no static DC current (with no load). In the proposed implementation, the switching transistors can be small since Vbs=0 which leads to less capacitance, higher speed and less dynamic power consumption. The driver even saves power when used as single ended driver.

(18) FIG. 3 shows a differential version of the PAM-4 driver of FIG. 2, according to an embodiment of the invention. The differential driver is divided to two independent single ended sides. Each side of the driver receives either the positive or the negative reflection of the input signals D.sub.0 and D.sub.1. Each side produces an output that corresponds to its inputs, i.e. O.sub.N refers to D.sub.1.sub.N and to D.sub.0.sub.N while O.sub.P refers to D.sub.1.sub.P and to D.sub.0.sub.P. Each of the output resistances is kept 50.

(19) FIG. 4 shows a single ended version of a PAM-8 driver, according to an embodiment of the invention. Similar to the single ended PAM-4 driver of FIG. 2, the conductivity (ON/OFF) of the MOSFETs in the PAM-8 is controlled by the values of the input signal (D.sub.0, D.sub.1 and D.sub.2). The input signals force different combinations of conductivity allowing, once again, uniform distribution of the output voltage levels over the overall voltage range.

(20) In the example of the fifth state, for the sake of demonstrating, D.sub.0=1, D.sub.1=0, D.sub.2=1. In this example M.sub.0, M.sub.3 and M.sub.4 will be on, while M.sub.1, M.sub.2 and M.sub.5 will be off. This will allow current to flow from V.sub.DD through M.sub.3 and R.sub.3, split between R.sub.0 and R.sub.4, and finally end up at GND. The output voltage in this case would be the voltage drop across the total resistance of the parallel connection of R.sub.4 and R.sub.0. The total resistance value is

(21) $R_T=\frac{350*87.5}{350+87.5}=70,$
and the output voltage value is

(22) $O=V_{\mathrm{DD}}*\frac{R_T}{R_T+R_3}=V_{\mathrm{DD}}*\frac{70}{70+175}=V_{\mathrm{DD}}*\frac{2}{7},$
similar to the PAM-4 implementation (of FIG. 2). The output resistance in this example is R.sub.3R.sub.T which is equal to

(23) $175.Math..Math.70=\frac{175*70}{175+70}=50.$
The output resistance in this circuit is kept 50 in all states due to the values of and the connection between resistors R.sub.0 to R.sub.5. By adding another pair of switches and adjusting the resistors values, the design can support PAM8 while keeping the advantages of PAM4 implementation, illustrated in FIG. 2.

(24) FIG. 5 shows eye diagram simulation results using the single ended PAM-4 driver of FIG. 2, with estimated layout parasitic, package model and 20 GHz output signal.

(25) The above examples and description have of course been provided only for the purpose of illustration, and are not intended to limit the invention in any way. As will be appreciated by the skilled person, the invention can be carried out in a great variety of ways, employing more than one technique from those described above, other than used in the description, all without exceeding the scope of the invention.