Semiconductor process for treating metal gate

Abstract

A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H.sub.2/N.sub.2 plasma treatment process is performed to reduce the main conductive material.

Claims

1. A semiconductor process for treating a metal gate, comprising: providing a metal gate comprising a main conductive material on a substrate; performing a H2/N2 plasma treatment process to deoxidize the main conductive material; and forming a contact plug contacting the main conductive material after the H2/N2 plasma treatment process is performed.

2. The semiconductor process for treating a metal gate according to claim 1, wherein the main conductive material comprises a metal oxide layer at a top surface of a metal layer.

3. The semiconductor process for treating a metal gate according to claim 2, wherein the metal oxide layer is reduced into a part of the metal layer while the H2/N2 plasma treatment process is performed.

4. The semiconductor process for treating a metal gate according to claim 3, wherein the main conductive material comprises aluminum or tungsten.

5. The semiconductor process for treating a metal gate according to claim 4, wherein the metal oxide layer comprises an aluminum oxide layer while the metal layer comprises an aluminum layer.

6. The semiconductor process for treating a metal gate according to claim 1, wherein the H2/N2 plasma treatment process comprises supplying a gas mixture of H2/N2 with a ratio of 2-3.5%.

7. The semiconductor process for treating a metal gate according to claim 6, wherein the H2/N2 plasma treatment process comprises supplying a gas mixture of H2/N2 with a ratio of 2.9%.

8. The semiconductor process for treating a metal gate according to claim 1, wherein the H2/N2 plasma treatment process comprises inserting an N2 gas while supplying a gas mixture of H2/N2.

9. The semiconductor process for treating a metal gate according to claim 8, wherein the H2/N2 plasma treatment process comprises inserting an N2 gas of 1900 sccm while supplying a gas mixture of H2/N2 with a ratio of 4% of 5000 sccm.

10. The semiconductor process for treating a metal gate according to claim 1, further comprising: forming a dielectric layer on the metal gate and patterning the dielectric layer to expose the main conductive material by using a photoresist layer and then removing the photoresist layer before the H2/N2 plasma treatment process is performed.

11. The semiconductor process for treating a metal gate according to claim 10, further comprising: performing a strip treatment process to remove the photoresist layer before the H2/N2 plasma treatment process is performed.

12. The semiconductor process for treating a metal gate according to claim 11, wherein the strip treatment process comprises an O2 strip treatment process.

13. The semiconductor process for treating a metal gate according to claim 11, wherein the strip treatment process comprises a first H2/N2 plasma treatment process having higher H2/N2 ratio than the H2/N2 plasma treatment process.

14. The semiconductor process for treating a metal gate according to claim 13, wherein the first H2/N2 plasma treatment process has a H2/N2 ratio of 4%.

15. The semiconductor process for treating a metal gate according to claim 1, further comprising: forming a source/drain in the substrate beside the metal gate; and forming S/D contact plugs directly contacting the source/drain while the contact plug contacting the main conductive material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1-8 schematically depict cross-sectional views of a semiconductor process for treating a metal gate according to an embodiment of the present invention.

DETAILED DESCRIPTION

(2) A semiconductor process of the present invention is applied to a CMOS transistor having a PMOS transistor paired with an NMOS transistor in the following embodiment. However, the present invention is not restricted thereto. The present invention can also be applied to a MOS transistor such as a planar MOS transistor, a non-planar MOS transistor, or others, depending upon practical requirements.

(3) FIGS. 1-8 schematically depict cross-sectional views of a semiconductor process for treating a metal gate according to an embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate. Isolation structures 10 may be formed in the substrate 110 to electrically isolate each transistor. The isolation structures 10 may be shallow trench isolation (STI) structures, which may be formed by a shallow trench isolation process, and the forming method is known in the art, and will not be described herein, but it is not limited thereto. In this embodiment, the substrate 110 is divided into a first area A and a second area B isolated by the isolation structures 10; the first area A serves as a PMOS transistor area while the second area B serves as an NMOS transistor area, but it is not limited thereto.

(4) A buffer layer (not shown), agate dielectric layer (not shown), a barrier layer (not shown), a sacrificial electrode layer (not shown) and a cap layer (not shown) are sequentially formed from bottom to top and cover the substrate 110. The cap layer (not shown), the sacrificial electrode layer (not shown), the barrier layer (not shown), the gate dielectric layer (not shown) and the buffer layer (not shown) are patterned to form buffer layers 122, gate dielectric layers 124, barrier layers 126, sacrificial electrode layers 128 and cap layers 129 on the substrate 110. This means that sacrificial gates G1 and G2 including the buffer layers 122, the gate dielectric layers 124, the barrier layers 126, the sacrificial electrode layers 128 and the cap layers 129 are formed in the first area A and the second area B respectively.

(5) Each of the buffer layers 122 may be an oxide layer, which may be formed through a chemical oxide process or a thermal oxide process, but it is not limited thereto. The buffer layer 122 is located between each of the gate dielectric layers 124 and the substrate 110 to buffer the gate dielectric layer 124 and the substrate 110. A gate-last for high-k first process is applied in this embodiment, so that each of the gate dielectric layers 124 is a gate dielectric layer having a high dielectric constant, which may be the group selected from hafnium oxide (HfO.sub.2), hafnium silicon oxide (HfSiO.sub.4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), tantalum oxide (Ta.sub.2O.sub.5), yttrium oxide (Y.sub.2O.sub.3), zirconium oxide (ZrO.sub.2), strontium titanate oxide (SrTiO.sub.3), zirconium silicon oxide (ZrSiO.sub.4), hafnium zirconium oxide (HfZrO.sub.4), strontium bismuth tantalite (SrBi.sub.2Ta.sub.2O.sub.9, SBT), lead zirconate titanate (PbZr.sub.xTi.sub.1-xO.sub.3, PZT) and barium strontium titanate (Ba.sub.xSr.sub.1-xTiO.sub.3, BST), but it is not limited thereto. In another embodiment, as agate-last for high-k last process is applied, each of the gate dielectric layers 124 will be removed in later processes and then a gate dielectric layer having a high dielectric constant is formed. Therefore, the material of the gate dielectric layer 124 may be just a sacrificial material suitable for being removed in later processes. Each of the barrier layers 126 is located on each of the gate dielectric layers 124 to prevent above disposed metals from diffusing downwards to the gate dielectric layer 124 and from polluting the gate dielectric layer 124. Each of the barrier layers 126 may be a single layer structure or a multilayer structure composed of tantalum nitride (TaN) or titanium nitride (TiN) etc. Each of the sacrificial electrode layers 128 may be made of polysilicon, but it is not limited thereto. Each of the cap layers 129 may be a single layer or a multilayer composed of a nitride layer or an oxide layer etc used for being a patterned hard mask, but it is not limited thereto.

(6) An offset (not shown) may be optionally formed on the substrate 110 beside each of the sacrificial gates G1 and G2, wherein the offset (not shown) may be a nitride layer, an oxide layer or an oxynitride layer etc. First spacers 132/134 are formed on the substrate 110 beside the sacrificial gates G1 and G2 respectively to define the positions of lightly doped source/drains in the substrate 110 beside the first spacers 132/134. Two lightly doped source/drains 136/138 are then formed in the substrate 110 beside the two first spacers 132/134 respectively, wherein as the first area A is a PMOS transistor area, the dopants of the lightly doped source/drain 136 may be trivalent ions such as boron ions; as the second area B is a NMOS transistor area, the dopants of the lightly doped source/drain 138 may be pentavalent ions such as phosphorus, depending upon practical needs.

(7) Then, main spacers 142/144 may be formed on the substrate 110 beside the first spacers 132/134 respectively. Each of the main spacers 142/144 may be a single layer spacer or a multilayer spacer, and its cross-sectional profile depends upon practical needs and processing steps. In this embodiment, the main spacers 142/144 are single layers. A source/drain 146/148 is formed in the substrate 110 beside each of the main spacers 142/144, wherein as the first area A is a PMOS transistor area, the dopants of the source/drain 146 may be trivalent ions such as boron ions; as the second area B is a NMOS transistor area, the dopants of the source/drain 148 may be pentavalent ions such as phosphorus, depending upon practical needs.

(8) Optionally, an epitaxial structure 152/154 is formed in the substrate 110 beside each of the main spacers 142/144 as well after the source/drains 146/148 are formed. As the first area A is a PMOS transistor area, the epitaxial structure 152 may be composed of silicon germanium or others; as the second area B is a NMOS transistor area, the epitaxial structure 154 may be composed of silicon carbide or others, depending upon practical needs.

(9) In this case, the epitaxial structures 152/154 overlap the source/drains 146/148 respectively with different overlapping ranges, wherein the epitaxial structure 152 overlaps the whole source/drain 146 and exceeds the source/drain 146, and the epitaxial structure 154 completely overlaps the source/drain 148, but it is not limited thereto. The order of forming the lightly doped source/drains 136/138, the source/drains 146/148 and the epitaxial structures 152/154 is not restricted thereto.

(10) A contact etch stop layer 12 may be optionally formed to cover the sacrificial gates G1 and G2 and the substrate 110. The contact etch stop layer may be a nitride layer or a doped nitride layer having a capability of inducing stresses in the substrate 110 under the sacrificial gates G1 and G2, but it is not limited thereto. A dielectric layer 14 is formed to entirely cover the contact etch stop layer 12, the sacrificial gates G1 and G2 and the substrate 110. In this embodiment, the dielectric layer 14 is an interdielectric layer made of oxide, but it is not limited thereto.

(11) Thereafter, the dielectric layer 14 is planarized to form a dielectric layer 14a having a flat surface S1 and expose the sacrificial gates G1 and G2, and then the cap layers 129, the sacrificial electrode layers 128 are removed to form recesses R1/R2 while the buffer layers 122, the gate dielectric layers 124 and the barrier layers 126 are preserved as a gate last for a high-k first process is applied in this embodiment, as shown in FIG. 2.

(12) As shown in FIG. 3, metal gates M1/M2 are formed to replace the sacrificial gates G1 and G2 (shown in FIG. 1) by processes such as a replacement metal gate (RMG) process. Thus, multi-metal layers fill into the recesses R1/R2, such that a first work function layer 162a, a second work function layer 162b, a selective buffer layer 164 and a main conductive material 166 may be formed in and fill the recess R1 while a second work function layer 162b, a selective buffer layer 164 and a main conductive material 166 may be formed in and fill the recess R2, thereby forming the metal gates M1/M2. The step of forming the metal gates M1/M2 are known in the art and are not described herein.

(13) The first work function layer 162a may be a single layer or a multilayer structure, composed of titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN) suited for a PMOS transistor, and the second work function layer 162b may be a single layer or a multilayer structure, composed of tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl) or aluminum titanium nitride (TiAlN) suited for a NMOS transistor; the selective barrier layer 164 may be a stacked structure composed of titanium nitride (TiN) or tantalum nitride (TaN); the main conductive material 166 may be composed of low resistivity materials such as aluminum, tungsten, titanium aluminum (TiAl) alloy, cobalt tungsten phosphide (CoWP), but the present invention is not restricted thereto.

(14) As shown in FIG. 4, a dielectric layer 170 may be formed on the metal gates M1/M2 and the dielectric layer 14a. The dielectric layer 170 may include an oxide layer 172 by using tetraethylorthosilicate (TEOS) as silicon source and an interdielectric layer 174 composed of oxide from bottom to top, but it is not limited thereto.

(15) As shown in FIG. 5, the dielectric layer 170 is then patterned to expose the main conductive materials 166. In this embodiment, the dielectric layer 170 is patterned by using a photoresist Q formed by covering and patterning, but it is not limited thereto. Since the main conductive materials 166 are exposed (to the air) while the dielectric layer 170 is patterned, the main conductive materials 166 are oxidized, thereby main conductive materials 166 being formed, such that a metal oxide layer 166b is formed at a top surface S2 of a metal layer 166a, wherein the metal oxide layer 166b and the metal layer 166a have common metal atoms. In one case, as the metal layer 166a is an aluminum layer, the metal oxide layer 166b is an aluminum oxide layer, but it is not limited thereto.

(16) In this embodiment, the dielectric layer 170 is patterned to form contact holes V1/V2. That is, the contact holes V1 expose the metal gates M1/M2, and the contact holes V2 expose the source/drains 146/148. More precisely, the dielectric layer 170 and the dielectric layer 14a are patterned by one single process to form the contact holes V1/V2 at the same time, but it is not limited thereto.

(17) Thereafter, a strip treatment process P1 is performed to remove the photoresist layer Q, as shown in FIG. 6. Preferably, the strip treatment process P1 is an O.sub.2 strip treatment process, but it is not limited thereto. In some cases, the strip treatment process P1 may be a first H.sub.2/N.sub.2 plasma treatment process, which supplies a gas mixture of H.sub.2/N.sub.2 into a processing chamber, and then the gas mixture of H.sub.2/N.sub.2 is dissociated to from active H.sub.2/N.sub.2 radical plasma to remove the photoresist layer Q, but it is not limited thereto. In this case, the first H.sub.2/N.sub.2 plasma treatment process has a H.sub.2/N.sub.2 ratio of 4%.

(18) A H.sub.2/N.sub.2 plasma treatment process P2 is performed to reduce (or deoxidize) the main conductive materials 166 after the strip treatment process P1 is performed, therefore main conductive materials 166c are formed, as shown in FIG. 7. The main conductive materials 166c are preferably common to the metal layers 166a; that is, the main conductive materials 166c are only composed of metal such as aluminum. More precisely, the metal oxide layers 166b of FIG. 6 are reduced (or deoxidized) into a part of the metal layers 166a of FIG. 6. Due to the main conductive materials 166 being reduced, ohmic contact resistance between the main conductive materials 166c and later formed contact plugs can be reduced.

(19) In a preferred embodiment, the H.sub.2/N.sub.2 plasma treatment process P2 supplies a gas mixture of H.sub.2/N.sub.2 with a ratio of 2-3.5%. In a still preferred embodiment, the H.sub.2/N.sub.2 plasma treatment process P2 supplies a gas mixture of H.sub.2/N.sub.2 with a ratio of 2.9%. In one case, the H.sub.2/N.sub.2 plasma treatment process P2 inserts an N2 gas while supplying a gas mixture of H.sub.2/N.sub.2 for adjusting the concentration of the total gas mixture of H.sub.2/N.sub.2. For example, the H.sub.2/N.sub.2 plasma treatment process P2 inserts an N.sub.2 gas of 1900 sccm while supplying a gas mixture of H.sub.2/N.sub.2 with a ratio of 4% of 5000 sccm, but it is not limited thereto.

(20) It is emphasized that, the first H.sub.2/N.sub.2 plasma treatment process P1 used for removing the photoresist layer Q has higher H.sub.2/N.sub.2 ratio than the H.sub.2/N.sub.2 plasma treatment process P2 used for reducing (or deoxidizing) the main conductive materials 166. As the H.sub.2/N.sub.2 ratio is lower, the dissociation rate of a gas mixture of H.sub.2/N.sub.2 (dissociated to active H.sub.2/N.sub.2 radical plasma) increases, hence the H.sub.2/N.sub.2 plasma treatment process P2 can reduce the main conductive materials 166.

(21) As shown in FIG. 8, contact plugs C1/C2 fill the contact holes V1/V2. That is, the contact plugs C1 fill the contact holes V1 and contact the main conductive materials 166c, and the contact plugs C2 fill the contact holes V2 and being S/D contact plugs contact the source/drains 146/148. In this case, the contact plugs C1/C2 are formed simultaneously and composed of same materials such as copper, tungsten, or others, but it is not limited thereto. Preferably, each of the contact plugs C1/C2 has a barrier layer C11/C21 covering each of the contact holes V1/V2 and a low resistivity material C12/C22 filling each of the contact holes V1/V2. The barrier layer C11/C21 may be a single layer or a multilayer structure composed of tantalum nitride (TaN), titanium nitride (TiN) or others; the low resistivity material C12/C22 may be composed of low resistivity materials such as copper, aluminum, tungsten, titanium aluminum (TiAl) alloy, cobalt tungsten phosphide (CoWP) or others.

(22) Accordingly, the semiconductor process of the present invention for treating metal gates is applied both in the first area A and the second area B at the same time in this embodiment. This means the semiconductor process of the present invention treats the PMOS transistor area and the NMOS transistor for forming a CMOS transistor at the same time. However, the semiconductor process of the present invention can treat metal gates selectively, individually or sequentially, depending upon practical requirements. In addition, the semiconductor process of the present invention can also be applied in other semiconductor devices for reducing oxide of conductors such as metal oxides.

(23) To summarize, the present invention provides a semiconductor process for treating a metal gate, which performs a H.sub.2/N.sub.2 plasma treatment process to reduce metal gates, especially for main conductive materials of the metal gates exposed while forming contact holes in a dielectric layer for filling contact plugs therein. Therefore, the present invention reduces ohmic contact resistance between the metal gates and the contact plugs. Preferably, the H.sub.2/N.sub.2 plasma treatment process supplies a gas mixture of H.sub.2/N.sub.2 with a ratio of 2-3.5%. Still preferably, the H.sub.2/N.sub.2 plasma treatment process supplies a gas mixture of H.sub.2/N.sub.2 with a ratio of 2.9%. In some case, the H.sub.2/N.sub.2 plasma treatment process can be processed by inserting an N.sub.2 gas while supplying a gas mixture of H.sub.2/N.sub.2 to adjust the concentration of a total gas mixture of H.sub.2/N.sub.2, but it is not limited thereto.

(24) The H.sub.2/N.sub.2 plasma treatment process is performed after a strip treatment process serving as removing a photoresist layer for patterning the dielectric layer having contact holes therein. The strip treatment process is preferably an O.sub.2 strip treatment process, a first H.sub.2/N.sub.2 plasma treatment process, or others. The first H.sub.2/N.sub.2 plasma treatment process has higher H.sub.2/N.sub.2 ratio than the H.sub.2/N.sub.2 plasma treatment process applied for reducing the metal gates. That is, the first H.sub.2/N.sub.2 plasma treatment process may have a H.sub.2/N.sub.2 ratio of 4% while the H.sub.2/N.sub.2 plasma treatment process supplies a gas mixture of H.sub.2/N.sub.2 with a ratio of 2-3.5%, but it is not limited thereto.

(25) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.