HETEROJUNCTION FIELD-EFFECT TRANSISTOR

Abstract

A process for fabricating a heterojunction field-effect transistor including a semiconductor structure made up of superposed layers, including: providing on a substrate layer (1) a buffer layer (2), a channel layer (3) and a barrier layer (4), the layers being made of materials having hexagonal crystal structures of the Ga.sub.(1-p-q)Al.sub.(p)In.sub.(q)N type; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing by high-temperature epitaxy a semiconductor material (6, 6) having a hexagonal crystal structure, namely Ga.sub.(1-x-y)Al.sub.(x)In.sub.(y)N, doped with germanium, on a growth zone defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy, and a gate electrode (13) in a location outside of the growth zone.

Claims

1. Process for fabricating a heterojunction field-effect transistor comprising a semiconductor structure made up of superposed layers, comprising: a) providing on a substrate layer (1): a buffer layer (2) composed of a semiconductor material having a hexagonal crystal structure, namely Ga.sub.(1-x-y)Al.sub.(x)In.sub.(y)N, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1; a channel layer (3) on the buffer layer, this channel layer being composed of a material having a hexagonal crystal structure, namely Ga.sub.(1-z-w)Al.sub.(z)In.sub.(w)N, where z and w may be comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from x or y, respectively; and a barrier layer (4) on this channel layer, this barrier layer being composed of a material having a hexagonal crystal structure, namely Ga.sub.(1-z-w)Al.sub.(z)In.sub.(w)N, where z and w may be comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from z or w, respectively; b) depositing a dielectric masking layer (5) on the barrier layer; c) forming an opening in the dielectric masking layer; d) growing by high-temperature epitaxy a semiconductor material (6, 6) having a hexagonal crystal structure, namely Ga.sub.(1-x-y)Al.sub.(x)In.sub.(y)N, doped with germanium, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1, on a growth zone defined by the opening formed in the masking layer; e) depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy in step d); and f) depositing a gate electrode (13) in a location outside of the growth zone.

2. Process according to claim 1, in which, a metalorganic vapour phase epitaxy technique is employed in step d).

3. Process according to claim 1, in which, a molecular beam epitaxy technique is employed in step d).

4. Process according to claim 1, in which the material deposited by epitaxy in step d) is germanium-doped GaN.

5. Process according to claim 1, in which, step e) of depositing the contact electrode is carried out without an alloying anneal.

6. Process according to claim 1, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

7. Heterojunction field-effect transistor comprising a semiconductor structure made up of superposed layers, comprising in the stacking order on a substrate layer (1): a buffer layer (2) composed of a material having a hexagonal crystal structure, namely Ga.sub.(1-x-y)Al.sub.(x)In.sub.(y)N, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1; a channel layer (3) on the buffer layer, this channel layer being composed of a material having a hexagonal crystal structure, namely Ga.sub.(1-z-w)Al.sub.(z)In.sub.(w)N, where z and w may be comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from x or y, respectively; and a barrier layer (4) on this channel layer, this barrier layer being composed of a material having a hexagonal crystal structure, namely Ga.sub.(1-z-w)Al.sub.(z)In.sub.(w)N, where z and w may be comprised between 0 inclusive and 1 inclusive, the sum z+w being lower than or equal to 1, at least one of z and w being different from z or w, respectively; a layer of epitaxial material (6, 6), deposited by high-temperature epitaxy on a growth zone corresponding to the location of an opening formed in a dielectric masking layer (5), this growth material having a hexagonal crystal structure and being composed of Ga.sub.(1-x-y)Al.sub.(x)In.sub.(y)N doped with germanium, where x and y are comprised between 0 inclusive and 1 inclusive, the sum x+y being lower than or equal to 1; and a contact electrode (15, 16) on the layer of growth material and a gate electrode (13) in a location outside of the growth zone.

8. Monolithic microwave integrated circuit comprising a transistor according claim 7.

9. Process according to claim 2, in which the material deposited by epitaxy in step d) is germanium-doped GaN.

10. Process according to claim 3, in which the material deposited by epitaxy in step d) is germanium-doped GaN.

11. Process according to claim 2, in which, step e) of depositing the contact electrode is carried out without an alloying anneal.

12. Process according to claim 3, in which, step e) of depositing the contact electrode is carried out without an alloying anneal.

13. Process according to claim 4, in which, step e) of depositing the contact electrode is carried out without an alloying anneal.

14. Process according to claim 2, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

15. Process according to claim 3, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

16. Process according to claim 4, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

17. Process according to claim 5, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

18. Process according to claim 9, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

19. Process according to claim 10, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

20. Process according to claim 11, in which step d) is carried out at a temperature strictly higher than 960 C. and lower than or equal to 1150 C.

Description

[0064] The invention will be better understood with reference to the figures, which illustrate nonlimiting embodiments given by way of example.

[0065] FIGS. 1 to 5 are very schematic cross-sectional views of one example transistor during fabrication, according to one example process according to one embodiment of the invention.

[0066] FIG. 6 is a very schematic cross-sectional view of an example transistor according to one embodiment of the invention.

[0067] Identical references will be used from one figure to another to designate identical or similar elements.

[0068] With reference to FIG. 1, provision is made to superpose, on a substrate 1 for example composed of silicon, semiconductor layers having hexagonal crystal structures, said layers being composed of III-V materials, the atoms from column V of the periodic table being nitrogen atoms, and the atoms from column III of this table being chosen from gallium, aluminium and indium.

[0069] This superposition comprises: [0070] a buffer layer 2, for example composed of undoped Ga.sub.0.9Al.sub.0.1N; [0071] a channel layer 3, for example composed of undoped GaN; [0072] a barrier layer 4, for example composed of undoped MN; and [0073] a dielectric masking layer 5, for example composed of SiN.

[0074] In FIG. 1, an etching step, carried out in a way known per se and involving an additional masking layer (not shown because removed after the etching), was used to form openings in the masking layer 5, so that there only remains a central portion of this layer 5.

[0075] With reference to FIG. 2, an etching step, carried out in a way known per se, is used to remove material level with the openings formed in the masking layer 5, so as to remove the portion of the barrier layer 4 corresponding to these locations. Thus only the portion of the barrier layer 4 corresponding to the location of the central portion of the layer 5 is retained. The openings thus defined now extend thicknesswise as far as the channel layer 3.

[0076] With reference to FIG. 3, germanium-doped growth material 6, 6 is grown using an MOVPE technique in the locations corresponding to the openings in the masking layer 5. The growth material has a hexagonal crystal structure and is composed of GaN doped N.sup.+ with germanium.

[0077] The choice of germanium allows relatively sharply defined interfaces to be obtained between the portions, 6, 6 and 5.

[0078] This step is carried out at a high temperature, so as to obtain substantial mass transport. The seeds may for example be liable to migrate over distances of about 10 m. In so far as the distance between drain and source locations is in general smaller than one m, it will be understood that selectivity is ensured. The material of seeds that would otherwise have formed on the layer 5 is thus transported by diffusion over the surface of the layer 5 toward the layers 6 and 6, where incorporation is thermodynamically more favourable. This high-temperature process makes it possible to limit, and advantageously prevent, the formation of seeds on the surface of the layer 5.

[0079] Since the growth material is doped with germanium, the mechanical stresses are lower than with a Si-doped material, and the morphology problems liable to be encountered in the case of silicon doping are not observed. The thickness of the growth layers 6, 6 is relatively uniform over the entire wafer. The edges of the zones 6, 6 are relatively clearly defined. Reproducibility is also satisfactory.

[0080] A high doping of these localized epitaxial zones 6, 6 is advantageous as this makes it possible to avoid the need for alloying to produce a good ohmic contact having a low contact resistance with the electrodes, and the improvement in and better control of the morphology therefore allows dimensions to be even further decreased.

[0081] To do this, the following conditions will possibly be implemented in the localized epitaxy step: [0082] vector gas: H.sub.2 and/or N.sub.2 and/or another inert gas; [0083] temperature between 700 and 1150 C. and advantageously between 1000 and 1150 C.; [0084] reactants: trimethylgallium (and/or other Ga organometallics) and NH.sub.3 (and/or other N-providing molecules, such as hydrazine, amines, etc.); [0085] dopant gas: GeH.sub.4 (and/or organo-germanium compounds or halogenides of germanium).

[0086] The proportions of the reactants and dopants are chosen so as to obtain a material containing 10.sup.18 germanium atoms per cubic centimetre or more, for example 10.sup.20 or 10.sup.21 germanium atoms per cubic centimetre.

[0087] Next, as is known per se, contacts 15, 16 are deposited on these layers of growth material 6, 6. More precisely, each contact 15, 16 comprises: [0088] a tie layer 7, 10, for example a layer of titanium, deposited on the epitaxial material; [0089] a barrier layer 8, 11, for example a layer of platinum, deposited on the corresponding tie layer 7, 10; and [0090] a conduction layer 9, 12, for example a layer of gold, deposited on the corresponding barrier layer 8, 11.

[0091] It may be noted that the source and drain contacts 15, 16 are deposited without an anneal.

[0092] Next, with reference to FIG. 5, one portion of the masking layer 5 is etched so that only two portions 5A, 5B of this masking layer SiN remain, and in the new opening thus defined a metal gate contact 13 is deposited.

[0093] Alternatively, provision could of course be made to remove completely the masking layer 5 before depositing the gate contact.

[0094] Again alternatively, it is also possible to leave all or some of the SiN masking layer 5 in place, and to deposit the gate electrode thereon.

[0095] As is known per se, this gate contact may also be made up of a plurality of layers (tie, barrier and conduction layers), not shown. For example, provision could be made for a nickel tie layer and a gold conduction layer.

[0096] The transistor thus obtained may contain germanium-doped portions 6, 6 of relatively high quality.

[0097] The materials of the channel and barrier layers 2, 3 are chosen so as to form a two-dimensional electron gas, represented in FIG. 5 by the zone referenced 14. Doping the layers 6, 6 with germanium allows a relatively sharply defined junction to be obtained between the layers 6, 3, 4 and 6, 3, 4, which contributes to improving the performance of the transistor.

[0098] This transistor may allow a MMIC circuit having a higher performance to be produced.

[0099] With reference to FIG. 6, the HEMT shown was obtained by etching the material corresponding to the locations defined by the dielectric masking layer corresponding to the reference 5 in FIGS. 1 to 4 under conditions such that the opening thus defined extends as far as the buffer layer 2. In other words, said opening extends through the channel layer 3.

[0100] The epitaxial growth material is then deposited at high temperature.

[0101] As has been expressly shown in this Figure, the growth layers 6, 6 thus obtained have slightly oblique walls 61 that are set back relative to the masking layer.

[0102] The layers 6, 6 may have a thickness such that they extend heightwise beyond the masking layer, without running the risk of covering the latter.

[0103] It is thus possible to choose to deposit, at the start of the process, a relatively thin masking layer.