METHOD FOR LATERAL PATTERNING OF A PATTERN LAYER WITH THREE-DIMENSIONAL PATTERN ELEMENTS, AND SEMICONDUCTOR DEVICE

Abstract

The invention relates to a method for laterally structuring a structured layer (2) with a plurality of three-dimensional structure elements (20), having the following steps: a) providing the structured layer with the three-dimensional structure elements; b) forming a laterally structured covering layer (3) on the structured layer in order to define at least one structured layer region (4) to be removed; and c) removing the structured layer region to be removed by means of a force acting on the structure elements in the region to be removed. The invention further relates to a semiconductor component (1).

Claims

1. Method for lateral patterning of a pattern layer with a plurality of three-dimensional pattern elements, having the steps: a) provision of the pattern layer with the three-dimensional pattern elements; b) formation of a laterally patterned covering layer on the pattern layer to determine at least one region to be removed of the pattern layer; and c) removal of the region to be removed of the pattern layer by means of a force acting on the pattern elements in the region to be removed.

2. Method according to claim 1, wherein the three-dimensional pattern elements have a maximum extent in at least one lateral direction of at most 5 m.

3. Method according to claim 2, wherein the extent of the pattern elements in a direction perpendicular to the lateral direction is at least twice as great as the maximum extent in the lateral direction.

4. Method according to claim lone of the preceding claims, wherein in step b) the region to be removed is free of the covering layer.

5. Method according to claim 4, wherein the applied force is exerted by a medium introduced with overpressure or by mechanical wiping.

6. Method according to claim 4, wherein the applied force is exerted by ultrasound or vibration.

7. Method according to claim 1, wherein in step b) the region to be removed is covered by the covering layer.

8. Method according to claim 7, wherein the covering layer is peeled off together with the pattern elements in the region to be removed.

9. Method according to claim 7, wherein the applied force is exerted by a thermally induced change in extent of the covering layer.

10. Semiconductor device with a pattern layer with a plurality of three-dimensional pattern elements, wherein, in plan view onto the semiconductor device, the pattern layer is subdivided into a device region and a stripped region, wherein the stripped region comprises remnants of the pattern elements with breakage traces.

11. Semiconductor device according to claim 10, wherein the extent of the pattern elements in the vertical direction in the stripped region amounts to at most 30% of the vertical extent of the pattern elements in the device region.

12. Semiconductor device according to claim 10, wherein the stripped region is a mesa trench of the semiconductor device or a region on which a contact area for external contacting is arranged.

13. Semiconductor device according to claim 10, wherein the pattern elements comprise a first semiconductor layer of a first conduction type and a second semiconductor layer of a second conduction type different from the first conduction type and wherein the second semiconductor layer covers the side faces of the first semiconductor layer at least in places.

14. Semiconductor device according to claim 10, wherein the pattern layer contains a III-V compound semiconductor material.

15. (canceled)

16. Method for producing a semiconductor device comprising of a pattern layer with a plurality of three-dimensional pattern elements, having the steps: a) provision of the pattern layer with the three-dimensional pattern elements; b) formation of a laterally patterned covering layer on the pattern layer to determine at least one region to be removed of the pattern layer; and c) removal of the region to be removed of the pattern layer by means of a force acting on the pattern elements in the region to be removed, so that the pattern elements in the region to be removed brake and the pattern layer in a top view is subdivided in a device region and a stripped region.

Description

[0037] The above-described method for lateral patterning is particularly suitable for production of the described semiconductor device. Features listed in connection with the semiconductor device may therefore also be used for the method and vice versa. Further features, configurations and convenient aspects are revealed by the following description of the exemplary embodiments in conjunction with the figures, in which:

[0038] FIGS. 1A to 1E and FIGS. 2A to 2F each show a first or second exemplary embodiment respectively of a method by way of intermediate steps shown schematically in sectional view;

[0039] FIGS. 3A to 3D show a third exemplary embodiment of a method by way of intermediate steps in sectional view (FIGS. 3A to 3C) and in plan view (FIG. 3D);

[0040] FIGS. 4A to 4C show a fourth exemplary embodiment of a method by way of intermediate steps shown schematically in sectional view; and

[0041] FIGS. 5A and 5B show an exemplary embodiment of a semiconductor device in schematic sectional view (FIG. 5A) with an enlarged representation of a portion in FIG. 5B.

[0042] Identical, similar or identically acting elements are provided with the same reference numerals in the figures.

[0043] The figures and the size ratios of the elements illustrated in the figures relative to one another are not to be regarded as being to scale. Rather, individual elements and in particular layer thicknesses may be illustrated on an exaggeratedly large scale for greater ease of depiction and/or better comprehension.

[0044] FIGS. 1A to 1E show a first exemplary embodiment of a method for lateral patterning by way of a portion in schematic sectional view. As shown in FIG. 1A, a pattern layer 2 with a plurality of three-dimensional pattern elements 20 is provided. For example, the pattern layer 2 is arranged on a carrier 7. The carrier may for example be a growth substrate for epitaxial deposition of the material of the pattern layer 2. Alternatively, the carrier may also be different from a growth substrate for the pattern layer. The pattern layer may comprise a semiconductor material, in particular a III-V compound semiconductor material. The pattern elements 20 may arise as early as during in particular epitaxial deposition of the pattern layer or through subsequent patterning of a planar layer to form three-dimensional patterns.

[0045] The pattern elements 20 may be arranged in particular regularly, for example in a matrix or in a hexagonal pattern. The position of the pattern elements may for example be determined by means of a mask layer 15. Alternatively, the pattern elements may also be arranged irregularly, in particular randomly, for example as a result of self-organized growth. The mask layer may then be omitted. Remnants of the mask layer which may optionally be present may be removed during the method or in a post-processing step or remain on the carrier.

[0046] In the lateral direction the pattern elements 20 preferably have a maximum extent of 5 m. The pattern elements may however also be smaller or larger. For example, the maximum lateral extent in at least one lateral direction is at most 1 m.

[0047] In a vertical direction, i.e. perpendicular to a main plane of extension of the pattern layer 2, the extent is at least as great as the maximum lateral extent, preferably at least twice as great as the maximum lateral extent.

[0048] A covering layer 3 is formed on the pattern layer 2. For example, the covering layer comprises a polymer material. The covering layer fills the interspaces between adjacent pattern elements 20. In the exemplary embodiment shown, a material 30 for the covering layer is applied already laterally patterned to the pattern elements 20. This may proceed for example by means of a mask, for instance a shadow mask, or by means of a method suitable for laterally patterned application, for example a printing method, for instance an inkjet printing method. In the regions in which the covering layer 3 is formed, the latter does not have to cover the pattern elements 20 completely in the vertical direction. It may also be sufficient merely for the bottom ends of the pattern elements 20 to be embedded in the covering layer.

[0049] The covering layer 3 forms a protective layer for the pattern elements 20 covered by the covering layer. Laterally of the covering layer 3, regions 4 to be removed, in which the pattern elements 20, in particular also the bottom ends of the pattern elements, are exposed, are defined by means of the covering layer 3 (FIG. 1B).

[0050] The pattern elements 20 are then exposed to a force in the regions to be removed 4, such that the pattern elements 20 break off in the regions to be removed. In the exemplary embodiment shown, the applied force is exerted by a medium introduced with overpressure, for example air, water or a solvent or by means of a particle jet, for instance a sand jet. FIG. 1C shows, by way of example, a jet 91 for mechanical application of force.

[0051] Alternatively, the applied force may also be exerted by mechanical wiping, by ultrasound or by vibration.

[0052] A sufficiently heavy application of force, exerted in particular obliquely relative to the vertical direction, results in the free-standing pattern elements 20 not protected by the covering layer 3 being broken off. The pattern elements 20 to be removed are removed as solid bodies. For example, the volume of a one-piece part of the removed pattern element amounts to at least 30%, preferably at least 50%, of the volume of the original pattern element.

[0053] In particular, the local application of force results in shear forces on the side faces of the pattern elements 20, which are at their greatest at the bottom end of the pattern elements 20. In this way, the pattern elements 20 break off, preferably at the bottom end, such that the vertical extent of the remnants of the pattern elements 20 remaining on the carrier is slight. The bottom end is considered to be the end of the pattern elements 20 facing the carrier 7. Preferably, after removal the extent of the pattern elements in the region to be removed amounts to at most 10%, particularly preferably at most 5%, of the non-stripped pattern elements 20.

[0054] Thus, only the pattern elements 20 embedded in the covering layer 3 remain on the carrier 7 (FIG. 1D).

[0055] The covering layer can then be removed, such that the pattern layer 2, as shown in FIG. 1E, is present in laterally patterned form, with a stripped region 22 of the pattern layer 2. Such a pattern layer may subsequently be further processed into semiconductor devices. The stripped region 22 may for example be a mesa trench of the semiconductor device or a region on which a contact area for external contacting is arranged. During further processing, it is for example possible further to process the stripped regions in a post-processing step, for example using a chemical method, for instance etching. As a result of the preceding formation of the stripped regions, such a post-processing step is simplified, since the region to be treated has reduced topological height differences.

[0056] In the stripped region 22, breakage traces 8 may remain as a consequence of the mechanical stripping.

[0057] The described method is largely independent of the material of the pattern layer 2 and is therefore suitable in particular for different semiconductor materials, in particular for the semiconductor materials stated in the general part. Furthermore, the resultant pattern is less heavily dependent on the morphology of the initial pattern of the pattern layer 2, in particular compared with a method in which the pattern layer is patterned by an etching method. In addition, the pattern elements 20 do not necessarily have to have the same height. The method is also suitable for simultaneous removal of pattern elements of different heights. In contrast, in a chemical method etching periods of different lengths would be necessary for the stripping of pattern elements of different heights.

[0058] Furthermore, it is possible for the lateral patterning not to take place until after formation of the pattern layer 2. It is thus not necessary to predetermine the geometric shape of the semiconductor devices, for example the grid, the size and/or the type of the semiconductor devices, by way of a specific growth mask for epitaxy of the pattern layer. In addition, it is simply and reliably ensured by means of the method that during lateral patterning no pattern elements 20 are split. It has been found that, by avoiding splitting of pattern elements, the aging resistance of the semiconductor devices to be produced can be increased. In the case of chemical removal of the pattern elements in the region 4 to be removed, on the other hand, at best very precise, complex adjustment for the lithography method might prevent splitting of individual pattern elements.

[0059] The second exemplary embodiment shown in FIGS. 2A to 2F corresponds substantially to the first exemplary embodiment described in connection with FIGS. 1A to 1E. At variance therewith, the material 30 of the covering layer 3 is first applied over the entire surface (FIG. 2B) and then laterally patterned, for example by means of a mask 95. The mask 95 may for example be formed by a photoresist.

[0060] Then, as shown in FIG. 2D, force is applied in the regions 4 to be removed. This takes place by way of example in FIG. 2D by means of a brush 92. It may however also be performed by another type of mechanical wiping, for example by means of a cloth, for instance a cleaning cloth. Furthermore, one of the other methods mentioned in connection with FIG. 1C can also be applied.

[0061] After a cleaning step, only the pattern elements 20 embedded in the covering layer 3 remain on the carrier 7 (FIG. 2E). The covering layer 3 may then be removed as shown in FIG. 2F, so resulting in a laterally patterned pattern layer 2.

[0062] The third exemplary embodiment shown in FIGS. 3A to 3C differs from the first and second exemplary embodiments in that the regions 4 to be removed are those regions which are covered by the covering layer 3 (FIG. 3A). The regions not to be removed may additionally be embedded in a protective layer (not explicitly illustrated).

[0063] As shown in FIG. 3B, the applied force does not act directly on the pattern elements 20, but rather is transferred in places to the pattern elements 20 via the covering layer 3. For example, a matrix material, for instance a silicone matrix into which the pattern elements 20 have been embedded in the region 4 to be removed, is suitable for the covering layer.

[0064] The pattern elements 20 not covered by the covering layer do not, on the other hand, undergo any application of force or at least none sufficient to break off the pattern elements 20.

[0065] FIG. 3D shows a portion of a peeled-off material 30 in the form of a silicone matrix. In this exemplary embodiment, the pattern elements 20 embedded in the material have a hexagonal basic shape and are arranged in a hexagonal pattern. It goes without saying, however, that the method is also suitable for pattern elements with other basic shapes and other relative arrangements.

[0066] The method again results, as shown in FIG. 3C, in a stripped region 22 of the pattern layer 2.

[0067] The fourth exemplary embodiment shown in FIGS. 4A to 4C corresponds substantially to the third exemplary embodiment described in connection with FIGS. 3A to 3D. The region 4 to be removed is in particular once again that region of the pattern layer 2 which is covered by the covering layer 3 (FIG. 4A). However, the applied force is exerted by a thermally induced change in the extent of the covering layer. This may proceed for example by means of heating, shown in FIG. 4B by arrows 96. To this end, the material of the covering layer 3 conveniently has as large as possible a coefficient of thermal expansion, which differs from coefficients of expansion of the pattern layer 2. For example, the coefficient of thermal expansion of the covering layer is at least 50% greater than the coefficient of thermal expansion of the material of the pattern layer 2. As a result of the temperature change, mechanical stresses arise which cause the pattern elements 20 to break off in the region 4 to be removed. The pattern layer 2 patterned laterally in this way is shown in FIG. 4C.

[0068] An exemplary embodiment of a semiconductor device is shown in schematic sectional view in FIG. 5A. A portion 99 is shown on an enlarged scale in FIG. 5B. The semiconductor device 1 comprises a pattern layer 2 with a plurality of three-dimensional pattern elements 20. In plan view onto the semiconductor device, the pattern layer is subdivided into a device region 21 and stripped regions 22. The stripped regions 22 each comprise remnants of the pattern elements with breakage traces 8. The lateral extent of the pattern elements 20 is shown exaggeratedly large. The device region 21 typically comprises a multiplicity of such pattern elements, for example a hundred pattern elements or more.

[0069] By way of example, the semiconductor device 1 comprises two stripped regions 22, wherein one of the stripped regions takes the form of a mesa trench 51. The above-described method ensures that, in plan view onto the semiconductor device, the mesa trench does not split any pattern elements 20.

[0070] A further stripped region 22 takes the form of a region 52, in which a contact area 6 is arranged for external electrical contacting of the semiconductor device, for example by means of a wire bond connection. No tall edges have to be covered over to form the contact area. The absence of pattern elements 20 in the stripped region 22 additionally ensures that, during production of the wire bond connection, no pattern elements arranged beneath the contact area 6 break and have a disadvantageous effect on the functionality of the semiconductor device.

[0071] The semiconductor device 1 illustrated is configured, by way of example, as a semiconductor device provided for generating radiation. A nitride compound semiconductor material, in particular Al.sub.x In.sub.y Ga.sub.1-x-y N, is for example suitable for the generation of ultraviolet or blue radiation. The pattern elements 20 each comprise a first semiconductor layer 25 of a first conduction type and a second semiconductor layer 26 of a second conduction type different from the first conduction type. For example, the first semiconductor layer 25 is n-conductive and the second semiconductor layer 26 p-conductive or vice versa. An active region 27 provided for generating radiation is formed between the first semiconductor layer 25 and the second semiconductor layer 26. The second semiconductor layer 26 also covers, at least in places, the side faces 250 of the first semiconductor layer 25. In this way, the area of the active region 27 usable for generating radiation is increased in comparison with two first and second semiconductor layers deposited flat one over the other. The pn junction between the first semiconductor layer 25 and the second semiconductor layer 26 does not have to be exposed to produce the semiconductor device, in particular neither for external electrical contacting nor for formation of the mesa trenches.

[0072] The risk of an electrical short-circuit due to an exposed region of the first semiconductor layer 25 resulting from a broken-off pattern element is prevented. By avoiding splitting of the pattern elements 20, it is moreover ensured that the pn junction between the first semiconductor layer 25 and the second semiconductor layer 26 is short-circuited in the mesa trench.

[0073] It goes without saying that the semiconductor device may also have just one stripped region or three or more stripped regions. Furthermore, unlike in the described exemplary embodiment, the semiconductor device may also take the form of another semiconductor device, for example a sensor or a microelectronic or micromechanical device. In general, the described method is suitable for producing devices in which lateral patterning of a pattern layer with three-dimensional pattern elements is desired.

[0074] When producing the semiconductor devices, the stripped regions may be further processed in a post-processing step. For example, an etch step may be performed by which the mesa trenches 51 are formed right down to the carrier 7. The previously performed method for forming the stripped regions simplifies such a post-processing step, since the surface to be treated has less pronounced topological differences.

[0075] This patent application claims priority from German patent application 10 2014 107 167.0, the disclosure content of which is hereby included by reference.

[0076] The invention is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or the exemplary embodiments.

[0077] The work leading to this invention has received funding from the European Union under grant agreement no NMP3-SL-2012-280694.