Circuit and Method for Maximum Duty Cycle Limitation in Step Up Converters

Abstract

An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.

Claims

1. An adaptive duty cycle limiting circuit for use with a switching DC-to-DC converter comprising: a ramp generator configured for receiving an output voltage of the switching DC-to-DC converter communicated from an output terminal of the switching DC-to-DC converter and configured for generating an output ramp signal created from the output voltage of the switching DC-to-DC converter; a variable voltage source configured for receiving an adjusting voltage level indicating the voltage level of an input voltage source and configured for generating an output voltage level that is a fractional value of the voltage level of the input voltage source; and a comparator circuit configured for receiving the output voltage level of the variable voltage source, and the output voltage ramp signal, and configured for determining if the voltage level of the variable voltage source is less than or greater than output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to adjust the duty cycle of the switching DC-to-DC converter.

2. The adaptive duty cycle limiting circuit of claim 1 wherein the converter switching control circuit has an logical OR circuit that is configured to receive the duty cycle limit signal and configured to logically combine it with a feedback duty cycle signal for deactivating a switching circuit of the switching DC-to-DC converter.

3. The adaptive duty cycle limiting circuit of claim 1 wherein the switching DC-to-DC converter is a step-up switching DC-to-DC converter.

4. The adaptive duty cycle limiting circuit of claim 3 wherein the step-up switching DC-to-DC converter is a boost switching DC-to-DC converter.

5. The adaptive duty cycle limiting circuit of claim 3 wherein the step-up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter.

6. The adaptive duty cycle limiting circuit of claim 1 wherein the fractional value of the voltage level of the input voltage source is approximately one-half.

7. An adaptive duty cycle limiting circuit for use with a switching DC-to-DC converter comprising: a ramp generator configured for receiving a reference voltage from a reference voltage source and configured for generating an output ramp signal created from the reference voltage source; a variable voltage source configured for receiving an adjusting voltage indicating the voltage level of an input voltage source and configured for generating an output voltage that is a fractional value of the voltage level of the input voltage source from the adjusting voltage; and a comparator circuit configured for receiving the output voltage of the variable voltage source and the output voltage ramp signal and configured for determining if the voltage level of the variable voltage source is less than or greater than output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to adjust the duty cycle of the switching DC-to-DC converter.

8. The adaptive duty cycle limiting circuit of claim 7 wherein the converter switching control circuit has an logical OR circuit that is configured to receive the duty cycle limit signal and configured to logically combine it with a feedback duty cycle signal for deactivating a switching circuit of the switching DC-to-DC converter.

9. The adaptive duty cycle limiting circuit of claim 7 wherein the switching DC-to-DC converter is a step-up switching DC-to-DC converter.

10. The adaptive duty cycle limiting circuit of claim 9 wherein the step-up switching DC-to-DC converter is a boost switching DC-to-DC converter.

11. The adaptive duty cycle limiting circuit of claim 9 wherein the step-up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter.

12. The adaptive duty cycle limiting circuit of claim 7 wherein the fractional value of the voltage level of the input voltage source is approximately one-half multiplied by a feedback division ratio.

13. A switching DC-to-DC converter comprising: an adaptive duty cycle limiting circuit comprising: a ramp generator configured for receiving an output voltage of the switching DC-to-DC converter communicated from an output terminal of the switching DC-to-DC converter and configured for generating an output ramp signal created from the output voltage of the switching DC-to-DC converter; a variable voltage source is configured for receiving an adjusting voltage level indicating the voltage level of an input voltage source and configured for generating an output voltage level that is a fractional value of the voltage level of the input voltage source from the adjusting voltage level; and a comparator circuit configured for receiving the output voltage level of the variable voltage source and the output voltage ramp signal, and configured for determining if the voltage level of the variable voltage source is less than or greater than output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to adjust the duty cycle of the switching DC-to-DC converter.

14. The switching DC-to-DC converter of claim 13 wherein the converter switching control circuit has an logical OR circuit that is configured to receive the duty cycle limit signal and configured to logically combine it with a feedback duty cycle signal for deactivating a switching circuit of the switching DC-to-DC converter.

15. The switching DC-to-DC converter of claim 13 wherein the switching DC-to-DC converter is a step-up switching DC-to-DC converter.

16. The switching DC-to-DC converter of claim 15 wherein the step-up switching DC-to-DC converter is a boost switching DC-to-DC converter.

17. The switching DC-to-DC converter of claim 15 wherein the step-up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter.

18. The switching DC-to-DC converter of claim 13 wherein the fractional value of the voltage level of the input voltage source is approximately one-half.

19. A switching DC-to-DC converter comprising: an adaptive duty cycle limiting circuit comprising: a ramp generator configured for receiving a reference voltage from a reference voltage source and configured for generating an output ramp signal created from the reference voltage source; a variable voltage source configured for receiving an adjusting voltage indicating the voltage level of the input voltage source and configured for generating an output voltage that is a fractional value of the voltage of the input voltage source; and a comparator circuit configured for receiving the output voltage of the variable voltage source and the output ramp signal and configured for determining if the voltage level of the variable voltage source is less than or greater than output voltage ramp signal to generate a duty cycle limit signal for transfer to a converter switching control circuit to adjust the duty cycle of the switching DC-to-DC converter.

20. The switching DC-to-DC converter of claim 19 wherein the converter switching control circuit has an logical OR circuit that configured to receive the duty cycle limit signal and configured to logically combine it with a feedback duty cycle signal for deactivating a switching circuit of the switching DC-to-DC converter.

21. The switching DC-to-DC converter of claim 19 wherein the switching DC-to-DC converter is a step-up switching DC-to-DC converter.

22. The switching DC-to-DC converter of claim 21 wherein the step-up switching DC-to-DC converter is a boost switching DC-to-DC converter.

23. The switching DC-to-DC converter of claim 21 wherein the step-up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter.

24. The switching DC-to-DC converter of claim 13 wherein the fractional value of the voltage level of the input voltage source is approximately one-half multiplied by a feedback division ratio.

25. A method for operating a switching DC-to-DC converter for limiting a duty cycle, comprising the steps of: generating duty cycle ramp signal; comparing the duty cycle ramp signal with a fractional value of a voltage level of an input voltage source; repeating the step of comparing the duty cycle ramp signal with a fractional value of a voltage level of an input voltage source, when the voltage level of the duty cycle ramp signal is greater than the fractional value of the voltage level of the input voltage source; and activating and communicating a cycle limit signal to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter, when the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage level of the input voltage source.

26. The method of claim 25 wherein the duty cycle ramp signal has a maximum value the output voltage of the switching DC-to-DC converter.

27. The method of claim 25 wherein the duty cycle ramp signal has a maximum value a reference voltage of the switching DC-to-DC converter.

28. The method of claim 26 wherein the fractional value of the voltage level of the input voltage source is one half.

29. The method of claim 27 wherein the fractional value of the voltage level of the input voltage source is one half multiplied by a feedback division ratio.

30. The method of claim 25 wherein the switching DC-to-DC converter is a step up switching DC-to-DC converter for providing an output voltage that is greater than the input voltage of the switching DC-to-DC converter.

31. The method of claim 25 wherein the step up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter or a boost switching DC-to-DC converter.

32. An apparatus for operating a switching DC-to-DC converter for limiting a duty cycle, comprising: means for generating duty cycle ramp signal; means for comparing the duty cycle ramp signal with a fractional value of a voltage level of an input voltage source; means for repeating the step of comparing the duty cycle ramp signal with a fractional value of a voltage level of an input voltage source, when the voltage level of the duty cycle ramp signal is greater than the fractional value of the voltage level of the input voltage source; and means for activating and communicating a cycle limit signal to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter, when the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage level of the input voltage source.

33. The apparatus of claim 32 wherein the duty cycle ramp signal has a maximum value the output voltage of the switching DC-to-DC converter.

34. The apparatus of claim 32 wherein the duty cycle ramp signal has a maximum value a reference voltage of the switching DC-to-DC converter.

35. The apparatus of claim 33 wherein the fractional value of the voltage level of the input voltage source is one half.

36. The apparatus of claim 35 wherein the fractional value of the voltage level of the input voltage source is one half multiplied by a feedback division ratio.

37. The apparatus of claim 32 wherein the switching DC-to-DC converter is a step up switching DC-to-DC converter for providing an output voltage that is greater than the input voltage of the switching DC-to-DC converter.

38. The apparatus of claim 32 wherein the step up switching DC-to-DC converter is a buck-boost switching DC-to-DC converter or a boost switching DC-to-DC converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG. 1 is schematic of a boost switching DC-to-DC converter of the prior art.

[0047] FIG. 2 is schematic of a buck-boost switching DC-to-DC converter of the prior art.

[0048] FIG. 3 is a plot of the effect of parasitic resistance on the voltage gain of the boost switching DC-to-DC converter versus duty cycle of the prior art.

[0049] FIG. 4 is a plot of the duty cycle ramp voltage and the duty cycle limit voltages.

[0050] FIG. 5 is schematic of a boost switching DC-to-DC converter embodying the principals of the present disclosure.

[0051] FIG. 6 is a schematic of a duty cycle limiting circuit of the boost switching DC-to-DC converter of FIG. 5 embodying the principals of the present disclosure.

[0052] FIG. 7 is a plot of the duty cycle ramp voltage and the duty cycle limit voltages of FIG. 6.

[0053] FIG. 8 is a plot of simulation results of the boost switching DC-to-DC converter of the prior art of FIG. 1.

[0054] FIG. 9 is a plot of the simulation results of the boost switching DC-to-DC converter embodying the principals of the present disclosure.

[0055] FIG. 10a is a plot of the simulation results of the boost switching DC-to-DC converter embodying the principals of the present disclosure as shown in FIG. 7 with expanded time scale.

[0056] FIG. 10b is a plot of the simulation results of the boost switching DC-to-DC converter illustrating the beginning of the functioning of the duty cycle limit circuit embodying the principals of the present disclosure as shown in FIG. 7 with expanded time scale.

[0057] FIG. 11 is flow chart of a method for limiting duty cycle of boost switching DC-to-DC converter embodying the principals of the present disclosure.

DETAILED DESCRIPTION

[0058] This disclosure provides circuits and methods for defining a maximum value of a duty cycle of a switching DC-to-DC converter such that as the parasitic resistance degrades the voltage gain of a switching DC-to-DC converter to the point that the slope of the voltage gain versus the duty cycle of the switching DC-to-DC converter becomes negative, the duty cycle is limited. To accomplish this, feedback from operation switching DC-to-DC converter is used for defining an adaptive limit of the duty cycle to prevent the switching DC-to-DC converter. The maximum limit of the duty cycle is modified in operation such that the switching DC-to-DC converter becomes more flexible and efficient and is simpler to implement and has limited circuit spread.

[0059] The switching DC-to-DC converter circuit of this disclosure is best suited for a boost and buck-boost switching DC-to-DC converter applications. For ease in understanding the structure of the switching DC-to-DC converter of this disclosure, the boost switching DC-to-DC converter as described in FIG. 1. The maximum duty cycle for the boost switching DC-to-DC converter is determined, as shown in Redl, by the equations:

[00003]$\begin{array}{cc}{V}_{\mathrm{IN}}.Math.I_L=R_W.Math.I_L^2+\frac{V_{\mathrm{OUT}}^2}{R_{\mathrm{LOAD}}}& \mathrm{Eq}..Math.1\end{array}$ [0060] Where [0061] V.sub.in is the voltage of the input voltage source. [0062] I.sub.L is the current flowing through the inductor L [0063] R.sub.W is the resistive value of the parasitic resistances. [0064] V.sub.OUT is the voltage at the output terminal OUT. [0065] R.sub.LOAD is the load resistance of the boost switching DC-to-DC converter.

[0066] Eq. 1 demonstrates that the input power is equal to the sum of the resistive loss and the output power.

[00004]$\begin{array}{cc}\left(1-\mathrm{DC}\right).Math.I_L=\frac{V_{\mathrm{OUT}}}{R_{\mathrm{LOAD}}}& \mathrm{Eq}..Math.2\end{array}$

[0067] From charge balance equation of Eq. 2, the average current through the diode D of FIG. 1 is equal to the load current I.sub.LOAD.

[0068] By solving Eq. 1 and Eq. 2, the function for determining the plots of FIG. 3 is given by Eq. 3 as:

[00005]$\begin{array}{cc}\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}=\frac{1}{1-\mathrm{DC}}\frac{1}{1+\frac{R_W}{\left(1-{\mathrm{DC}}^2\right).Math.R_{\mathrm{LOAD}}}}& \mathrm{Eq}..Math.3\end{array}$

[0069] The maximum duty cycle DC.sub.max is determined by taking the derivative of Eq. 3 with respect to the duty cycle DC and solving the derivative of Eq. 3 equal to zero to find the value of the duty cycle DC where the gain Vout/Vin of the switching DC-to-DC converter circuit has a peak. The maximum duty cycle DC.sub.max is equal to:

[00006]$\begin{array}{cc}{\mathrm{DC}}_{\max }=1-\sqrt{\frac{R_W}{R_{\mathrm{LOAD}}}}& \mathrm{Eq}..Math.4\end{array}$

[0070] The maximum duty cycle DC.sub.max value should be the actual limit for duty cycle (D.sub.LIMIT). But it has to be expressed in terms of parameters more compatible with analog design components of the switching DC-to-DC converter circuit. Therefore, Eq. 4 is substituted into Eq. 3 at the duty cycle DC equal to the maximum duty cycle DC.sub.max. This achieves the equation:

[00007]$\begin{array}{cc}\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}=\frac{1}{2}.Math.\sqrt{\frac{R_{\mathrm{LOAD}}}{R_W}}.Math..Math.\mathrm{and}& \mathrm{Eq}..Math.5\\ \frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}=\frac{1}{2.Math.\left(1-{\mathrm{DC}}_{\max }\right)}& \mathrm{Eq}..Math.6\end{array}$

[0071] If eq. 6 is rearranged, the maximum duty cycle becomes a function of the input voltage according to the equation:

[00008]$\begin{array}{cc}{V}_{\mathrm{OUT}}\left(1-{\mathrm{DC}}_{\max }\right)=\frac{V_{\mathrm{in}}}{2}& \mathrm{Eq}..Math.7\end{array}$

Thus a condition for stability that ensures the boost switching DC-to-DC converter operates in the positive slope region to the left of the Line 30 of FIG. 3. Thus the condition for stability becomes:

[00009]$\begin{array}{cc}{V}_{\mathrm{OUT}}\left(1-\mathrm{DC}\right)>\frac{V_{\mathrm{in}}}{2}& \mathrm{Eq}..Math.8\end{array}$

[0072] FIG. 4 is a plot of the duty cycle ramp voltage 50 and the duty cycle limit voltage 55 of Equation 7. The duty cycle ramp voltage 50 is formed to have a peak that is the voltage level V.sub.OUT at the output terminal OUT of the boost switching DC-to-DC converter. The duty cycle limit signal 55 is the logical level that is set such that the switch SW of FIG. 1 is deactivated until the end of the cycle. The deactivated switch SW causes the current IL through the inductor L to flow through the diode D to the output terminal OUT, the capacitor CL, and the load resistor R.sub.LOAD. The deactivation 60 of the switch SW occurs when the voltage level V.sub.OUT at the output terminal OUT is equal to a voltage level V.sub.IN/2 that is one half of the voltage level V.sub.OUT at the output terminal OUT. The next cycle starts when the switch SW is activated at the time T.

[0073] In an implementation embodying the principals of the present disclosure, a comparator will compare the voltage level V.sub.IN/2 with the duty cycle ramp voltage 50 to determine the duty cycle limit signal 55. The compare voltage level V.sub.IN/2 may preferably with some margin to generate the duty cycle limit signal 55.

[0074] FIG. 5 is schematic of a boost switching DC-to-DC converter embodying the principals of the present disclosure. The boost switching DC-to-DC converter includes a boost switching circuit 100 that has an inductor L with a first terminal connected to a first terminal of a duty cycle limit circuit 110. The associated parasitic resistances R.sub.W of the boost switching DC-to-DC converter is shown as a series resistance with the inductor L. The first terminal of the parasitic resistances R.sub.W is connected to a second terminal of the inductor L. The second terminal of the parasitic resistances R.sub.W is connected to a drain of a switching NMOS transistor M.sub.5 and the anode of a diode D. The cathode of the diode D is connected to a first terminal of a filter capacitor CL and a first terminal of a load resistance R.sub.LOAD. The cathode of the diode D, the first terminal of a filter capacitor CL, and the first terminal of a load resistance R.sub.LOAD form the output terminal OUT of the boost switching DC-to-DC converter. A duty cycle control signal D.sub.BOOST is applied to the gate of the switching NMOS transistor M.sub.5 and the source of the switching NMOS transistor M.sub.5 is connected to the ground reference voltage source. The second terminals of the filter capacitor CL, and the load resistance R.sub.LOAD are connected to the ground reference voltage source.

[0075] The duty cycle control signal D.sub.BOOST is generated by the boost control circuit 105. The boost control circuit 105 receives a reference voltage V.sub.REF that provides a reference voltage level that is indicative of the output voltage level V.sub.OUT. The output voltage V.sub.OUT is applied to a first terminal of the first divider resistor R.sub.1 of the voltage divider 160. The second terminal of the first divider resistor R.sub.1 is connected to a first terminal of a second divider resistor R.sub.2. The common connection of the second terminal of the first divider resistor R.sub.1 and the second terminal of the second divider resistor R.sub.2 provides a scaled voltage V.sub.ODIV from the voltage divider 160. The scaled voltage V.sub.ODIV is scaled by the factor

[00010]$\frac{R_2}{R_1+R_2}$

from the output voltage level V.sub.OUT and is applied to the control circuit 105.

[0076] The reference voltage V.sub.REF and the scaled voltage V.sub.ODIV are the inputs to an error amplifier 115. The output of the error amplifier 115 is an error signal V.sub.E that is the voltage level of the difference between the voltage levels of the reference voltage V.sub.REF and the scaled voltage V.sub.ODIV. A ramp generator 120 produces a boost ramp signal V.sub.RAMPB+ that is applied to the noninverting input of the comparator 125. The error signal V.sub.E is applied to the inverting input of the comparator 125. The boost ramp signal V.sub.RAMPB is compared with the error signal V.sub.E to produce a reset signal V.sub.RESET at the output of the comparator 125 that is applied to a first terminal the logical OR circuit 130. The second terminal of the logical OR circuit 130 receives a duty cycle limit signal D.sub.LIMIT. The duty cycle limit signal D.sub.LIMIT provides the indication that the gain

[00011]$\left(\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}\right)$

of the boost switching DC-to-DC converter is at a point of inflection or has started to decrease for indicating that the duty cycle must be reduced. The output of the logical OR circuit 130 is applied to the reset terminal R of the set-reset latch 140.

[0077] The set clock generator 135 generates a set clock signal V.sub.SET that is applied to the set terminal S of the set-reset latch 140. The output Q of the set-reset latch 140 is connected to the gate of the boost switching NMOS transistor M.sub.2 to provide the boost switching control signal D.sub.BOOST. The boost switching control signal D.sub.BOOST activates the switching NMOS transistor M.sub.5 to divert the inductor current IL to the ground reference voltage source when the set terminal S of the set-reset latch 140 is activated such that the output Q turns on the switching NMOS transistor M.sub.5.

[0078] A duty cycle limit circuit 110 generates the duty cycle limit signal D.sub.LIMIT that is applied to the second terminal of the logical OR circuit 130. The duty cycle limit circuit 110 has a variable voltage source 150 that receives the voltage of the input voltage source V.sub.IN. The variable voltage source 150 divides the voltage level of the input voltage source V.sub.IN by approximately one-half to generate the compare voltage level V.sub.IN/2 that is applied to the noninverting terminal of the comparator 145. The output voltage V.sub.OUT is applied to a ramp generator 155 that generates a ramp signal V.sub.RAMPDC that has a peak amplitude that is approximately the voltage level of the output voltage V.sub.OUT. The ramp signal V.sub.RAMPDC is applied to the inverting terminal of the comparator 145. The output of the comparator is the duty cycle limit signal D.sub.LIMIT that is applied to the logical OR circuit 130 to cause the reset terminal R of the set-reset latch 140 to activate thus causing the switching NMOS transistor M.sub.5 to turn off truncating the duty cycle of the boost switching DC-to-DC converter to insure that the boost switching DC-to-DC converter operates in the positive slope region to the left of the Line 30 of FIG. 3. It is apparent that generating the duty cycle limit signal D.sub.LIMIT is independent of load current I.sub.LOAD, temperature, process and any parasitic resistances R.sub.W in series with the inductor L. This results in a wide operational range for the boost switching DC-to-DC converter with different internal/external components.

[0079] The operation of the boost switching DC-to-DC converter begins with the activation of the input voltage source V.sub.in. The switching NMOS transistor M.sub.2 is turned off and the diode D is polarized to be conducting to allow current to flow from the input voltage source V.sub.in through the inductor L, the parasitic resistances R.sub.W, the diode D and the load resistance RL. A portion of the inductor current IL charges the capacitor CL. The set clock generator 135 generates the set clock signal V.sub.SET to set the set-reset latch 140 such that the switching NMOS transistor M.sub.2 is turned on and the inductor current IL is shunted to the ground reference voltage source and the diode D is inversely polarized and nonconducting. Consequently, there is no connection between the input voltage source V.sub.in and the load resistance RL and thus the voltage across the load resistance RL is developed by the charge of the capacitor CL.

[0080] When the error voltage V.sub.E as applied to the inverting input of the comparator 125 is greater than the voltage of the boost ramp signal V.sub.RAMPB+ that is applied to the noninverting input of the comparator 125, a reset signal V.sub.RESET is produced at the output of the comparator 125 that is applied to a first terminal the logical OR circuit 130. The output of the logical OR circuit 130 is applied to the reset terminal of the set-reset latch 140 is deactivated such that the output Q turns off the switching NMOS transistor M.sub.5. The diode D is polarized to be conducting to allow current to flow from the input voltage source V.sub.in through the inductor L, the parasitic resistances R.sub.W, the diode D and the load resistance RL. A portion of the inductor current IL charges the capacitor CL. The output voltage V.sub.OUT rises until the set clock generator 135 generates the set clock signal V.sub.SET to set the set-reset latch 140 such that the switching NMOS transistor M.sub.5 is turned on and the cycle is repeated.

[0081] If the output load current I.sub.LOAD is sufficiently large that the duty cycle generated from the first comparator 125 is greater than the duty cycle limit signal D.sub.LIMIT, the duty cycle limit signal D.sub.LIMIT triggers the reset signal of the set-reset latch 140 to deactivate the output Q to turn off the switching NMOS transistor M.sub.5 to prevent the t the boost switching DC-to-DC converter from operating in the negative slope region to the right of the Line 30 of FIG. 3.

[0082] The principals of the circuit that embody the present disclosure can be regarded as a protection circuit. The circuit as shown above insures that the control loop of the switching DC-to-DC converter is always in positive slope range. It is desirable that the protection turns on during load transients and input voltage source V.sub.IN transients.

[0083] In various embodiments, the output voltage V.sub.OUT is converted to a current by dividing the output voltage V.sub.OUT by a scaling resistance R.sub.D (V.sub.OUT/R.sub.D). The current is converted to a sawtooth shaped current I.sub.SAW. The sawtooth current signal I.sub.SAW is set to a zero (0) ampere level at the start of the duty cycle and will be equal to the current V.sub.OUT/R.sub.D at the end of duty cycle.

[0084] The resulting current is multiplied by resistance R.sub.D to generate the duty cycle limit voltage V.sub.D as defined by the equation Eq. 9:

[00012]$\begin{array}{cc}{V}_D=R_D\left(\frac{V_{\mathrm{OUT}}}{R_D}-I_{\mathrm{SAW}}\right)=\frac{V_{\mathrm{IN}}}{2}& \mathrm{Eq}..Math.9\end{array}$

[0085] As is known in the art the output voltage V.sub.OUT is subject to line and load transients and other transient noise sources. To mitigate these sources, the output voltage V.sub.OUT should be replaced with the reference voltage V.sub.REF, since it is immune to the transients. The reference voltage V.sub.REF is related to the output voltage V.sub.OUT by the equation Eq. 10:

[00013]$\begin{array}{cc}{V}_{\mathrm{OUT}}=V_{\mathrm{REF}}.Math.\frac{R_1+R_2}{R_2}& \mathrm{Eq}..Math.10\end{array}$ [0086] Where [0087] V.sub.REF is the fixed reference voltage for the error amplifier. [0088] R.sub.1 is first divider resistor of the voltage divider 160 of FIG. 5. [0089] R.sub.2 is second divider resistor of the voltage divider 160 of FIG. 5.

[0090] Substituting Eq. 10 into Eq. 8 and dividing and multiplying by the scaling resistance R.sub.D to calculate the duty cycle limit voltage V.sub.D according to the equation:

[00014]$\begin{array}{cc}{V}_D=R_D.Math.\frac{R_1+R_2}{R_2}.Math.\left(\frac{V_{\mathrm{REF}}}{R_D}-\mathrm{DC}.Math.\frac{V_{\mathrm{REF}}}{R_D}\right)=\frac{V_{\mathrm{IN}}}{2}.Math..Math.\mathrm{Where}& \mathrm{Eq}..Math.11\\ \frac{R_1+R_2}{R_2}.Math.\mathrm{DC}.Math.\frac{V_{\mathrm{REF}}}{R_D}=I_{\mathrm{SAW}}& \mathrm{Eq}..Math.12\end{array}$

[0091] As is apparent, the sawtooth shaped current I.sub.SAW is proportional to the duty cycle. From the proportionality of the reference voltage level V.sub.REF to the output voltage level V.sub.OUT of Eq. 10, the reference voltage level V.sub.REF is developed according to the equation Eq. 13:

[00015]$\begin{array}{cc}{V}_{\mathrm{REF}}\left(1-{\mathrm{DC}}_{\mathrm{MAX}}\right)=\frac{V_{\mathrm{in}}}{2}.Math.\left(\frac{R_2}{R_1+R_2}\right)& \mathrm{Eq}..Math.13\end{array}$

[0092] The reference voltage level V.sub.REF and the voltage level of the input voltage source V.sub.in is converted to currents by dividing by a scaling resistance R.sub.D according to the equation Eq. 14

[00016]$\begin{array}{cc}{R}_D\left(\frac{V_{\mathrm{REF}}}{R_D}-\frac{{\mathrm{DC}}_{\mathrm{MAX}}.Math.V_{\mathrm{REF}}}{R_D}\right)=\frac{V_{\mathrm{in}}}{2}.Math.\left(\frac{R_2}{R_1+R_2}\right)& \mathrm{Eq}..Math.14\end{array}$

[0093] FIG. 6 is a schematic of an implementation of a duty cycle limiting circuit 110 of the boost switching DC-to-DC converter of FIG. 5 embodying the principals of the present disclosure. The reference voltage V.sub.REF is applied to a noninverting input terminal of an operational amplifier 200. The operational amplifier 200 is configured as a unity gain amplifier having its output connected to the gates of the PMOS transistors M.sub.6 and M.sub.7. The drain of the PMOS transistor M.sub.6 is connected as a feedback loop to the input of the inverting terminal of operational amplifier 200. The source of the PMOS transistor M.sub.6 is connected to the input voltage source V.sub.in. The drain of the PMOS transistor M.sub.6 is also connected to a first terminal of a first scaling resistor R.sub.D1. A second terminal of the first scaling resistor R.sub.D1 is connected to the ground reference voltage source.

[0094] The drain of the PMOS transistor M.sub.7 is connected to the inverting terminal of comparator 205. The source of the PMOS transistor M.sub.7 is connected to the input voltage source V. The drain of the PMOS transistor M.sub.7 is connected to a first terminal of a second scaling resistor R.sub.D2. A second terminal of the second scaling resistor R.sub.D2 is connected to the ground reference voltage source. The current I.sub.RD through the PMOS transistor M.sub.7 is equal to the reference voltage V.sub.REF divided by the resistance of the second scaling resistor R.sub.D2.

[0095] The drain of the PMOS transistor M.sub.7 and the first terminal of a second scaling resistor R.sub.D2 are connected to a drain of a first NMOS transistor M.sub.8. The source of the first NMOS transistor M.sub.8 is connected to the ground reference voltage source. The first NMOS transistor M.sub.8 and a second NMOS transistor M.sub.9 have their gates commonly connected and connected to the drain of second NMOS transistor M.sub.9 to form a current mirror. The second NMOS transistor M.sub.9 provides the reference leg of the current mirror, with the drain of the second NMOS transistor M.sub.9 connected to the ramp current source 215. The ramp current source 215 provides a current I.sub.RAMP to the drain of the second NMOS transistor M.sub.8. The current passed through the second NMOS transistor M.sub.9 to the first plate of the capacitor C.sub.RAMP. The second plate of the capacitor C.sub.RAMP is connected to the ground reference voltage source. The ramp current source 215, the second NMOS transistor M.sub.9, and the capacitor C.sub.RAMP form a ramp generator 210 which has a ramp time based on the current I.sub.RAMP and the capacitance of the capacitor C.sub.RAMP. The mirror leg of the current mirror is the first NMOS transistor M.sub.8 that has a current that equal to the current I.sub.RD multiplied by the duty cycle DC and establishes the ramp signal V.sub.RAMPDC at the inverting terminal of the comparator 205.

[0096] A voltage V.sub.in/2 that is one half of the input voltage source V.sub.in is applied to a first terminal of the first divider resistor R.sub.1. The second terminal of the first divider resistor R.sub.1 is connected to the first terminal of the second divider resistor R.sub.2 and the second terminal of the second divider resistor R.sub.2 is connected to the ground reference voltage source. The first divider resistor R.sub.1 and second divider resistor R.sub.2 form a voltage divider similar to that of the voltage divider 160 of FIG. 5 that has the feedback resistive ratio of the boost switching DC-to-DC converter of FIG. 5. The divider voltage 220 developed at the common connection of the second terminal of the first divider resistor R.sub.1 and the first terminal of the second divider resistor R.sub.2 is one half of the input voltage source V.sub.in scaled by the feedback resistive ratio

[00017]$\left(\frac{R_2}{R_1+R_2}\right).$

[0097] FIG. 7 is a plot of the duty cycle ramp voltage V.sub.RAMPDC and the duty cycle limit signal D.sub.limit of FIG. 6. The duty cycle ramp voltage V.sub.RAMPDC has a peak voltage that is the reference voltage V.sub.REF. The duty cycle ramp voltage V.sub.RAMPDC decreases in amplitude, as described above, until the duty cycle ramp voltage V.sub.RAMPDC reaches the divider voltage level 220. At the divider voltage level 220, the duty cycle limit signal D.sub.limit is activated and the reset terminal of the set-reset latch 140 is reset until the set clock generator 135 generates the next set clock signal V.sub.SET that is applied to the set terminal S of the set-reset latch 140 to start the next cycle of the boost switching DC-to-DC converter.

[0098] FIG. 8 is a plot of simulation results of the boost switching DC-to-DC converter of the prior art of FIG. 1. The boost switching DC-to-DC converter has an input voltage source V.sub.in equal to 2.5V with the set clock generator 135 set the frequency of the clock signal V.sub.SET to approximately 3 MHz. At the time 100 s, the load current begins to increase and output voltage V.sub.OUT starts to decrease. With no duty cycle limit, the duty cycle control signal D.sub.BOOST is activated 250 continuously and the switching NMOS transistor M.sub.5 is turned on. The output voltage V.sub.OUT decreases until it collapses 255 to a voltage approaching 1.2V from an output voltage V.sub.OUT of approximately 3.3V.

[0099] FIG. 9 is a plot of the simulation results of the boost switching DC-to-DC converter embodying the principals of the present disclosure. FIG. 10a is a plot of the simulation results of the boost switching DC-to-DC converter embodying the principals of the present disclosure as shown in FIG. 7 with expanded time scale. FIG. 10b is a plot of the simulation results of the boost switching DC-to-DC converter illustrating the beginning of the functioning of the duty cycle limit circuit embodying the principals of the present disclosure as shown in FIG. 7 with expanded time scale. The boost switching DC-to-DC converter has the input voltage source V.sub.in equal to 2.5V with the set clock generator 135 set the frequency of the clock signal V.sub.SET to approximately 3 MHz. At the time 100 s, the load current begins to increase and output voltage V.sub.OUT starts to decrease. When load current increases with the duty cycle limit circuit 110 operating, the duty cycle control signal D.sub.BOOST is activated 250 to increase the period to turn on the switching NMOS transistor M.sub.5 longer and the output voltage V.sub.OUT decreases in amplitude. When the duty cycle has increased sufficiently long, the duty cycle limit signal D.sub.limit will now limit the duty cycle and control the period of the turn on of the switching NMOS transistor M.sub.5. The output voltage V.sub.OUT now only decreases to a voltage level of approximately 3.1V.

[0100] Referring to FIG. 10a, the clock signal V.sub.SET defines the start of the duty cycle control signal D.sub.BOOST but as the load increases and the duty cycle is impacted such that the reset signal V.sub.RESET is not resetting the set-reset latch 140 correctly, the duty cycle limit signal D.sub.limit will now limit the duty cycle. As described above, when the duty cycle ramp voltage V.sub.RAMPDC is equal to the divider voltage level 220, the duty cycle limit signal D.sub.limit is activated to limit the duty cycle by resetting the set-reset latch 140 to turn off the switching NMOS transistor M.sub.5. The inductor current IL begins to decrease until the next cycle of the clock signal V.sub.SET.

[0101] Referring to FIG. 10b, the duty cycle starts with the clock signal V.sub.SET and the duty cycle control signal D.sub.BOOST is activated. The duty cycle control signal V.sub.DBOOST is expected to end when the output of the reset signal V.sub.RESET at the output of the comparator 125 is activated. However when load current I.sub.LOAD increases, the duty cycle limit circuit 110 assumes control with the duty cycle limit signal D.sub.limit being activated and the duty cycle limit signal D.sub.limit as applied to the input of the logical OR circuit 130 causes the output of the logical OR circuit 130 to the reset the set-reset latch 140. The output signal V.sub.DBOOST of the reset the set-reset latch 140 deactivates the NMOS transistor M.sub.5. The cycle complete and now awaits the arrival of the next clock signal V.sub.SET.

[0102] FIG. 11 is flow chart of a method for limiting duty cycle of boost switching DC-to-DC converter embodying the principals of the present disclosure. Referring to FIGS. 5 and 11, the reference voltage is set (Box 300) to a voltage level that will product the desired output voltage level V.sub.OUT. A duty cycle ramp signal V.sub.RAMPDC is generated (Box 305). In some embodiments, the duty cycle ramp has a maximum voltage of the voltage level of the output voltage level V.sub.OUT as shown in FIG. 5 or the reference voltage V.sub.REF as shown in FIG. 6. The duty cycle ramp signal V.sub.RAMPDC is compared with a fractional voltage level of the input voltage source V.sub.IN (Box 310). If the duty cycle ramp signal V.sub.RAMPDC has a maximum voltage level of output voltage level V.sub.OUT, the fraction voltage level of the input voltage source V.sub.IN is one half the voltage level of the input voltage source V.sub.IN. If the duty cycle ramp signal V.sub.RAMPDC has a maximum voltage level of reference voltage level V.sub.REF, the fraction voltage level of the input voltage source V.sub.IN is one half the voltage level of the input voltage source V.sub.IN multiplied by the feedback resistive ratio

[00018]$\left(\frac{R_2}{R_1+R_2}\right).$

It is then determined (Box 315) if the duty cycle ramp signal V.sub.RAMPDC is greater than the fractional fraction voltage level of the input voltage source V.sub.IN. If the duty cycle ramp signal V.sub.RAMPDC is greater than the fractional fraction voltage level of the input voltage source V.sub.IN, the comparison (Box 310) continues until the duty cycle ramp signal V.sub.RAMPDC is not greater than the fractional fraction voltage level of the input voltage source V.sub.IN. When the duty cycle ramp signal V.sub.RAMPDC is not greater than the fractional fraction voltage level of the input voltage source V.sub.IN, the duty cycle limit D.sub.LIMIT is set (Box 320). The next cycle is started with the generation (Box 305) of the duty cycle ramp signal V.sub.RAMPDC.

[0103] The principals embodying this disclosure in FIGS. 5 and 6 uses a boost switching DC-to-DC converter. This structure for the duty cycle limiting circuit is not limited to a boost switching DC-to-DC converter and includes any step up DC-to-DC converter where the circuit parasitic resistances impact the output voltage as the load current causes the duty cycle to increase to the level that it is approaching 100%

[0104] While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure.