Digital input circuit and method for high voltage sensors

Abstract

A digital input circuit includes a series connection of a current limiter and a switch having a switch control input coupled between a signal input and ground, and a logic level shifter coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output. A digital input method includes coupling an input signal to ground with a current limiter by closing an electronic switch, providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage and opening the electronic switch after the output signal is latched.

Claims

1. A digital input circuit comprising: a series connection of a current limiter and a switch coupled between a signal input and ground, wherein the switch has a switch control input; a logic level shifter including a voltage comparator and a low pass filter, the logic level shifter being coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output; a clock coupled to the low pass filter; and an N-counter coupling the clock to the switch control input.

2. A digital input circuit as recited in claim 1 wherein the voltage comparator has an input coupled to the signal input and an output coupled to the signal output by the low pass filter.

3. A digital input circuit as recited in claim 1 wherein the low pass filter is a digital low pass filter.

4. A digital input circuit as recited in claim 3 wherein the low pass filter comprises a plurality of bistable multivibrators.

5. A digital input circuit as recited in claim 4 wherein the bistable multivibrators comprise positive edge clock triggered flip-flops.

6. A digital input circuit as recited in claim 5 further comprising an AND gate having inputs coupled to outputs of the flip-flops and having an output providing the signal output.

7. A digital input circuit as recited in claim 1 further comprising a frequency divider coupling the clock to the low pass filter.

8. A digital input circuit comprising: a series connection of a first current limiter and switch coupled between a signal input and ground, wherein the switch has a switch control input; and a logic level shifter coupled to the signal input and having a first switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output; wherein the logic level shifter includes a current comparator having a current input coupled to the signal input and a current output and a second current limiter coupling the input of the current comparator to ground, wherein the first current limiter has a higher current limit than the second current limiter, and wherein the logic level shifter includes a voltage comparator having an input coupled to the signal input and an output coupled to the switch control by a one-shot monostable multivibrator.

9. A digital input circuit as recited in claim 8 further comprising a latch having a first input coupled to an output of the current comparator, a second input coupled to an output of the one-shot monostable multivibrator, and an output comprising the signal output.

10. A digital input method comprising: comparing an input signal to a reference threshold voltage activating a one-shot monostable multivibrator when the input signal exceeds the reference threshold voltage; coupling the input signal to ground with a current limiter by closing an electronic switch that is controlled by the activation of the one-shot monostable multivibrator; providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage; and opening the electronic switch after the output signal is latched.

11. A digital input method as recited in claim 10 further comprising providing debouncing between the input signal and the output signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Several example embodiments will now be described with reference to the drawings, wherein like components are provided with like reference numerals. The example embodiments are intended to illustrate, but not to limit, the invention. The drawings include the following figures:

(2) FIG. 1A is a schematic diagram of a first prior art digital input module;

(3) FIG. 1B is a schematic diagram of a second prior art digital input module;

(4) FIG. 2 is a block diagram of an example improved digital input module;

(5) FIG. 3 is a block diagram of a first example logic level shifter of FIG. 2;

(6) FIG. 4 is a schematic diagram of an example low pass filter of FIG. 4;

(7) FIG. 5 is a timing diagram illustrating an example operation of the example digital input module of FIGS. 2-4;

(8) FIG. 6 is a schematic diagram of a second example logic level shifter of FIG. 2;

(9) FIG. 7 is a timing diagram illustrating an example operation of the example digital input module of FIGS. 2, 4 and 6.

(10) FIG. 8 is a schematic diagram of a third example logic level shifter of FIG. 2;

(11) FIG. 9 is a timing diagram illustrating an example operation of the example digital input module of FIGS. 2, 4 and 8.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

(12) FIGS. 1A and 1B were described with reference to the prior art. FIG. 2 is a block diagram of an example improved digital input module 48 including an input resistor 50, and input capacitor 52, a current limiter 54, an electronic switch 56 and a logic level shifter 58. The current limiter 50 and the electronic switch 56 comprise a series connection 57 coupled, directly or indirectly, between the input voltage V.sub.i and ground. A sensor 60, illustrated here as a switch, couples the input resistor 50 to the field voltage supply V.sub.s (e.g. 24 VDC).

(13) As indicated by broken line 62, the current limiter 54, electronic switch 56 and logic level shifter 58 may form a part of a packaged integrated circuit, in an example embodiment. In another example embodiment, the components within broken line 62 may comprise discrete components. In a still further example embodiment, the components within broken line 62 may comprise a combination of discrete components and one or more packaged integrated circuits.

(14) In an embodiment, set forth by way of example but not limitation, the circuit 60 can comprise one channel of a plurality of channels. In this example embodiment, other components of the digital input module 48, such as input resistor 50 and input capacitor 62, may be provided externally, e.g. on a printed circuit (PC) board of the digital input module 48.

(15) FIG. 3 is a block diagram of a first non-limiting example logic level shifter 58A of FIG. 2. In this example, logic level shifter 58A includes a voltage/current comparator 64, a low pass filter 66, a clock 68 producing a clock signal CLK, and an inverter 70. An input of the comparator 64 is coupled to the input resistor 50 and to the current limiter 54 of FIG. 2. That is, in this example embodiment, the current limiter 54 is connected directly to the input voltage V.sub.i. Other inputs of the comparator 64 are connected to a threshold detection reference voltage V.sub.TH and to a threshold detection reference current i.sub.TH. The low pass filter 66 provides a debounce function in that it removes certain transients that might be present in the input signal (V.sub.i). In this example embodiment, the low pass filter 66 is a digital low pass filter, which is clocked by a signal CLK developed by the clock 68. The clock 68 can be an RC oscillator having a nominal frequency of about 125 KHz, although other frequencies are also suitable depending upon the low pass filter implementation and system requirements, as will be appreciated by those of skill in the art. A switch control signal S.sub.L is developed at the output of the inverter 70 and controls the electronic switch 56 (see also FIG. 2). Also, as will be appreciated by those of skill in the art, galvanic isolation can be provided by an external optocoupler, external digital isolator, or an integrated digital isolator, by way of non-limiting examples.

(16) FIG. 4 is a schematic diagram, set forth by way of example and not limitation, of a low pass filter 66 of FIG. 3. In this example, three bistable multivibrators 72, 74 and 76, and an AND gate 78 are used to debounce the high voltage input signal V.sub.i. In this non-limiting example, the multivibrators 72, 74, 76 are positive edge clock triggered D flip-flops having their clock inputs coupled to the CLK signal. The input signal V.sub.i is coupled to the D input of multivibrator 72, the Q output of the multivibrator 72 is coupled to the D input of multivibrator 74 and the Q output of multivibrator 74 is coupled to the D input of multivibrator 76. The AND gate 78 has inputs coupled to the Q outputs of the three multivibrators 72, 74, 76 and has an output of V.sub.o.

(17) FIG. 5 is a timing diagram illustrating an example operation of the of the example digital input module of FIGS. 2-4. In this non-limiting example, when the clock CLK is high (HI or 1), the switch control signal S.sub.L is low (LO or 0), opening switch 56, and when the clock CLK is low the switch control signal S.sub.L is high, closing the switch 56. Therefore, for every A cycle of the signal CLK, the switch 70 is open, and the current i.sub.L through the current limiter is zero. Therefore, in this example, the power use due to the current i.sub.L is decreased by about 50%.

(18) It will therefore be appreciated that the example embodiment of FIGS. 2-5, the same clock (or oscillator) 68 used to clock the digital low pass (debounce) filter 66 is used to control a switch 56 in series with current limiter 54 to turn the current flow off during the part of the cycle when the output of the detector 64 is not being sampled by the filter. By turning the input current i.sub.L off, when the signal is not being processed, power consumption decreases, and a power savings of about 50% or more can be achieved.

(19) The power savings are directly correlated to the on/off duty cycle of the current limiter 54. In one example embodiment, a first half of a clock cycle of clock CLK is used to turn the current limiter 54 ON and power the sensor 60 output circuitry. The duration of this half cycle must be long enough to provide enough settling time to charge any capacitances (parasitic or intentional) associated with the sensor 60 output and connection wiring.

(20) As will be appreciated by those of skill in the art, the electronic switch 56 can be implemented a variety of fashions. By way of non-limiting example, an N-channel MOSFET can be placed in series with the current limiter 54, thereby forming a series connection 57, with its gate coupled to the signal Si.

(21) FIG. 6 is a block diagram of a second non-limiting example logic level shifter 58B of FIG. 2, where like components will have like reference numbers with respect to the first non-limiting example logic level shifter 58A of FIG. 3. In this example, logic level shifter 58B includes a voltage/current comparator 64, a low pass filter 66 and a clock 68 producing a clock signal CLK. Logic level shifter 58B also includes a frequency divider 82 having a filter clock FCLK and an N-counter 80.

(22) In this non-limiting example, an input of the comparator 64 is coupled to the input resistor 50 and to the current limiter 54 of FIG. 2. That is, in this example embodiment, the current limiter 54 is connected directly to the input voltage V.sub.i. Other inputs of the comparator 64 are connected to a threshold detection reference voltage V.sub.TH and to the threshold detection reference current i.sub.TH. The low pass filter 66 provides debounce between the high-voltage (V.sub.i) and low voltage (V.sub.o) sides of the logic level shifter 58B. In this example embodiment, the low pass filter 66 is a digital low pass filter, which is clocked by the signal FCLK developed by the frequency divider 82. A switch control signal S.sub.L is developed at the output of the N-counter 80 and controls the electronic switch 56 (see also FIG. 2).

(23) With additional reference to the timing diagram of FIG. 7, the N-counter is designed to count N cycles of the clock CLK and to provide an output to inverter 70 when it reaches N cycles. In this example, when the clock signal FCLK is HI, the N-counter is reset and the signal SL is LO (0). When the clock signal FLCK is LO, the N-Counter starts counting cycles of the clock CLK. For example, in this case the N-counter 80 counts to N=1, and after counting one cycle of the clock CLK after FLCK goes low, the signal SL goes HI (1). In this way, the current i.sub.L flows through the current limiter 56 only 25% of the time, further decreasing power consumption, in this non-limiting examples. It will be appreciated that by increasing the relative frequency between CLK and FCLK, and by counting to higher numbers than N=1 in the N-counter 80, that even further power savings can be achieved.

(24) FIG. 8 is a schematic diagram of a third non-limiting example logic level shifter 58C of FIG. 2. In this example, logic level shifter 58C includes a voltage comparator 84, a current comparator 86, a low current limiter 88, a monostable multivibrator 80 and a latch 92. In this example embodiment, the monostable multivibrator 80 is a one-shot having a period t.sub.os and the latch 92 is formed by four NAND gates 94, 96, 98 and 100 connected in a T latch configuration. Inputs of voltage comparator 84 and current comparator 86 are coupled to the input resistor 50 of FIG. 2, in this example. Current I.sub.T=I.sub.L+I.sub.lo flows through the current comparator 86. Therefore, in this example, the current limiter 54 is coupled to the input voltage V.sub.i by current comparator 86 rather than being connected directly to V.sub.i. A reference voltage V.sub.TH is applied to an input of voltage comparator 84 and a reference current i.sub.TH flows through current comparator 86.

(25) It should be noted that, unlike the previous example embodiments, the example logic level shifter 58C of FIG. 8 does not require a clock (oscillator) or a low pass filter to perform debounce. Instead, one-shot 90 develops the signal S.sub.L to turn on and off the electronic switch 56 of FIG. 2. The current limiter 88 is provided to maintain a bias current on the current detector 86.

(26) With additional reference to the timing diagram of FIG. 9, in this non-limiting example the current limiter 88 is always on but is set to a low current value I.sub.lo which is considerably below the required current trip point threshold, I.sub.th. Voltage sensor 84 is constantly monitoring the input voltage V.sub.i. Any time the input voltage V.sub.i exceeds the reference threshold voltage V.sub.th, one-shot 90 is activated. The one shot closes the switch 56 permitting the current to rise to i.sub.T to cause current comparator 86 to develop a HI or 1 output V.sub.1C, to toggle latch 92.

(27) During the time that the one-shot 90 is activated (e.g. t.sub.os), if the value of the current detected by the current comparator 86 exceeds the threshold current I.sub.th, then the latch is toggled to a logical HI, indicating that a valid logic 1 has been detected from the sensor 60. If the current does not exceed I.sub.th, the latch is toggled to logical LO, indicating that current from the sensor was below the required threshold I.sub.th, and the sensor 60 signal is a logic 0. In this manner current is drawn and power is dissipated only during time t.sub.os, instead of during the entire time that the sensor is in the on state, T.sub.on. This reduces the average power dissipated by a factor of t.sub.os/T.sub.on. It will be appreciated by those of skill in the art that t.sub.os is preferably designed to be long enough to allow sufficient settling time to charge/discharge any parasitic and/or intentional capacitances associated with the sensor, its wiring and the input detection circuitry.

(28) Although various embodiments have been described using specific terms and devices, such description is for illustrative purposes only. The words used are words of description rather than of limitation. It is to be understood that changes and variations may be made by those of ordinary skill in the art without departing from the spirit or the scope of various inventions supported by the written disclosure and the drawings. In addition, it should be understood that aspects of various other embodiments may be interchanged either in whole or in part. It is therefore intended that the claims be interpreted in accordance with the true spirit and scope of the invention without limitation or estoppel.