Pipelined analog-to-digital converter incorporating variable input gain and pixel read out analog front end having the same

Abstract

A pipelined ADC incorporating variable input gain has a novel first stage generating a first digital output and a residue according to an analog input. The first stage comprises a novel MDAC. The MDAC comprises an operational amplifier, a feedback capacitor, a first sampling capacitor and a second sampling capacitor. First terminals of the feedback capacitor, the first sampling capacitor and the second sampling capacitor are connected to an inverted input terminal of the operational amplifier. A non-inverted input terminal of the operational amplifier is connected to a ground. In a sampling phase, second terminals of the feedback capacitor, the first sampling capacitor and the second sampling capacitor are connected to the analog input. In a charge transferring phase, second terminals of the feedback capacitor, the first sampling capacitor and the second sampling capacitor are respectively connected to the output terminal, a flash ADC output and the ground.

Claims

1. A pipelined analog-to-digital converter incorporating variable input gain, comprising: N stages coupled in cascade, N being an integer larger than 1, a first stage of the N stages generating a first digital output and a residue of the first stage according to an analog input, a N-th stage of the N stages acquiring the residue from a previous stage ((N1)th stage) to output an N-th digital output and a residue of the N-th stage; and an align and combine bits circuit, coupled to each of the N stages, acquiring the first digital output to N-th digital output to generate M-bits digital output, where M>N; wherein the first stage comprises: a flash analog-to-digital converter (flash ADC), generating a flash ADC output according to the analog input; and a multiplying digital-to-analog converter (MDAC), comprising an operational amplifier, a feedback capacitor, a first sampling capacitor and a second sampling capacitor, wherein a first terminal of the feedback capacitor, a first terminal of the first sampling capacitor and a first terminal of the second sampling capacitor are connected to an inverted input terminal of the operational amplifier, a non-inverted input terminal of the operational amplifier is connected to a ground; wherein the multiplying digital-to-analog converter (MDAC) operates in a sampling phase and a charge transferring phase; wherein in the sampling phase a second terminal of the feedback capacitor, a second terminal of the first sampling capacitor and a second terminal of the second sampling capacitor are connected to the analog input, an output terminal of the operational amplifier is connected to the inverted input terminal of the operational amplifier; wherein in the charge transferring phase the second terminal of the feedback capacitor is connected to the output terminal of the operational amplifier, the second terminal of the first sampling capacitor is connected to a corresponding reference voltage related to the flash ADC output, the second terminal of the second sampling capacitor is connected to the ground; wherein the residue of the first stage is an output of the multiplying digital-to-analog converter (MDAC) provided by the output terminal of the operational amplifier.

2. The pipelined analog-to-digital converter incorporating variable input gain according to claim 1, wherein the output of the multiplying digital-to-analog converter (MDAC) is given by the following equation: $V_{\mathrm{res}1}=\frac{C_F+C_{S1}+C_{S2}}{C_F}{V}_i-\frac{C_{S1}}{C_F}{V}_{\mathrm{DAC}\_\mathrm{ref}},$ where C.sub.F is the capacitance of the feedback capacitor, C.sub.S1 is the capacitance of the first sampling capacitor, C.sub.S2 is the capacitance of the second sampling capacitor, V.sub.i is the analog input, and V.sub.DAC.sub._.sub.ref is the corresponding reference voltage related to the flash ADC output.

3. The pipelined analog-to-digital converter according to claim 1, wherein the multiplying digital-to-analog converter (MDAC) is a switched-capacitor circuit.

4. The pipelined analog-to-digital converter incorporating variable input gain according to claim 3, wherein the output of the flash analog-to-digital converter (flash ADC) is given by the following equation: $V_o=\{\begin{array}{c}1\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)0\\ 0\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)<0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)<0\end{array},$ where V.sub.i is the analog input, V.sub.ADC.sub._.sub.ref/k is the reference voltage, k is a variable input gain of the analog input.

5. The pipelined analog-to-digital converter incorporating variable input gain according to claim 4, wherein the reference voltage is generated from a resistor string.

6. The pipelined analog-to-digital converter incorporating variable input gain according to claim 1, wherein the flash analog-to-digital converter (flash ADC) operates in a reset phase and a compare phase, the flash analog-to-digital converter (flash ADC) comprises: a regenerative amplifier, having an inverted input terminal and a non-inverted input terminal and an output terminal, the inverted input terminal connected to the ground; and a third sampling capacitor, a first terminal of the third sampling capacitor connected to the non-inverted input terminal of the regenerative amplifier; wherein in the reset phase a second terminal of the third sampling capacitor is connected to a reference voltage, the first terminal of the third sampling capacitor is connected to the ground; wherein in the compare phase the second terminal of the third sampling capacitor is connected to the analog input.

7. The pipelined analog-to-digital converter incorporating variable input gain according to claim 1, wherein the analog input is converted by the pixel array from a light signal of an optical computer mouse.

8. The pipelined analog-to-digital converter according to claim 1, wherein the pipelined analog-to-digital converter further comprises a sample and hold circuit connected between the first stage and a pixel array.

9. A pixel read out analog front end, comprising: a pixel array, generating an analog input; and a pipelined analog-to-digital converter incorporating variable input gain, coupled to the pixel array, comprising: N stages coupled in cascade, N being an integer larger than 1, a first stage of the N stages generating a first digital output and a residue of the first stage according to the analog input, an N-th stage of the N stages acquiring the residue from a previous stage ((N1)th stage) to output an N-th digital output and a residue of the N-th stage; and an align and combine bits circuit, coupled to each of the N stages, acquiring the first digital output to N-th digital output to generate M-bits digital output, where M>N; wherein the first stage comprises: a flash analog-to-digital converter (flash ADC), generating a flash ADC output according to the analog input; and a multiplying digital-to-analog converter (MDAC), comprising an operational amplifier, a feedback capacitor, a first sampling capacitor and a second sampling capacitor, wherein a first terminal of the feedback capacitor, a first terminal of the first sampling capacitor and a first terminal of the second sampling capacitor are connected to an inverted input terminal of the operational amplifier, a non-inverted input terminal of the operational amplifier is connected to a ground; wherein the multiplying digital-to-analog converter (MDAC) operates in a sampling phase and a charge transferring phase; wherein in the sampling phase a second terminal of the feedback capacitor, a second terminal of the first sampling capacitor and a second terminal of the second sampling capacitor are connected to the analog input, an output terminal of the operational amplifier is connected to the inverted input terminal of the operational amplifier; wherein in the charge transferring phase the second terminal of the feedback capacitor is connected to the output terminal of the operational amplifier, the second terminal of the first sampling capacitor is connected to a corresponding reference voltage related to the flash ADC output, the second terminal of the second sampling capacitor is connected to the ground; wherein the residue of the first stage is an output of the multiplying digital-to-analog converter (MDAC) provided by the output terminal of the operational amplifier.

10. The pixel read out analog front end according to claim 9, further comprising: a buffer, coupled between the pixel array and the pipelined analog-to-digital converter.

11. The pixel read out analog front end according to claim 9, wherein the output of the multiplying digital-to-analog converter (MDAC) is given by the following equation: $V_{\mathrm{res}1}=\frac{C_F+C_{S1}+C_{S2}}{C_F}{V}_i-\frac{C_{S1}}{C_F}{V}_{\mathrm{DAC}\_\mathrm{ref}},$ where C.sub.F is the capacitance of the feedback capacitor, C.sub.S1 is the capacitance of the first sampling capacitor, C.sub.S2 is the capacitance of the second sampling capacitor, V.sub.i is the analog input, and V.sub.DAC.sub._.sub.ref is the corresponding reference voltage related to the flash ADC output.

12. The pixel read out analog front end according to claim 9, wherein the multiplying digital-to-analog converter (MDAC) is a switched-capacitor circuit.

13. The pixel read out analog front end according to claim 9, wherein the flash analog-to-digital converter (flash ADC) operates in a reset phase and a compare phase, the flash analog-to-digital converter (flash ADC) comprises: a regenerative amplifier, having an inverted input terminal and a non-inverted input terminal and an output terminal, the inverted input terminal connected to the ground; and a third sampling capacitor, a first terminal of the third sampling capacitor connected to the non-inverted input terminal of the regenerative amplifier; wherein in the reset phase a second terminal of the third sampling capacitor is connected to a reference voltage, the first terminal of the third sampling capacitor is connected to the ground; wherein in the compare phase the second terminal of the third sampling capacitor is connected to the analog input.

14. The pixel read out analog front end according to claim 13, wherein the output of a comparator in the flash analog-to-digital converter (flash ADC) is given by the following equation: $V_o=\{\begin{array}{c}1\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)0\\ 0\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)<0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)<0\end{array},$ where V is the analog input, V.sub.ADC.sub._.sub.ref/k is the reference voltage, k is a variable input gain of the analog input.

15. The pixel read out analog front end according to claim 14, wherein the reference voltage is generated from a resistor string.

16. The pixel read out analog front end according to claim 9, wherein the analog input is converted by the pixel array from a light signal of an optical computer mouse.

17. The pixel read out analog front end according to claim 9, wherein the pipelined analog-to-digital converter further comprises a sample and hold circuit connected between the first stage and the pixel array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a block diagram of a conventional pixel read out analog front end;

(2) FIG. 2 shows a block diagram of a pixel read out analog front end according to an embodiment of the instant disclosure;

(3) FIG. 3 shows a block diagram of a pipelined analog-to-digital converter incorporating variable input gain according to an embodiment of the instant disclosure;

(4) FIG. 4 shows a block diagram of a first stage of the N stages of the pipelined analog-to-digital converter shown in FIG. 3;

(5) FIG. 5 shows a block diagram of conventional flash ADCs for all stages with an encoding logic block;

(6) FIG. 6A shows a circuit diagram of a comparator in a flash ADC operating in a reset phase according to an embodiment of the instant disclosure;

(7) FIG. 6B shows a circuit diagram of a comparator in a flash ADC operating in a compare phase according to an embodiment of the instant disclosure;

(8) FIG. 7A shows a circuit diagram of a multiplying digital-to-analog converter (MDAC) operating in a sampling phase according to an embodiment of the instant disclosure;

(9) FIG. 7B shows a circuit diagram of a multiplying digital-to-analog converter (MDAC) operating in a charge transferring phase according to an embodiment of the instant disclosure;

(10) FIG. 8A shows a circuit diagram of a conventional transfer amplifier (TA) operating in a sampling phase;

(11) FIG. 8B shows a circuit diagram of a conventional transfer amplifier (TA) operating in a charge transferring phase;

(12) FIG. 9A shows a circuit diagram of a conventional multiplying digital-to-analog converter (MDAC) operating in a sampling phase; and

(13) FIG. 9B shows a circuit diagram of a conventional multiplying digital-to-analog converter (MDAC) operating in a charge transferring phase.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(14) The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the instant disclosure. Other objectives and advantages related to the instant disclosure will be illustrated in the subsequent descriptions and appended drawings.

(15) Please refer to FIG. 2 showing a block diagram of a pixel read out analog front end according to an embodiment of the instant disclosure. The pixel read out analog front end comprises a pixel array 1, a buffer 5 and a pipelined analog-to-digital converter 6 incorporating variable input gain. The buffer 5 coupled between the pixel array 1 and the pipelined analog-to-digital converter 6 can be used for reducing the operation current of the pipelined analog-to-digital converter 6. The buffer 5, which will be described hereinafter, is used to reduce the overall operation current (or power consumption) of the pixel read out analog front end shown in FIG. 2. The pixel array 1 generates an analog input Vin. The pipelined analog-to-digital converter 6 is coupled to the pixel array through the buffer 5. However, the buffer 5 is not necessary for the pixel read out analog front end.

(16) Please refer to FIG. 3 showing a block diagram of a pipelined analog-to-digital converter incorporating variable input gain according to an embodiment of the instant disclosure. The pipelined analog-to-digital converter 6 comprises a sample and hold circuit 63, N stages coupled in cascade (61 . . . 6N1, and 6N) and an align and combine bits circuit 62. The number N is an integer larger than 1.

(17) The sample and hold circuit 63 is connected between a first stage 61 and the pixel array 1. The analog input V.sub.in generated from the pixel array 1 is converted from a light signal of an optical computer mouse. The analog input V.sub.in first passes through the sample and hold circuit 63 such as a sample and hold amplifier (SHA), if it is not a sampled-and-hold signal. The first stage 61 of the N stages generates a first digital output D.sub.1 and a residue V.sub.res1 of the first stage 61 according to the analog input V.sub.in. In detail, the first stage consists of a coarse ADC and DAC (will be described in FIG. 4 in detail) to generate the most significant bit (MSB) portion (D.sub.1) of a final ADC output (D.sub.out) and an amplified residue voltage (V.sub.res1) for conversion in a second stage and so on until the last stage (stage N). That is, an N-th stage of the N stages acquires the residue from a previous stage ((N1)th stage) to output an N-th digital output and a residue of the N-th stage. For example, the (N1)th stage 6N1 acquires the residue from the previous stage (N2)th stage to output N1 digital out and a residue of the (N1)th stage.

(18) The align and combine bits circuit 62 is coupled to each of the N stages for acquiring the first digital output to N-th digital output to generate M-bits digital output D.sub.out, where M>N. The first digital output to the N-th digital output can be n-bits. In fact, individual stage in a pipelined ADC may not have equal number of n-bit output. As individual stage in a pipelined ADC may generate more than 1-bit so that the final digital output provided by the align and combine bits circuit 62 could be M-bit resolution where M>N. The digital align and combine bits circuit 62 properly aligns the individual stage outputs (D.sub.1, D.sub.2, . . . D.sub.N) to generate the final multi-bit output D.sub.out corresponding to the sampled V.sub.in with certain latency depending on the number of stages.

(19) The architecture of the pipelined analog-to-digital converter 6 is the same to the architecture of the conventional pipelined analog-to-digital converter 3 except that the first stage 61 of the pipelined analog-to-digital converter 6 is different from the conventional first stage of the conventional pipelined analog-to-digital converter. However, the architecture of the pipelined analog-to-digital converter of the instant disclosure is not so restricted. An artisan of ordinary skill in the art will appreciate the implementation manner of the architecture of the conventional pipelined analog-to-digital converter (abbreviate as pipelined ADC). Furthermore, compared to FIG. 1, by utilizing the provided pipelined ADC 6, the conventional transfer amplifier 2 is not required. The function of the provided pipelined ADC 6 has both the functions of the conventional transfer amplifier 2 and the conventional pipelined ADC 3. Details of the first stage 61 will be described in the following.

(20) Refer to FIG. 4 showing a block diagram of a first stage of the N stages of the pipelined ADC shown in FIG. 3. The first stage 61 comprises a flash analog-to-digital converter (flash ADC) 611 and a multiplying digital-to-analog converter (MDAC) 612. The flash analog-to-digital converter (flash ADC) 611 generates a flash ADC output D.sub.1 according to the analog input V.sub.in. Referring to FIG. 5 showing a block diagram of conventional flash ADCs for all stages with an encoding logic block. A B-bit flash ADC employs 2.sup.B1 comparators to compare the analog input V.sub.in against a set of reference voltage to form a B-bit output as shown in FIG. 5. The operation of the flash ADCs for all stages with the encoding logic block can be appreciated by an artisan of ordinary skill in the art, thus there is no need to go into detail. Details of the circuit of the flash ADC are described in the following. Please refer to FIG. 6A in conjunction with FIG. 6B. Each comparator of FIG. 5 is implemented in the single ended form. The flash ADC comprises a regenerative amplifier 611a and a sampling capacitor 611b. The regenerative amplifier 611a has an inverted input terminal and a non-inverted input terminal and an output terminal. The inverted input terminal of the regenerative amplifier 611a is connected to the ground. The sampling capacitor 611b has a first terminal and a second terminal. The first terminal of the sampling capacitor 611b is connected to the non-inverted input terminal of the regenerative amplifier 611a. The flash ADC operates in a reset phase and a compare phase. In the reset phase, referring to FIG. 6A, the second terminal of the sampling capacitor 611b is connected to a reference voltage V.sub.DAC-ref, the first terminal of the sampling capacitor 611b is connected to the ground. The sampling capacitor 611b is pre-charged to the desired reference voltage V.sub.DAC-ref while the regenerative amplifier 611a is off. In the compare phase, referring to FIG. 6B, the regenerative amplifier 611a is in operation. The second terminal of the sampling capacitor 611b is connected to the analog input V.sub.in. And, the first terminal of the sampling capacitor 611b returns to connect with the non-inverted input terminal of the regenerative amplifier 611a. Then, the regenerative amplifier 611a can output the compare result. The output of a comparator in the flash analog-to-digital converter (flash ADC) is given by the following equation:

(21) $V_o=\{\begin{array}{c}1\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)0\\ 0\mathrm{if}\left(V_i-V_{\mathrm{ADC}\_\mathrm{ref}}/k\right)<0\mathrm{or}\left(k{V}_i-V_{\mathrm{ADC}\_\mathrm{ref}}\right)<0\end{array},$
where V.sub.i is the analog input (Vin), V.sub.ADC.sub._.sub.ref/k is the reference voltage, and k is a variable input gain of the analog input (Vin). The number k which is described hereinafter is corresponding to the gain of the conventional transfer amplifier (TA). The reference voltage can be generated from a resistor string and the scaled down version of V.sub.ADC.sub._.sub.ref could be easily obtained by dividing the resistor into finer segments with minimal penalty to the silicon area.

(22) Then, please refer to FIG. 7A and FIG. 7B. The multiplying digital-to-analog converter (MDAC) 612 can be implemented using a switched-capacitor circuit. The multiplying digital-to-analog converter (MDAC) 612 operates in a sampling phase referring to FIG. 7A and a charge transferring phase referring to FIG. 7B. The multiplying digital-to-analog converter (MDAC) 612 comprises an operational amplifier 612a, a feedback capacitor C.sub.F, a first sampling capacitor C.sub.1 and a second sampling capacitor Cs.sub.2. A first terminal of the feedback capacitor C.sub.F, a first terminal of the first sampling capacitor C.sub.1 and a first terminal of the second sampling capacitor C.sub.S2 are connected to an inverted input terminal of the operational amplifier 612a. A non-inverted input terminal of the operational amplifier 612b is connected to the ground. In the sampling phase, referring to FIG. 7A, a second terminal of the feedback capacitor C.sub.F, a second terminal of the first sampling capacitor C.sub.1 and a second terminal of the second sampling capacitor C.sub.S2 are connected to the analog input V.sub.in. At the same time, an output terminal of the operational amplifier 612a is connected to the inverted input terminal of the operational amplifier 612a. In the charge transferring phase, referring to FIG. 7B, the second terminal of the feedback capacitor C.sub.F is connected to the output terminal of the operational amplifier 612a. At the same time, the second terminal of the first sampling capacitor C.sub.S1 is connected to a corresponding reference voltage V.sub.ADC.sub._.sub.ref (this reference voltage will minimize the output residue voltage of the MDAC) related to the flash ADC output, and the second terminal of the second sampling capacitor C.sub.S2 is connected to the ground. The residue V.sub.res1 of the first stage 61 is the output of the multiplying digital-to-analog converter (MDAC) 612a provided by the output terminal of the operational amplifier 612a.

(23) Before describing the output of the multiplying digital-to-analog converter (MDAC) 612, we discuss the conventional transfer amplifier (TA) and the conventional multiplying digital-to-analog converter (MDAC). The architecture of the multiplying digital-to-analog converter (MDAC) 612 combines the conventional transfer amplifier (TA) and the conventional multiplying digital-to-analog converter (MDAC). Please refer to FIG. 8A and FIG. 8B respectively showing a circuit diagram of a conventional transfer amplifier (TA) operating in a sampling phase and a charge transferring phase. The transfer amplifier operates in two phases, namely the sampling phase and charge transferring phase. In the sampling phase, the input is sampled by the sampling capacitor C.sub.S while the feedback capacitor C.sub.F is fully discharged. In the subsequent charge transferring phase, the charge stored in the sampling capacitor C.sub.S is fully transferred to the feedback capacitor C.sub.F and the output voltage V.sub.o is given by V.sub.o=(C.sub.S/C.sub.F)Vi whereby the ratio of C.sub.S and C.sub.F determines the transfer amplifier gain ranging typically from 2 to 4 (i.e. Cs>C.sub.F).

(24) Then, please refer to FIG. 9A and FIG. 9B. FIG. 9A shows a circuit diagram of a conventional multiplying digital-to-analog converter (MDAC) operating in a sampling phase. FIG. 9B shows a circuit diagram of a conventional multiplying digital-to-analog converter (MDAC) operating in a charge transferring phase. Similar to the transfer amplifier (TA), the MDAC operates in two phases. During the sampling phase, the input V.sub.1 is sampled by capacitors C.sub.A and C.sub.B in parallel. During the charge transferring phase, the capacitor C.sub.A is flipped around the operational amplifier to become the feedback capacitor while the capacitor C.sub.B is connected to a variable reference voltage (V.sub.ref) whose value depends on the flash ADC output.

(25) The output of the MDAC is given by the following equation:

(26) $V_o=\frac{C_A+C_B}{C_A}{V}_i-\frac{C_B}{C_A}{V}_{\mathrm{ref}}$

(27) It can be seen that the residue output V.sub.o is equal to the difference of V.sub.i multiplied by (1+C.sub.B/C.sub.A) and V.sub.ref scaled by a factor of C.sub.B/C.sub.A. For C.sub.B=3C.sub.A, the residue is V.sub.o=4V.sub.i3V.sub.ref.

(28) By comparing the MDAC 612 with the conventional transfer amplifier (TA), referring to FIG. 7A, FIG. 7B in conjunction with FIG. 8A, FIG. 8B, the feedback capacitor C.sub.F of the MDAC 612 can be considered as the feedback capacitor C.sub.F of the transfer amplifier (TA) shown in FIG. 8A and FIG. 8B due to similar operation. Also, the second sampling capacitor C.sub.S2 of the MDAC 612 can be considered as the sampling capacitor C.sub.S due to similar operation of the second sampling capacitor C.sub.S2 and the sampling capacitor C.sub.S.

(29) By comparing the MDAC 612 with the conventional MDAC, referring to FIG. 7A, FIG. 7B in conjunction with FIG. 9A, FIG. 9B, the feedback capacitor C.sub.F of the MDAC can be considered as the capacitor C.sub.A of the conventional multiplying digital-to-analog converter (MDAC) shown in FIG. 9A and FIG. 9B due to similar operation of the feedback capacitor C.sub.F and the capacitor C.sub.A. Also, the first sampling capacitor C.sub.S1 of the MDAC 612 can be considered as the capacitor C.sub.B. As a result, compared to utilizing the conventional transfer amplifier (TA) and the conventional MDAC, one operational amplifier (used in the transfer amplifier (TA)) can be saved by removing the conventional transfer amplifier (TA) and utilizing the provided MDAC 612 of this embodiment.

(30) The output of the multiplying digital-to-analog converter (MDAC) 612 is given by the following equation:

(31) $V_{\mathrm{res}1}=\frac{C_F+C_{S1}+C_{S2}}{C_F}{V}_i-\frac{C_{S1}}{C_F}{V}_{\mathrm{DAC}\_\mathrm{ref}},$

(32) where C.sub.F is the capacitance of the feedback capacitor, C.sub.S1 is the capacitance of the first sampling capacitor, Cs.sub.2 is the capacitance of the second sampling capacitor, V.sub.i is the analog input (Vin), and V.sub.DAC.sub._.sub.ref is a corresponding reference voltage related to the flash ADC output. By matching the V.sub.i multiplying factor of (C.sub.F+C.sub.S1+C.sub.S2)/C.sub.F=k*(C.sub.A+C.sub.B)/C.sub.A of the conventional first stage MDAC of the pipelined ADC where k=TA gain in the conventional scheme (FIG. 1), we can effectively achieve the same effect of converting the amplified pixel signal through a TA provided. We also can match the second term factor of C.sub.S1/C.sub.F=C.sub.B/C.sub.A in the conventional scheme. Also, as aforementioned the flash ADC 611 of the first stage 61 has taken into account the effective TA gain of k in the pipelined ADC of this embodiment. Therefore, the provided pixel read out analog front end shown in FIG. 2 of the instant disclosure can replace the conventional pixel read out analog front end shown in FIG. 1.

(33) Furthermore, compared with the conventional pixel read out analog front end shown in FIG. 1, the buffer 5 shown in FIG. 2 can reduce the consumed current due to higher capacitive load from MDAC 612 of the first stage 61 (referring to FIG. 7A) especially for high k, in order to reduce the overall operation current of the pixel read out analog front end shown in FIG. 2. The power consumption of the added buffer 5 coupled between the pixel array 1 and the pipelined ADC 6 can be less than the power consumption of the transfer amplifier (TA) (and power consumption of a source follower) used in the conventional pixel read out analog front end. That is, when replacing the conventional pixel read out analog front end shown in FIG. 1 by the provided pixel read out analog front end shown in FIG. 2, the provided pixel read out analog front end can have lower power consumption compared to the conventional pixel read out analog front end because of removing the transfer amplifier (TA) but adding the buffer 5. In an application of gaming computer mouse design, when considering an 8-bit pipelined ADC at 50 MS/s operation, power saving of 25% to 34% can be expected when k ranges from 2 to 4, and the feedback capacitor C.sub.F is the same as (or half of) the feedback capacitor C.sub.F of the conventional transfer amplifier (TA) (referring to FIG. 8A and FIG. 8B). Furthermore, the silicon area of the provided pixel read out analog front end can be saved because of not using the conventional transfer amplifier. More than 10% saving in the silicon area can be expected compared to the conventional transfer amplifier (TA) and pipelined ADC scheme (FIG. 1). It is envisaged that the saving in terms of silicon area and power could be even more substantial when the sampling speed of TA and ADC is increased further in the future high-end gaming mouse design.

(34) According to above description, a pipelined ADC incorporating variable input gain is provided by using a novel first stage. The provided pixel read out analog front end having the pipelined ADC incorporating variable input gain can replace the conventional pixel read out analog front end. The provided architecture of the provided pixel read out analog front end can save power consumption and save the silicon area compared to the conventional pixel read out analog front end.

(35) The descriptions illustrated supra set forth simply the preferred embodiments of the instant disclosure; however, the characteristics of the instant disclosure are by no means restricted thereto. All changes, alterations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the instant disclosure delineated by the following claims.