Time amplifier and method for controlling the same

Abstract

Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch.

Claims

1. A time amplifier comprising: an SR latch providing two output signals having an output time difference, which is determined according to an input time difference between two input signals of the time amplifier; and an operation determination unit connected to a power of the SR latch and configured to determine an operation of the SR latch, wherein the operation determination unit comprises: a first operation determination unit connected to an input power of the SR latch and configured to determine a gain between the input time difference and the output time difference; and a second operation determination unit connected to an output power of the SR latch and configured to determine an available input range of the input time difference, wherein the input time difference and the output time difference of the time amplifier maintain linearity, wherein the first operation determination unit and the second operation determination unit comprise transistor, respectively, and wherein the gain and the available input range are determined, by adjusting a bias voltage of the transistor.

2. The time amplifier of claim 1, wherein the SR latch comprises a first NAND gate and a second NAND gate performing a NAND operation.

3. The time amplifier of claim 1, wherein the SR latch comprises a first NOR gate and a second NOR gate performing a NOR operation.

4. The time amplifier of claim 1, wherein the second operation determination unit comprises a current mirror determining the output power of the SR latch according to the bias voltage applied to a gate of the current mirror.

5. The time amplifier of claim 1, wherein the input power supplies a first adjustable voltage.

6. The time amplifier of claim 5, wherein the gain of the time amplifier is adjusted by adjusting the first adjustable voltage.

7. The time amplifier of claim 1, wherein the output power supplies a second adjustable voltage.

8. The time amplifier of claim 7, wherein the available input range of the time amplifier is adjusted by adjusting the second adjustable voltage.

9. A time amplifier comprising: a first delay unit outputting a first delay input signal by delaying a first input signal of the time amplifier by a predetermined time; a second delay unit outputting a second delay input signal by delaying a second input signal of the time amplifier by a predetermined time; a first SR latch providing an output at a timing determined according to an input time difference between the first delay input signal and the second input signal; a second SR latch providing an output at a timing determined according to the input time difference between the first input signal and the second delay input signal; a first SR latch operation determination unit connected to a power of the first SR latch and configured to determine an operation of the first SR latch; a second SR latch operation determination unit connected to a power of the second SR latch and configured to determine an operation of the second SR latch; a first XOR gate outputting a first output signal by performing an XOR operation on the output of the first SR latch; and a second XOR gate outputting a second output signal by performing an XOR operation on the output of the second SR latch, wherein the first SR latch operation determination unit comprises: a first operation determination unit connected to an input power of the first SR latch and configured to determine a gain between the input time difference and an output time difference between the first output signal and the second output signal; and a second operation determination unit connected to an output power of the first SR latch and configured to determine an available input range of the input time difference, in which, wherein the second SR latch operation determination unit comprises: a third operation determination unit connected to an input power of the second SR latch and configured to determine the gain between the input time difference and the output time difference; and a fourth operation determination unit connected to an output power of the second SR latch and configured to determine the available input range of the input time difference, wherein the input time difference and the output time difference of the time amplifier maintain linearity, wherein the first operation determination unit, the second operation determination unit, the third operation determination unit, and the fourth operation determination unit comprise transistor, respectively, and wherein the gain and the available input range are determined, by adjusting a bias voltage of the transistor.

10. The time amplifier of claim 9, wherein the second operation determination unit comprises a current mirror determining the output power of the first SR latch according to the bias voltage applied to a gate of the current mirror.

11. The time amplifier of claim 9, wherein the fourth operation determination unit comprises a current mirror determining the output power of the second SR latch according to the bias voltage applied to a gate of the current mirror.

12. The time amplifier of claim 9, wherein the gain of the time amplifier is adjusted by adjusting the input power of the first SR latch or the input power of the second SR latch.

13. The time amplifier of claim 9, wherein the available input range of the time amplifier is adjusted by adjusting the output power of the first SR latch or the output power of the second SR latch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:

(2) FIG. 1 is a circuit diagram of a time amplifier according to an embodiment of the present invention;

(3) FIG. 2 is a circuit diagram of a time amplifier including an operation determination unit according to an embodiment of the present invention;

(4) FIG. 3 is a circuit diagram of an SR latch according to another embodiment of the present invention;

(5) FIG. 4 is a circuit diagram of an SR latch connected to an operation determination unit according to an embodiment of the present invention;

(6) FIG. 5 is a circuit diagram of an SR latch connected to a first operation determination unit according to another embodiment of the present invention;

(7) FIG. 6 is a circuit diagram of an SR latch connected to a first operation determination unit according to another embodiment of the present invention;

(8) FIG. 7 is a circuit diagram of an SR latch connected to a second operation determination unit according to another embodiment of the present invention;

(9) FIG. 8 is a circuit diagram of an SR latch connected to a second operation determination unit according to another embodiment of the present invention;

(10) FIG. 9 is a circuit diagram of a time amplifier according to another embodiment of the present invention;

(11) FIG. 10 is a circuit diagram of a time amplifier according to another embodiment of the present invention;

(12) FIG. 11 is a flowchart illustrating a method of controlling a time amplifier according to an embodiment of the present invention;

(13) FIG. 12 is a flowchart illustrating a method of calculating a gain according to an embodiment of the present invention; and

(14) FIG. 13 is a flowchart illustrating a method of controlling a time amplifier according to another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(15) Advantages and features of the present invention, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Further, the present invention is only defined by scopes of claims.

(16) Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meanings generally accepted by universal techniques in the art. Terms defined by general dictionaries are interpreted as having the same meanings as that in related techniques and/or this specification and if not clearly defined, are not conceptualized or not be interpreted as being overly excessive.

(17) In the following description, the technical terms are used only for explaining specific embodiments while not limiting the present invention. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of include, comprise, including, or comprising, specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

(18) The term unit, device, block, or module may mean a unit for processing at least one function or operation. For example, the term unit, device, block, or module may means a software component or a hardware component such as an FPGA or an ASIC. However, unit, device, block, or module is not limited to software or hardware. unit, device, block, or module may be configured to be stored on an addressable storage medium and may be configured to execute at least one processor.

(19) Accordingly, for example, unit, device, block, or module may include components (e.g., software components, object oriented software components, class components, and task components), processes, functions, attributes, procedures, sub routines, program code segments, drivers, firmware, micro code, circuits, data, database, data structures, tables, arrays, and parameters. Functions provided in components and unit, device, block, or module may be combined in less components and unit, device, block, or module or may be further separated in more additional components and unit, device, block, or module.

(20) According to an embodiment of the present invention, at least one of a gain and an input range of a time amplifier may be adjusted by adjusting a power of an SR latch therein. Additionally, according to an embodiment of the present invention, when both a gain and an input range of a time amplifier are adjusted, they may be adjusted separately not affecting each other.

(21) Hereinafter, it will be described about an exemplary embodiment of the present invention in conjunction with the accompanying drawings.

(22) FIG. 1 is a circuit diagram of a time amplifier according to an embodiment of the present invention.

(23) As shown in FIG. 1, the time amplifier 100 includes SR latches 121 and 122.

(24) The SR latches 121 and 122 provide an output at the timing determined according to a time difference between two inputs inputted to the SR latches 121 and 122. The timing at which the SR latches 121 and 122 provide an output may be determined according to a time difference between two inputs due to the metastability of a transistor configuring the SR latches 121 and 122.

(25) Additionally, the time amplifier 100 may include an operation determination unit for determining an operation of an SR latch connected to a power terminal of the SR latches 121 and 122.

(26) FIG. 2 is a circuit diagram of a time amplifier including an operation determination unit according to an embodiment of the present invention.

(27) As shown in FIG. 2, the time amplifier 100 includes operation determination units 131, 132, 133, and 134 connected to a power terminal of the SR latches 121 and 122 to determine an operation of an SR latch.

(28) If the time amplifier 100 of FIGS. 1 and 2 are described in more detail, it includes a first delay unit 111, a second delay unit 112, a first SR latch 121, a second SR latch 122, first SR latch operation determination units 131 and 132, second SR latch operation determination units 133 and 134, a first XOR gate 141, and a second XOR gate 142.

(29) The first delay unit 111 may output a first delay input signal by delaying a first input signal IN1 by a predetermined time T.sub.off. The second delay unit 112 may output a second delay input signal by delaying a second input signal IN2 by the predetermined time T.sub.off.

(30) Each of the first delay unit 111 and the second delay unit 112 may include at least one buffer. The number of buffers may be determined the predetermined time T.sub.off.

(31) The first SR latch 121 may provide an output at the timing determined according a time difference between the first delay input signal and the second input signal IN2. The second SR latch 122 may provide an output at the timing determined according a time difference between the first input signal IN1 and the second delay input signal.

(32) Each of the SR latches 121 and 122 shown in FIGS. 1 and 2 are configured with two NAND gates, that is, a first NAND gates 1211 or 1221 and a second NAND gate 1212 or 1222 performing NAND operations, but according to an embodiment of the present invention, the SR latch 121 or 122 may include two NOR gates, that is, a first NOR gate 1231 and a second NOR gate 1232, as shown in FIG. 3,

(33) The operation determination units 131, 132, 133, and 134 may be connected to the power terminal of the SR latches 121 and 122 to determine operations thereof. For example, the first SR latch operation determination units 131 and 132 are connected to the power terminal of the first SR latch 121 to determine an operation of the first SR latch 121 and the second SR latch operation determination units 133 and 134 are connected to the power terminal of the second SR latch 122 to determine an operation of the second SR latch 122.

(34) According to an embodiment of the present invention, the operation determination unit may include a first operation determination unit connected to the power input terminal of an SR latch. For example, the first SR latch operation determination unit may include a first operation determination unit 131 connected to the power input terminal of the first SR latch 121. Additionally, the second SR latch operation determination unit may include a third operation determination unit 133 connected to the power input terminal of the second SR latch 122.

(35) According to an embodiment of the present invention, as shown in FIG. 2, each of the first operation determination unit 131 and the second operation determination unit 133 may include a transistor. The transistor may determine a power input of the SR latches 121 and 122 according to a bias voltage V.sub.head supplied to the gate of the transistor.

(36) FIG. 4 is a circuit diagram of the first SR latch 121 connected to the first operation determination unit 131 according to an embodiment of the present invention.

(37) According to an embodiment of the present invention, a gain of the time amplifier may be adjusted by adjusting a bias voltage V.sub.head supplied to the gate of the transistor. That is, a gain of the time amplifier 100 may be determined by a bias voltage V.sub.head.

(38) According to an embodiment of the present invention, as the bias voltage V.sub.head becomes higher, a gain of the time amplifier 100 may become higher. On the contrary, as the bias voltage V.sub.head becomes lower, a gain of the time amplifier 100 may become lower.

(39) According to another embodiment of the present invention, each of the first operation determination unit 131 and the third operation determination unit 133 may include a current mirror.

(40) FIG. 5 is a circuit diagram of the first SR latch connected to the first operation determination unit 131 according to another embodiment of the present invention.

(41) As shown in FIG. 5, the first operation determination unit 131 may include a current mirror. The current mirror may determine a power input of the SR latch 121 according to the bias voltage V.sub.head supplied to a gate.

(42) According to this embodiment, the present invention adjusts a gain of the time amplifier 100 by adjusting the bias voltage V.sub.head of the current mirror.

(43) According to another embodiment of the present invention, each of the first operation determination unit 131 and the third operation determination unit 133 may include a variable resistor.

(44) FIG. 6 is a circuit diagram of the first SR latch connected to the first operation determination unit 131 according to another embodiment of the present invention.

(45) As shown in FIG. 6, the first operation determination unit 131 may include a variable resistor. The variable resistor may determine a power input of the first SR latch 121 according to a resistance value.

(46) According to this embodiment, the present invention adjusts a gain of the time amplifier 100 by adjusting a resistance value of the variable resistor.

(47) As mentioned above, the operation determination units 131 and 133 are connected to the power input terminal of the SR latches 121 and 122 in the time amplifier 100 and a gain of the time amplifier 100 is adjusted by adjusting the power of the SR latches 121 and 122 through the operation determination units 131 and 133.

(48) According to an embodiment of the present invention, the operation determination unit may include a second operation determination unit 132 connected to the power output terminal of the SR latch. For example, referring to FIG. 2, the first SR latch operation determination unit may include a second operation determination unit 132 connected to the power output terminal of the first SR latch 121. Additionally, the second SR latch operation determination unit may include a fourth operation determination unit 134 connected to the power output terminal of the second SR latch 122.

(49) According to an embodiment of the present invention, each of the second operation determination unit 132 and the fourth operation determination unit 134 may include a current mirror.

(50) For example, as shown in FIGS. 2 and 4, each of the second operation determination unit 132 and the fourth operation determination unit 134 may include a current mirror and the current mirror determines a power output of the SR latches 121 and 122 according to a bias voltage V.sub.foot applied to a gate.

(51) According to this embodiment, the present invention adjusts an input range of the time amplifier 100 by adjusting the bias voltage V.sub.foot of the current mirror.

(52) Here, an available input range of a time amplifier represents a range in which the time amplifier maintains a gain uniformly. An input value (i.e., a time difference between two input signals) and an output value (i.e., a time different between two output signals) of the time amplifier may maintain linearity within a corresponding input range. However, with respect to an input value beyond the corresponding input range, a gain of the time amplifier is changed so that an output value for the input value has non-linearity.

(53) According to this embodiment, the present invention may adjust an input value range, in which the linearity of an output value for an input value of the time amplifier 100 is secured, by adjusting the bias voltage V.sub.foot of the current mirror. As a result, an available input range of the time amplifier 100 may be adjusted. That is, an available input range of the time amplifier 100 may be determined by the bias voltage V.sub.foot.

(54) According to an embodiment of the present invention, as the bias voltage V.sub.foot becomes lower, the linearity of the time amplifier 100 is improved, so that an available input range may be broader. On the contrary, as the bias voltage V.sub.foot becomes higher, the linearity of the time amplifier 100 is deteriorated, so that an available input range may be narrower.

(55) According to another embodiment of the present invention, each of the second operation determination unit 132 and the fourth operation determination unit 134 includes a transistor.

(56) FIG. 7 is a circuit diagram of the first SR latch 121 connected to the second operation determination unit 132 according to another embodiment of the present invention.

(57) As shown in FIG. 7, according to another embodiment of the present invention, the second operation determination unit 132 may include a transistor. The transistor may determine a power output of the SR latch 121 according to the bias voltage V.sub.foot applied to a gate.

(58) According to this embodiment, the present invention may adjust an available input range of the time amplifier 100 by adjusting the bias voltage V.sub.foot of the transistor.

(59) According to another embodiment of the present invention, each of the second operation determination unit 132 and the fourth operation determination unit 134 may include a variable resistor.

(60) FIG. 8 is a circuit diagram of the first SR latch connected to the second operation determination unit 132 according to another embodiment of the present invention.

(61) As shown in FIG. 8, according to another embodiment of the present invention, the second operation determination unit 132 may include a variable resistor. The variable resistor may determine a power output of the SR latch 121 according to a resistance value.

(62) According to this embodiment, the present invention may adjust an available input range of the time amplifier 100 by adjusting a resistance value of the variable resistor.

(63) As mentioned above, the operation determination units 132 and 134 are connected to the power output terminal of the SR latches 121 and 122 in the time amplifier 100 and the linearity of the time amplifier 100 and an available input range according thereto may be adjusted by adjusting the power of the SR latches 121 and 122 through the operation determination units 132 and 134.

(64) FIG. 9 is a circuit diagram of the time amplifier 100 according to another embodiment of the present invention.

(65) As shown in FIG. 9, the time amplifier 100 may further include a gain calculation unit 151 and a first control unit 161.

(66) The gain calculation unit 151 may calculate a gain of the time amplifier 100. The first control unit 161 may control operation determination units (i.e., the first operation determination unit 131 and the third operation determination unit 133) connected to the power input terminal of the SR latches 121 and 122 to that the calculated gain reaches a predetermined target gain.

(67) According to an embodiment of the present invention, the gain calculation unit 151 may detect a time difference T.sub.IN between two input signals IN1 and IN2 of the time amplifier 100 and a time difference T.sub.OUT between two output signals OUT1 and OUT2 of the time amplifier 100. Then, the gain calculation unit 151 may calculate a gain of the time amplifier 100 by dividing the time difference T.sub.OUT between the two output signals OUT1 and OUT2 by the time difference T.sub.IN between the two input signals IN1 and IN2.

(68) According to an embodiment of the present invention, when the gain is less than a target gain, a gain of the time amplifier 100 may be increased by increasing the bias voltage V.sub.head of the operation determination units 131 and 133 connected to the power input terminal of the SR latches 121 and 122, for example, the transistor shown in FIG. 2.

(69) Additionally, when the gain is greater than a target gain, a gain of the time amplifier 100 may be decreased by decreasing the bias voltage V.sub.head of the operation determination units 131 and 133, for example, the transistor shown in FIG. 2, connected to the power input terminal of the SR latches 121 and 122.

(70) FIG. 10 is a circuit diagram of a time amplifier 100 according to another embodiment of the present invention.

(71) As shown in FIG. 10, the time amplifier 100 includes a time difference detection unit 152 and a second control unit 162.

(72) The time difference detection unit 152 may detect a time difference T.sub.IN between two input signals IN1 and IN2 of the time amplifier 100. When the time difference T.sub.IN between the two input signals N1 and IN2 is greater than a predetermined marginal time difference, the second control unit 162 may control the operation determination units (i.e., the second operation determination unit 132 and the fourth operation determination unit 134) connected to the power output terminal of the SR latches 121 and 122 so as to increase the marginal time difference.

(73) Herein, the marginal time difference represents the maximum value of an input value that secures the linearity of an output value for an input value of the time amplifier 100. When an input value of the time amplifier 100 is identical or less than the marginal time difference, it is within an available input range of the time amplifier 100 and thus is amplified by a predetermined gain. However, when the input value of the time amplifier 100 becomes greater than marginal time difference, it is beyond the available input range of the time amplifier 100 and is amplified by a gain different from the predetermined gain.

(74) According to an embodiment of the present invention, when the time difference T.sub.IN between the two input signals IN1 and IN2 is greater than the marginal time difference, the second control unit 162 may increase the available input range of the time amplifier 100 by reducing the bias voltage V.sub.foot of the operation determination unit, for example, the current mirror of FIG. 2, connected to the power output terminal of the SR latches 121 and 122.

(75) In such a way, as the available input range of the time amplifier 100 becomes broader, the marginal time difference becomes greater and when the time difference T.sub.IN between two input signals becomes less than or identical to the marginal time difference, a desired gain may be obtained.

(76) According to an embodiment of the present invention, the first control unit 161 and the second control unit 162 may be configured as one and then may be implemented with one control unit.

(77) FIG. 11 is a flowchart illustrating a time amplifier controlling method according to an embodiment of the present invention.

(78) As shown in FIG. 11, the time amplifier controlling method 200 includes calculating a gain of the time amplifier 100 in operation S210, comparing the calculated gain with a predetermined target gain in operations S221 and S222, and adjusting a power of an SR latch in the time amplifier 100 when the calculated gain is different from the target gain in operations S231 and 232.

(79) FIG. 12 is a flowchart illustrating a gain calculating process according to an embodiment of the present invention.

(80) As shown in FIG. 12, the calculating of the gain of the time amplifier 100 in operation S210 includes detecting a time difference T.sub.IN between two input signals of the time amplifier 100 and a time difference T.sub.OUT between two output signals of the time amplifier 100 in operation S211 and dividing the time difference T.sub.IN between two input signals by the time difference T.sub.OUT between two input signals in operation S212.

(81) According to an embodiment of the present invention, the adjusting of the power of the SR latch includes adjusting a bias voltage V.sub.head of a transistor connected to the power input terminal of the SR latches 121 and 122.

(82) The adjusting of the bias voltage V.sub.head of the transistor includes increasing the bias voltage V.sub.head in operation S231 when the calculated gain is less than the target gain (YES in operation S221) and decreasing the bias voltage V.sub.head in operation S232 when the calculated gain is greater than the target gain (YES in operation S222).

(83) According to another embodiment of the present invention, adjusting the power of the power of the SR latch includes adjusting the bias voltage V.sub.head of a current mirror connected to the power input terminal of the SR latches 121 and 122.

(84) According to another embodiment of the present invention, adjusting the power of the power of the SR latch includes adjusting a resistance value of a variable resistor connected to the power input terminal of the SR latches 121 and 122.

(85) FIG. 13 is a flowchart illustrating a time amplifier controlling method according to another embodiment of the present invention.

(86) As shown in FIG. 13, the time amplifier controlling method 300 includes detecting a time difference T.sub.IN between the two input signals IN1 and IN2 of the time amplifier 100 in operation S310, comparing the time difference T.sub.IN between the two input signals IN1 and IN2 with a predetermined marginal time difference in operation 5320, and adjusting a power of the SR latches 121 and 122 in the time amplifier 100 in operation 5330 when the time difference T.sub.IN between the two input signals IN1 and IN2 is greater than the predetermined marginal time difference (YES in operation S320).

(87) According to an embodiment of the present invention, the adjusting of the power of the SR latch includes adjusting the bias voltage V.sub.foot of a current mirror connected to the power output terminal of the SR latches 121 and 122.

(88) The adjusting of the bias voltage V.sub.foot of the current mirror comprises decreasing the bias voltage V.sub.foot in operation 5330 when the time difference T.sub.IN between the two input signals is greater than the marginal time difference.

(89) According to another embodiment of the present invention, the adjusting of the SR latch includes adjusting the bias voltage V.sub.foot of a transistor connected to the power output terminal of the SR larches 121 and 122.

(90) According to another embodiment, the adjusting of the power of the SR latch includes adjusting a resistance value of a variable resistor connected to the power output terminal of the SR latches 121 and 122.

(91) The time amplifier controlling method according to the above-mentioned embodiments of the present invention may be implemented as a program executed in a computer and stored in a computer readable recording medium. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices.

(92) As mentioned above, a time amplifier adjusting a gain or an input rage thereof by adjusting a power provided to an SR latch in the time amplifier and a method of controlling the same are described.

(93) According to an embodiment of the present invention, a gain or an input range of a time amplifier may be adjusted if necessary and a gain and an input range of a time amplifier may be adjusted separately. Therefore, the excellent performance of the time amplifier may be realized.

(94) According to an embodiment of the present invention, a gain and an input range of a time amplifier may be adjusted.

(95) According to an embodiment of the present invention, a gain and an input range of a time amplifier may be adjusted separately.

(96) The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.