Electric circuit of a generator of oscillations

Abstract

The invention relates to an electric circuit of a generator of oscillations, comprising an enhancement-mode field transistor T1, inductance L1 and resistance R1 connected to the source or the drain of the transistor T1, characterized in that the inductance L1 is connected directly between the gate and the drain of the transistor T1 or to an electric circuit of a generator of oscillations, comprising an depletion-mode field transistor T1, inductance L1 and resistance R1 connected with its one end to the source of the transistor T1, characterized in that the inductance L1 is connected directly between the gate of the transistor T1 and the other end of the resistance R1.

Claims

1. An electric circuit of a generator of oscillations comprising: a single n-channel enhancement-mode field transistor (T1); exactly one inductance (L1), which is connected directly between a gate of the transistor (T1) and a drain of the transistor (T1); a resistance (R1) connected directly between a source of the transistor (T1) and a ground or connected directly between a supply voltage and the drain of the transistor (T1).

2. The circuit according to claim 1, characterized in that it additionally comprises a first capacity (C1) connected in parallel to the resistance (R1).

3. The circuit according to claim 2, characterized in that it comprises exactly one first capacity (C1).

4. The circuit according to claim 1 characterized in that it additionally comprises a second capacity (C2) connected in parallel to the inductance (L1).

5. The circuit according to claim 4, characterized in that it comprises exactly one second capacity (C2).

6. The circuit according to claim 1, characterized in that it comprises exactly one resistance (R1).

7. An electric circuit of a generator of oscillations comprising: a single p-channel enhancement-mode field transistor (T1); exactly one inductance (L1), which is connected directly between a gate of the transistor (T1) and a drain of the transistor (T1); a resistance (R1) connected directly between the source of the transistor (T1) and a supply voltage or connected between the drain of the transistor (T1) and a ground.

8. The circuit according to claim 7 further comprising a first capacity (C1) connected in parallel to the resistance (R1).

9. The circuit according to claim 8 wherein the circuit comprises exactly one first capacity (C1).

10. The circuit according to claim 7 further comprising a second capacity (C2) connected in parallel to the inductance (L1).

11. The circuit according to claim 10 wherein the circuit comprises exactly one second capacity (C2).

12. The circuit according to claim 7 wherein the circuit comprises exactly one resistance (R1).

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) Preferred embodiments of the present invention are presented in a more detailed way with reference to the attached drawings, in which:

(2) FIGS. 1, 2 and 3 (prior art)show known realizations of stabilized operating point circuits, on the basis of which the present invention has been made by adding an inductance;

(3) FIGS. 4, 5 and 6illustrate the essence of the present invention, i.e. circuits of FIG. 1-3 with an inductance added;

(4) FIG. 7shows the scheme of FIG. 4 with a first and second capacities added; in a similar manner a first and/or second capacity may be added to circuits shown in FIGS. 5-6;

(5) FIG. 8shows the final possible schemes of the inventive circuits depending on the type of the transistor T1 used;

(6) FIG. 9shows an example inventive circuit used for simulations made in the LTSPICE software; and

(7) FIG. 10shows the results of the LTSPICE software simulation (voltage as a function of time) made for the circuit shown in FIG. 8, wherein in the vertical axis there is the value of the Out signal in volts and on the horizontal axis there is the time in microseconds.

DETAILED DESCRIPTION AND EMBODIMENTS

(8) As mentioned above, the potential instability emerging in the circuits of FIGS. 1-3 is used in the present invention to obtain oscillations by purposefully introducing a delay by properly adding an inductance.

(9) The inductance is connected either between the gate and the drain as show in FIG. 4 and FIG. 5 for an enhancement-mode transistor or between the gate and the pole of a supply for a depletion-mode transistor, as show in FIG. 6.

(10) It is possible to add an additional parallel first capacity C1 to the resistance R1 and/or an additional parallel second capacity C2 to the inductance L1, as shown by way of example in FIG. 7, but they are not necessary for generating oscillations. The second capacity C2 makes oscillations more sinusoidal but also makes oscillations more difficult to evokebecause when the second capacity C2 is presentstarting of oscillation takes more time. Therefore the basic structures of the inventive circuit are those in FIGS. 4, 5 and 6.

(11) Depending on the type of the transistor used, the final possible schemes of inventive circuits are shown in FIG. 8.

(12) For generation of oscillations a circuit comprising exactly one transistor T1, exactly one inductance L1 and exactly one resistance R1 is sufficient.

(13) The generated signal can be fed/taken from the point marked as RefV in the figures or from the gate of the transistor T1. FIG. 9 shows an example inventive circuit used for simulations made in the LTSPICE software. The result of the simulation (voltage as a function of time) is shown in FIG. 10, in which in the vertical axis there is the value of the Out signal in volts and on the horizontal axis there is the time in microseconds.