PACKAGE STRUCTURE, CHIP STRUCTURE AND FABRICATION METHOD THEREOF

Abstract

A chip structure is provided, which includes: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer, thereby effectively reducing stresses.

Claims

1. A chip structure, comprising: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads, wherein the first copper layer has a wide bottom and a narrow top; a nickel layer formed on the first copper layer; a second copper layer formed on the nickel layer; and a tin layer formed on the second copper layer.

2. The structure of claim 1, wherein the substrate is an active chip, a passive chip or an interposer.

3. (canceled)

4. The structure of claim 1, further comprising a UBM (Under Bump Metallurgy) layer formed between each of the conductive pads and the first copper layer.

5. The structure of claim 1, further comprising a Cu.sub.6Sn.sub.5 layer formed between the second copper layer and the tin layer.

6. A method for fabricating a chip structure, comprising the steps of: providing a substrate having a plurality of conductive pads formed on a surface thereof and forming a resist layer on the substrate, wherein the resist layer has a plurality of openings formed corresponding in position to the conductive pads, respectively; sequentially forming a first copper layer, a nickel layer, a second copper layer and a tin layer in each of the openings of the resist layer; and removing the resist layer.

7. The method of claim 6, wherein the conductive pads are exposed from the openings of the resist layer, respectively, and the first copper layer is formed on each of the conductive pads.

8. The method of claim 6, wherein the substrate is an active chip, a passive chip or an interposer.

9. The method of claim 6, wherein each of the openings has a wide bottom and a narrow top so as to cause the first copper layer formed in the opening to have a wide bottom and a narrow top.

10. The method of claim 6, before forming the resist layer, further comprising forming a UBM layer on the surface of the substrate, thereby allowing the UBM layer to be sandwiched between the first copper layer and the conductive pads.

11. The method of claim 10, after removing the resist layer, further comprising removing the UBM layer under the resist layer.

12. The method of claim 6, further comprising forming a Cu.sub.6Sn.sub.5 layer between the second copper layer and the tin layer.

13. A package structure, comprising: a carrier having a plurality of conductive posts formed on a surface thereof; and a chip structure, comprising: a substrate having a plurality of conductive pads formed on a surface thereof; a first copper layer formed on each of the conductive pads; a first nickel layer formed on the first copper layer; a second copper layer formed on the first nickel layer; and a first tin layer formed on the second copper layer, wherein the chip structure is disposed on the conductive posts through the first tin layer.

14. The structure of claim 13, wherein the substrate is an active chip, a passive chip or an interposer.

15. The structure of claim 13, wherein the first copper layer has a wide bottom and a narrow top.

16. The structure of claim 13, further comprising a UBM layer formed between each of the conductive pads and the first copper layer.

17. The structure of claim 13, further comprising a Cu.sub.6Sn.sub.5 layer formed between the second copper layer and the first tin layer.

18. The structure of claim 13, wherein each of the conductive posts comprises a third copper layer, a second nickel layer and a second tin layer sequentially formed on the surface of the carrier.

19. The structure of claim 18, further comprising a Ni.sub.3Sn.sub.4 layer formed between the second nickel layer and the second tin layer.

20. The structure of claim 13, wherein each of the conductive posts comprises a third copper layer, a second nickel layer, a fourth copper layer and a second tin layer sequentially formed on the surface of the carrier.

21. The structure of claim 20, further comprising a Cu.sub.6Sn.sub.5 layer formed between the fourth copper layer and the second tin layer.

22. The structure of claim 13, wherein the carrier is an active chip, a passive chip, an interposer, a packing substrate or a circuit board.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1A is a schematic cross-sectional view of a conventional package structure having a silicon interposer;

[0026] FIG. 1B is a schematic cross-sectional view of a bump interconnection structure between the semiconductor chip and the silicon interposer of a conventional package structure;

[0027] FIGS. 2A to 2D are schematic cross-sectional views showing a method for fabricating a chip structure according to the present invention; and

[0028] FIGS. 3A and 3B are schematic cross-sectional views showing different embodiments of a package structure of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0029] The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.

[0030] It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms in the present specification are merely for illustrative purposes and should not be construed to limit the scope of the present invention.

[0031] FIGS. 2A to 2D are schematic cross-sectional views showing a method for fabricating a chip structure according to the present invention.

[0032] Referring to FIG. 2A, a substrate 20 having a plurality of conductive pads 21 formed on a surface thereof is provided, and a UBM layer (Under Bump Metallurgy) 22 is formed on the surface of the substrate 20. A resist layer 23 is formed on the UBM layer 22, and a plurality of openings 230 are formed in the resist layer 23 corresponding in position to the conductive pads 21, respectively. The substrate 20 is an active chip, a passive chip or an interposer. A portion of the openings 230 of the resist layer 23 have a wide bottom and a narrow top. In another embodiment, the UBM layer 22 is omitted and the resist layer 23 is directly formed on the substrate 20, and the conductive pads 21 are exposed from the openings 230 of the resist layer 23.

[0033] Referring to FIG. 2B, a first copper layer 24, a nickel layer 25, a second copper layer 26 and a tin layer 27 are sequentially formed in each of the openings 230 of the resist layer 23. For each of the openings 230 having a wide bottom and a narrow top, the first copper layer 24 formed in the opening 230 also has a wide bottom and a narrow top. In the case the resist layer 23 is directly formed on the substrate 20 and the conductive pads 21 are exposed from the openings 230 of the resist layer 23, the first copper layer 24 is formed on each of the conductive pads 21.

[0034] Referring to FIG. 2C, the resist layer 23 is removed.

[0035] Referring to FIG. 2D, the UBM layer 22 under the resist layer 23 is removed. If needed, a reflow process can be performed. As such, a chip structure 2 is obtained.

[0036] In another embodiment, a patterned UBM layer 22 is formed before formation of the resist layer 23. As such, the process of removing the UBM layer 22 under the resist layer 23 as described in FIG. 2D is dispensed with.

[0037] Further, a Cu.sub.6Sn.sub.5 layer (not shown) can be formed between the second copper layer 26 and the tin layer 27.

[0038] The present invention further provides a chip structure, which has: a substrate 20 having a plurality of conductive pads 21 formed on a surface thereof; a first copper layer 24 formed on each of the conductive pads 21; a nickel layer 25 formed on the first copper layer 24; a second copper layer 26 formed on the nickel layer 25; and a tin layer 27 formed on the second copper layer 26.

[0039] In the above-described chip structure, the substrate 20 can be an active chip, a passive chip or an interposer. The first copper layer 24 can have a wide bottom and a narrow top.

[0040] The above-described chip structure can further have a UBM layer 22 formed between each of the conductive pads 21 and the first copper layer 24. The above-described chip structure can further have a Cu.sub.6Sn.sub.5 layer (not shown) formed between the second copper layer 26 and the tin layer 27.

[0041] FIGS. 3A and 3B are schematic cross-sectional views showing different embodiments of a package structure of the present invention. Retelling to FIGS. 3A and 3B, a carrier 40 having a plurality of conductive posts 41 formed on a surface thereof is provided, and a chip structure 3 is disposed on the conductive posts 41 of the carrier 40. In particular, retelling to FIG. 3A, a chip structure 3 having a plurality of bumps having a cylindrical shape as in FIG. 2D is disposed on the conductive posts 41 of the carrier 40, and retelling to FIG. 3B, a chip structure 3 having a plurality of bumps having a wide bottom and a narrow top as in FIG. 2D is disposed on the conductive posts 41 of the carrier 40. The chip structure 3 has: a substrate 30 having a plurality of conductive pads 31 formed on a surface thereof; a first copper layer 32 formed on each of the conductive pads 31; a first nickel layer 33 formed on the first copper layer 32; a second copper layer 34 formed on the first nickel layer 33; and a first tin layer 35 formed on the second copper layer 34. The chip structure 3 is disposed on the conductive posts 41 of the carrier 40 through the first tin layer 35.

[0042] The substrate 30 can be an active chip, a passive chip or an interposer. The first copper layer 32 can have a wide bottom and a narrow top. Further, a UBM layer (not shown) can be formed between each of the conductive pads 31 and the first copper layer 32.

[0043] The package structure can further have a Cu.sub.6Sn.sub.5 layer 36 formed between the second copper layer 34 and the first tin layer 35. Each of the conductive posts 41 can have a third copper layer 411, a second nickel layer 412 and a second tin layer 413 sequentially formed on the surface of the carrier 40. Further, a Ni.sub.3Sn.sub.4 layer can be formed between the second nickel layer 412 and the second tin layer 413.

[0044] Alternatively, each of the conductive posts 41 can have a third copper layer, a second nickel layer, a fourth copper layer and a second tin layer (not shown) sequentially formed on the surface of the carrier 40. Further, a Cu.sub.6Sn.sub.5 layer (not shown) can be formed between the fourth copper layer and the second tin layer. The carrier 40 can be an active chip, a passive chip, an interposer, a packaging substrate or a circuit board.

[0045] Compared with the conventional Ni.sub.3Sn.sub.4 layers formed at upper and lower sides of a tin layer, a Cu.sub.6Sn.sub.5 layer is formed at at least one side of the tin layer in the present invention. Since Cu.sub.6Sn.sub.5 is softer and lower in rigidity than Ni.sub.3Sn.sub.4, stresses can be absorbed by the Cu.sub.6Sn.sub.5 layer, thereby improving the product yield. Further, the copper layer close to each of the conductive pads can have a wide bottom and a narrow top so as to strengthen its bonding with the conductive pad or the UBM layer and reduce stresses.

[0046] The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.