NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET)

Abstract

A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

Claims

1. A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprising: a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer a floating gate wrapping around a segment of the hetero-junction structure disposed between a source electrode and a drain electrode disposed on top of the hetero-junction structure; and a gate electrode wrapping around the floating gate for controlling a current flow between said source and drain electrodes in said 2DEG layer.

2. The HFET GaN semiconductor power device of claim 1 wherein: the first semiconductor layer comprising GaN interfacing the second semiconductor layer comprising Aluminum gallium nitride (AlGaN).

3. The HFET GaN semiconductor power device of claim 1 wherein: the floating gate having a built-in negative charge.

4. The HFET GaN semiconductor power device of claim 1 wherein: the HFET gallium nitride (GaN) semiconductor power device is supported on a sapphire substrate for supporting the hetero-junction structure thereon.

5. The HFET GaN semiconductor power device of claim 1 wherein: the floating gate having a negatively charged potential to shift the pinch off voltage of the 2DEG layer from a negative pinch off voltage to a positive pinch off voltage equal to or greater than three volts (3.0V).

6. The HFET GaN semiconductor power device of claim 1 wherein: the source electrode having an extended field plate extending from the source electrode and covering over the gate electrode.

7. The HFET GaN semiconductor power device of claim 1 wherein: the source electrode further having an extended field plate extending from the source electrode and covering over the gate electrode wherein the field plate is insulated from the gate electrode with a thick insulation layer.

8. A method of forming a heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprising: forming a hetero-junction structure from a first semiconductor layer interfacing a second semiconductor layer having different band gaps to make a two dimensional gas (2DEG) at the hetero-junction; forming a source electrode and drain electrode on opposite ends of the 2DEG; forming a floating gate wrapping around a segment of the hetero-junction structure between the source electrode and the drain electrode on top of the hetero-junction structure; and forming a gate electrode wrapping around the floating gate for controlling a current flow between said source and drain electrodes in said 2DEG layer.

9. The method of claim 8 wherein: the step of forming the hetero-junction structure further comprises a step of forming the first semiconductor layer comprising GaN interfacing the second semiconductor layer comprising Aluminum gallium nitride (AlGaN).

10. The method of claim 8 wherein: the step of charging the gate insulation layer to deplete the 2DEG further comprises a step of forming the gate insulation layer with a built-in negative charge.

11. The method of claim 8 further comprising: forming the HFET gallium nitride (GaN) semiconductor power device on a sapphire substrate for supporting the hetero-junction structure thereon.

12. The method of claim 8 further comprising: forming a gate insulation layer between the gate electrode and the hetero-junction structure and charging the gate insulation layer to deplete the 2DEG for operating the HFET semiconductor device in a normally off condition.

13. The method of claim 12 wherein: the step of charging the gate insulation layer to deplete the 2DEG further comprises a step of writing negative charges into said gate by insulation layer by applying a similar process of writing charges to a floating gate of a flash memory.

14. The method of claim 12 wherein: the process of forming the gate insulation layer further comprises a step of forming the gate insulation layer with the negatively charged potential to shift the pinch off voltage of the 2DEG layer from a negative pinch off voltage to a positive pinch off voltage equal to or greater than three volts (3.0V).

15. The method of claim 8 wherein: the step of forming the source electrode further includes a step of forming the source electrode with an extended field plate extending from the source electrode and covering over the gate electrode.

16. The method of claim 8 wherein: the step of forming the source electrode further includes a step of forming an extended field plate extending from the source electrode and covering over the gate electrode wherein the field plate is insulated from the gate electrode with a thick insulation layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is cross sectional view to show a conventional normally-on GaN-based HFET power device.

[0017] FIG. 2 is a cross sectional view of a HFET power device of this invention with negative charged floating gate to deplete the channel for operating the transistor as a normally-off device.

[0018] FIG. 3 is a cross sectional view of a HFET power device of this invention with negative charged gate oxide layer to deplete the channel for operating the transistor as a normally-off device.

[0019] FIG. 4 is a cross sectional perspective view of a multiple-channel HFET power device of this invention with negative charged floating gate configured as wrap-around floating gate to deplete the channel for operating the transistor as a normally-off device.

[0020] FIG. 5 is a top view of the HFET power device of FIG. 4.

[0021] FIGS. 6 and 7 are cross sectional perspective views of alternative embodiments of HFET power devices of this invention similar to that of FIG. 4.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Referring to FIG. 2 for a cross sectional view of a heterostructure field effect transistor (HFET) semiconductor power device 100 of this invention. The HFET semiconductor power device 100 comprises an AlGaN layer 120 epitaxial grown on top of gallium nitride (GaN) layer 110 thus forming a AlGaN/GaN hetero-junction with a two-dimensional electron gas (2DEG) 115 located at the interface. The AlGaN/GaN hetero-junction structure is supported on a sapphire substrate 105. A source electrode 130 and a drain 140 are disposed on two opposite sides of a gate electrode 150 to control the current flow through the 2DEG layer 115. The gate electrode 150 is insulated from the N-doped AlGaN layer 120 with a thicker gate oxide layer 155. In order to configure the HFET power device as a normally off device, a floating gate 160 is formed beneath at least a portion of the gate oxide layer 155. The floating gate 160 is insulated from the AlGaN layer 120 with a thin oxide layer 145, and from the gate electrode 150 by gate oxide 155.

[0023] The floating gate 160 is negatively charged and is configured to shift the pinch off voltage from a negative pinch off voltage to a positive pinch off voltage. For example, the pinch off voltage Vp was originally 4.0 volts without the negatively charged floating gate, is now shitted to a pinch off voltage of +3 volts with the negatively charged floating gate 160. Without an external applied voltage to the gate electrode 150, the floating gate 160 automatically pinches off the 2DEG 115. The gate electrode 150 overlaps the negatively charged floating gate 160 and is insulated from it with a thick oxide layer 155. The gate electrode 150 is applied a voltage to control the electric field. The function of the gate electrode 150 is therefore not to invert the channel. The function of the gate electrode 150 is to cancel the negative charges on the floating gate 160, which would then allow the 2DEG 115 to form uninterrupted between source 130 and drain 140 and thus turn on the device. The negative charges may be injected, e.g., written to the floating gate 160 in a same manner as charges are written to flash memory devices.

[0024] Referring to FIG. 3 for a cross sectional view of another heterostructure field effect transistor (HFET) semiconductor power device 200 of this invention. The HFET semiconductor power device 200 has a similar AlGaN/GaN hetero-junction structure with a two-dimensional electron gas (2DEG) layer 215 formed at an interface layer between a gallium nitride (GaN) layer 210 and AlGaN layer 220. The AlGaN/GaN hetero-junction structure is supported on a sapphire substrate 205. A source electrode 230 and a drain 240 are disposed on two opposite sides of a gate electrode 250 to control the current flow through the 2DEG layer 215. The source electrode 230 is formed with an extended field plate 230-FP that extends and covers over the gate electrode 250 to reduce the gate oxide peak field near the drain electrode 240. The extended field plate 230-FP is insulated from the gate electrode 250 by a thick oxide 235. The gate electrode 250 is insulated from the N-doped AlGaN layer 220 with a gate oxide layer 255. In order to configure the HFET power device as a normally off device, fixed negative charges are stored, e.g., in the same manner charges are stored in flash memory, in the gate oxide layer 255 by fluorine treatment into AlGaN layer or alternate processes during the manufacturing process. The negative charges fixed in the gate oxide layer 255 drive off the electrons in the 2DEG layer 215 thus depleting the channel. A voltage applied to the gate electrode 250 offsets the negative charges to allow the 2DEG layer 215 to return to a conduction mode. Therefore, a normally-off HFET device is achieved without degrading the electron mobility.

[0025] FIG. 4 is a partial/cross sectional perspective view to show an alternate embodiment of a HFET power device 100 of this invention. The HFET power device 100 is similar in structure as that shown in FIG. 1. The HFET power device 100 includes three AlGaN/GaN hetero-junctions between two layers of GaN layers 110-1 and 110-2 and two layers of AlGaN layers 120-1 and 120-2 respectively thus forming three channels of 2DEG layers (not specifically shown but the same as FIGS. 1-3)one 2DEG channel at each of the AlGaN/GaN hetero-junctions. The gate electrode 150 is insulated from the negative charged floating gate 160 with a thick oxide layer 155. The negatively charged floating gate 160 surrounds the hetero-junctions on both the top and on both sides of the hetero-junctions formed between the GaN and AlGaN layers. A wrap-around configuration of the negatively charged floating gate 160 would further assure complete depletion of the channels thus reliably providing a normally-off multi-channel HFET power device 100 with increased electric current flows between the source electrode 130 (not shown in FIG. 4) to the drain electrode 140, due to the multiple channels provided by the AlGaN/GaN layers 110-1, 120-1, 110-2, 120-2. FIG. 4 shows a cross section to illustrate the gate and channel structure of the HFET power device 100. FIG. 5 shows a top view of HFET power device 100 to illustrate the relative positioning of the source electrode 130, gate electrode 150 and drain electrode 140.

[0026] FIG. 6 shows a partial perspective view to show an alternative embodiment of a HFET power device 100-1. It is similar to HFET power device 100 of FIGS. 4 and 5, except that the two layers of GaN layers 110-1 and 110-2 and two layers of AlGaN layers 120-1 and 120-2 of HFET power device 100 are replaced with just a single layer of GaN 110-1 and a single layer of AlGaN 120-1. The HFET power device 100-1 has only a single 2DEG channel disposed between the AlGaN layer 120-1 and the GaN layer 110-1, but the floating gate 145 is still wrapped around to improve control of the hetero-junction.

[0027] FIG. 7 shows a partial perspective view to show an alternative embodiment of a HFET power device 100-2. It is similar to HFET power device 100 of FIGS. 5 and 6, except that the two layers of GaN layers 110-1 and 110-2 and two layers of AlGaN layers 120-1 and 120-2 of HFET power device 100 are replaced with two vertical layers of GaN layers 110-1 and 110-2 and two vertical layers of AlGaN layers 120-1 and 120-2. The vertically oriented layers mean that the hetero-junctions GaN/AlGaN are vertically oriented and thus the 2DEG channels are vertically oriented as well. In this case the wrap-around floating gate 160 may be more effective in pinching off the 2DEG channels.

[0028] According to above drawings and descriptions, the present invention discloses a method of forming a heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device. The method includes steps of forming a hetero-junction structure from a first semiconductor layer interfacing a second semiconductor layer having different band gaps to make a two dimensional gas (2DEG) at the hetero-junction; forming a source electrode and drain electrode on opposite ends of the 2DEG; forming a floating gate over a portion of the 2DEG, between the source and drain electrodes; and forming a gate electrode over the floating gate, the gate electrode being insulated from the floating gate by an insulating layer; wherein the floating gate is charged such that it depletes the 2DEG so that the device HFET semiconductor device is normally off, and wherein the gate electrode cancels the charge of the floating gate to turn the device on. In another embodiment, the step of forming a hetero-junction structure from a first semiconductor layer comprising GaN interfacing a second semiconductor layer comprising Aluminum gallium nitride (AlGaN). In another embodiment, the method further includes a step of forming the floating gate with a built-in negative charge. In another embodiment, the method further includes a step of forming the floating gate with negative charge includes a step of writing the negative charges into the floating gate in a similar manner as charge is written to flash memory. In another embodiment, the method further includes a step of wrapping the floating gate and gate electrode around the sidewalls and top of the hetero-junction structure. In another embodiment, the method further includes a step of insulating the floating gate from the hetero-junction structure with a thin insulating layer.

[0029] Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.