Advanced successive approximation register analog-to-digital converter and corresponding method

Abstract

An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

Claims

1. A successive approximation register analog-to-digital converter (SAR-ADC) comprising: a digital-to-analog converter (DAC); a successive approximation register (SAR); a comparator; and a threshold voltage determining unit (TVDU), wherein the TVDU is configured to set a threshold voltage of the comparator based on an input signal of the DAC or an output signal of the comparator, and wherein the TVDU is configured to set the threshold voltage of the comparator based on a mismatch of the DAC.

2. The SAR-ADC according to claim 1, further comprising a sample-and-hold unit configured to acquire an input signal of the SAR-ADC.

3. The SAR-ADC according to claim 2, wherein the sample-and-hold unit is configured to generate a differential signal as an output signal of the sample-and-hold unit.

4. The SAR-ADC according to claim 3, wherein the differential signal is symmetric.

5. The SAR-ADC according to claim 1, wherein the DAC is configured to provide an analog signal to the comparator based on the output signal of the SAR.

6. The SAR-ADC according to claim 1, wherein the SAR is configured to provide a digital representation of the input signal of the SAR-ADC to the DAC.

7. The SAR-ADC according to claim 1, wherein the comparator is configured to compare an input signal of the SAR-ADC and an output signal of the DAC with the threshold voltage of the comparator and to provide a result of the comparison to the SAR.

8. The SAR-ADC according to claim 1, wherein the TVDU is configured to determine the threshold voltage iteratively.

9. The SAR-ADC according to claim 1, wherein when the input signal of the DAC is configured to be directly brought to a top plate of the DAC, and the TVDU is configured to set the threshold voltage of the comparator to zero or to an offset of the comparator caused by mismatch.

10. The SAR-ADC according to claim 1, wherein the TVDU is configured to set the threshold voltage of the comparator based on a mismatch of a most significant bit of the DAC.

11. The SAR-ADC according to claim 1 wherein the TVDU is configured to set the threshold voltage of the comparator based on a mismatch of one bit less than a most significant bit of the DAC.

12. The SAR-ADC according to claim 11, wherein the TVDU is configured to increase or decrease the threshold voltage by an amount based on the mismatch of the lowest bit of the previous step of the DAC.

13. A method comprising setting a threshold voltage of a comparator of a successive approximation register analog-to-digital converter (SAR-ADC) based on an input signal of a digital-to-analog converter (DAC) of the SAR-ADC or an output signal of the comparator, wherein setting the threshold voltage of the comparator comprises setting the threshold voltage of the comparator based on a mismatch of the DAC.

14. The method according to claim 13, wherein setting the threshold voltage comprises determining the threshold voltage iteratively.

15. The method according to claim 13, further comprising setting the threshold voltage of the comparator to: zero; an offset of the comparator caused by mismatch; an amount based on a mismatch of a most significant bit of the DAC; an amount based on a mismatch of one bit less than the most significant bit of the DAC or an amount based on a mismatch of a lowest bit of the previous step of the DAC.

16. The method of claim 13, wherein setting the threshold voltage comprises setting the threshold voltage based on a mismatch of a most significant bit of the DAC.

17. The method of claim 13, wherein setting the threshold voltage comprises setting the threshold voltage based on a mismatch of one bit less than a most significant bit of the DAC.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

(2) Embodiments of the disclosure are now further explained with respect to the drawings by way of example only, and not for limitation.

(3) FIG. 1 shows a successive approximation register analog-to-digital converter, according to an example.

(4) FIG. 2 shows a differential (N+1)-bit successive approximation register analog-to-digital converter without digital-to-analog converter mismatch compensation, according to an example.

(5) FIG. 3 shows top plate voltages of the digital-to-analog converter in an ideal case (dotted line) and with mismatch (solid line), according to an example.

(6) FIG. 4 shows the differential N-bit successive approximation register analog-to-digital converter of FIG. 2 with an additional signal-dependent comparator offset, according to an example.

(7) FIG. 5A shows an improvement of the effective number of bits, according to an example.

(8) FIG. 5B shows an improvement of the spurious-free dynamic range, according to an example.

(9) FIG. 6 shows a reduction of the number of missing codes, according to an example.

(10) FIG. 7 shows a flow chart of a method for compensating a mismatch of a digital-to-analog converter of a successive approximation register analog-to-digital converter, according to an example.

(11) All the figures are schematic, not necessarily to scale, and generally only show parts used to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

(12) Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

(13) With respect to FIG. 1, a block diagram of an embodiment of an advanced successive approximation register analog-to-digital converter (SAR-ADC) 10 is shown.

(14) According to FIG. 1, the SAR-ADC 10 comprises a digital-to-analog converter 11, a successive approximation register 12, a comparator 13, and a threshold voltage determining unit 14. In this context, the threshold voltage determining unit 14 is configured to dynamically determine the threshold voltage of the comparator 13 on the basis of the input signal of the digital-to-analog converter 11 or the output signal of the comparator 13.

(15) In some embodiments, the threshold voltage determining unit 14 firstly determines the threshold voltage based on the output signal, such as the previous output signal of the comparator 13 and then increases or decreases the threshold voltage for the new comparison by an amount based on the mismatch of the digital-to-analog converter capacitors that are switched based on the output of the comparator 13.

(16) As it can further be seen from FIG. 1, the SAR-ADC 10 further comprises a sample-and-hold unit 15. In this context, the sample-and-hold unit 15 is configured to acquire the input signal of the SAR-ADC 10.

(17) In some embodiments, the digital-to-analog converter 11 is configured to provide an analog signal for the comparator 13 on the basis of the output signal of the successive approximation register 12. It is further noted that the successive approximation register 12 may be configured to provide an approximate digital representation of the input signal of the SAR-ADC 10 for the digital-to-analog converter 11.

(18) Furthermore, the comparator 13 may be configured to compare the difference between the input signal of the SAR-ADC 10 and the output signal of the digital-to-analog converter 11 with the threshold voltage of the comparator 13, and to provide the corresponding result of the comparison for the successive approximation register 12. Moreover, in some embodiments, the input signal of the comparator 13 comprises or is a differential signal.

(19) It is further noted that the dynamic determination of the threshold voltage of the comparator 13 may comprise or be an iterative determination. With respect to the iterative determination, for example in a first iteration step, the threshold voltage determining unit 14 may be configured to set the threshold voltage of the comparator 13 to zero or to an offset of the comparator 13.

(20) In addition to this or as an alternative, for example in a second iteration step, the threshold voltage determining unit 14 may be configured to increase or decrease the threshold voltage of the comparator 13 by an amount based on switching the most significant bit with a mismatch of the digital-to-analog converter 11.

(21) Further additionally or further alternatively, for example in a third iteration step, the threshold voltage determining unit 14 may be configured to increase or decrease the threshold voltage of the comparator 13 by an amount based on switching one bit less than the most significant bit with a mismatch of the digital-to-analog converter 11.

(22) In further addition to this or as a further alternative, for example in the case that further iteration steps are performed, in each further step, the threshold voltage determining unit 14 may be configured to increase or decrease the threshold of comparator 13 by an amount based on switching one bit less than the lowest bit of the previous step with a mismatch of the digital-to-analog converter 11.

(23) Now, with respect to FIG. 2, a differential (N+1)-bit successive approximation register analog-to-digital converter (SAR-ADC) 20 is shown. In this context, the input signal is sampled onto a differential digital-to-analog converter 21 of the (N+1)-bit (SAR-ADC) 20, wherein a mismatch in the digital-to-analog converter 21 is not compensated. As it can further be seen, the (N+1)-bit (SAR-ADC) 20 additionally comprises a successive approximation register 22 and a comparator 23.

(24) It is noted that each of the two differential paths of the digital-to-analog converter 21 comprises N capacitors. In this context, the capacitance value of the capacitor for the most significant bit (MSB) is 2.sup.N-1 times the capacitance value of the capacitor for the least significant bit (LSB), whereas the capacitance value is halved for each bit between the most and the least significant bit (starting from the MSB and going to the LSB).

(25) In an example, for example due to mismatch effects during the fabrication of the device, these capacitance values may slightly differ from the designed values. Hence, the output voltage of the digital-to-analog converter may differ from the intended one, which may cause errors in the analog-to-digital conversion.

(26) The mismatch in the digital-to-analog converter 21 is to be compensated especially with a signal-dependent offset in the comparator 23, which will be explained in more detail in the following. For the sake of completeness, it is primarily demonstrated what happens if the mismatch is not compensated with the aid of the threshold voltage determination or the signal-dependent offset.

(27) In this context, after the sampling operation which puts a voltage V.sub.sampled on the top plate of the digital-to-analog converter, the comparator 23 (without offset) decides on the most significant bit according to the following equation:

(28) $\begin{array}{cc}MSB=b_{N-1}=\{\begin{array}{cc}0& \mathrm{if}{V}_{\mathrm{sampled}}<0,\\ 1& \mathrm{if}{V}_{\mathrm{sampled}}>0.\end{array}& \left(1\right)\end{array}$

(29) Then, the digital-to-analog converter 21 generates a new signal on its top plate as illustrated by FIG. 3 showing top plate voltages of the digital-to-analog converter 21 for example versus the sampled input voltage V.sub.sampled in an ideal case (dotted line) and with mismatch (solid line).

(30) As it can be seen from FIG. 3, with mismatch in the digital-to-analog converter 21, an error ε.sub.0 or ε.sub.1 is made depending on the value of b.sub.N-1. The top plate voltage then becomes:
V.sub.top,1=V.sub.sample+(1−2b.sub.N-1).Math.V.sub.fb,MSB+ε(b.sub.N-1)=V.sub.top,1+ε.sub.MSB(b.sub.N-1)  (2)

(31) In this context, V.sub.fb,MSB denotes the ideal MSB feedback step, V.sub.top,1 denotes the ideal top plate value, and ε.sub.MSB(b.sub.N-1) denotes the error due to the MSB switching with mismatch of the digital-to-analog converter 21:

(32) $\begin{array}{cc}{\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right)=\{\begin{array}{cc}{\mathrm{.Math.}}_0& \mathrm{if}{b}_{N-1}=0,\\ {\mathrm{.Math.}}_1& \mathrm{if}{b}_{N-1}=1.\end{array}& \left(3\right)\end{array}$

(33) For an ideal converter, the next bit is determined by a comparator without offset:

(34) $\begin{array}{cc}{b}_{N-2}=\{\begin{array}{cc}0& \mathrm{if}{\stackrel{\_}{V}}_{top}<0,\\ 1& \mathrm{if}{\stackrel{\_}{V}}_{top}>0.\end{array}& \left(4\right)\end{array}$

(35) In the case of mismatch, this would cause errors in the analog-to-digital conversion, since the actual V.sub.top especially differs from the ideal V.sub.top.

(36) However, from equation (2) above, this comparison gives the same result as

(37) $\begin{array}{cc}{b}_{N-2}=\{\begin{array}{c}0\mathrm{if}{V}_{top}<{\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right),\\ 1\mathrm{if}{V}_{top}>{\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right).\end{array}& \left(5\right)\end{array}$

(38) So, if the comparator has a built-in offset of ε.sub.MSB(b.sub.N-1), the mismatch of the digital-to-analog converter 21 is compensated.

(39) This leads to the differential (N+1)-bit successive approximation register analog-to-digital converter 30 with an additional signal-dependent comparator offset according to the disclosure as shown in FIG. 4, which is based on FIG. 2. In this context, it is noted that FIG. 4 especially differs from FIG. 2 in that FIG. 4 additionally comprises a threshold voltage determining unit, namely the threshold voltage (Vth) selector 24.

(40) Each time the digital-to-analog converter 21 executes a feedback, the new value on the top plate can be written as:

(41) $\begin{array}{cc}{V}_{\mathrm{top},k}=V_{\mathrm{top},k-1}+\left(1-2b_{N-k}\right).Math.{\stackrel{\_}{V}}_{\mathrm{fb},\mathrm{MSB}-k+1}+\mathrm{.Math.}\left(b_{N-k}\right)& \left(6a\right)\\ ={\stackrel{\_}{V}}_{\mathrm{top},k}+{\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right)+{\mathrm{.Math.}}_{\mathrm{MSB}-1}\left(b_{N-2}\right)+\mathrm{.Math.}+{\mathrm{.Math.}}_{MSB-k+1}\left(b_{N-k}\right)& \left(6b\right)\end{array}$

(42) Hence, to obtain the correct result from the comparators, the offset Vth (threshold voltage) should be set as:

(43) $\mathrm{step}\text{0:}\mathrm{Vth}=0$$\mathrm{step}\text{1:}\mathrm{Vth}={\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right)$$\mathrm{step}\text{2:}\mathrm{Vth}={\mathrm{.Math.}}_{\mathrm{MSB}}\left(b_{N-1}\right)+{\mathrm{.Math.}}_{MSB-1}\left(b_{N-2}\right)$$\mathrm{.Math.}$$\mathrm{step}\text{k}\text{:}\mathrm{Vth}={\mathrm{.Math.}}_{\mathrm{MSB}}\left(b_{N-1}\right)+{\mathrm{.Math.}}_{MSB-1}\left(b_{N-2}\right)+\mathrm{.Math.}+{\mathrm{.Math.}}_{MSB-k+1}\left(b_{N-k}\right)$

(44) The amounts by which the threshold determining unit should increase or decrease the threshold voltage or then as follows:

(45) $\mathrm{step}\text{0:}\Delta \mathrm{Vth}=0$$\mathrm{step}\text{1:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right)$$\mathrm{step}\text{2:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB-1}\left(b_{N-2}\right)$$\mathrm{.Math.}$$\mathrm{step}\text{k}\text{:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB-k+1}\left(b_{N-k}\right)$

(46) Assuming the errors become smaller, when going deeper into the conversion, after some steps the threshold can be kept constant to continue the conversion.

(47) In some embodiments, the offset of the comparator is added as follows:

(48) $\mathrm{step}\text{0:}\Delta \mathrm{Vth}=V_{\mathrm{offset}}$$\mathrm{step}\text{1:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB}\left(b_{N-1}\right)$$\mathrm{step}\text{2:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB-1}\left(b_{N-2}\right)$$\mathrm{.Math.}$$\mathrm{step}\text{k}\text{:}\Delta \mathrm{Vth}={\mathrm{.Math.}}_{MSB-k+1}\left(b_{N-k}\right)$

(49) Furthermore, FIG. 5A and FIG. 5B show the effect on the effective number of bits (ENOB) and spurious-free dynamic range (SFDR) for a 12-bit SAR for 5000 Monte-Carlo points with random mismatch. The x-axis contains the number of comparisons with signal-dependent threshold. As described above, the remaining comparisons are done with the same threshold as the last one.

(50) Moreover, in FIG. 6, the number of missing codes is plotted. With the aid of the systems and methods of the disclosure, the number of missing codes drops to zero after enabling the signal-dependent offset for enough comparisons.

(51) It is further noted that the disclosure also provides the following potential benefits:

(52) The size of the digital-to-analog converter 21 can be made much smaller than required by the matching. This saves digital-to-analog converter area as well as power drawn from the reference. Also, settling becomes faster due to smaller RC time constants.

(53) Further In some examples, the successive approximation register analog-to-digital converter starts from a basic successive approximation register without changing the switching scheme or requiring oversampling.

(54) In some embodiments, no digital post-processing is required. Accuracy is set by the resolution of the threshold voltage tuning especially in the analog domain, which generally requires less complexity to achieve the same level of accuracy.

(55) In some examples, the offset of the comparator 23 is easily tuned within less than 1 LSB via, e.g., nonlinear capacitors made with metal oxide semiconductor capacitors (MOSCAPs). Tuning via the digital-to-analog converter 21 requires very small linear units. For instance, a 0.2 fF unit is needed on a 1 pF to generate 0.2 mV compensation with Vdd=1V. Whereas 0.2 fF can be complicated to make, 0.2 mV compensation on the offset is usually straightforward.

(56) In some embodiments, nonlinear tuning of the threshold voltage can be used to linearize the digital-to-analog converter 21.

(57) Finally, FIG. 7 shows a flow chart of an embodiment of the method for compensating a mismatch of a digital-to-analog converter of a successive approximation register analog-to-digital converter (SAR-ADC).

(58) In a first step 100, the threshold voltage of a comparator of the (SAR-ADC) is dynamically determined on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator. Then, in a second step 101 being an optional step, the dynamic determination of the threshold voltage of the comparator is defined as an iterative determination.

(59) In some embodiments, the method further comprises the steps of, for example as a first iteration step, setting the threshold voltage of the comparator to zero or to the offset of the comparator. In addition to this or as an alternative, for example as a second iteration step, the method may further comprise the step of increasing or decreasing the threshold voltage of the comparator by an amount based on switching the most significant bit with a mismatch of the digital-to-analog converter.

(60) Further additionally or further alternatively, for example as a third iteration step, the method may further comprise the step of increasing or decreasing the threshold voltage of the comparator by an amount based on switching one bit less than the most significant bit with a mismatch of the digital-to-analog converter.

(61) In further addition to this or as a further alternative, the method may further comprise the step of, for example in the case that further iteration steps are required, as each further step, increase or decrease the threshold by an amount based on switching one bit less than the lowest bit of the previous step with a mismatch of the digital-to-analog converter.

(62) While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.

(63) Although the disclosure has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired for any given or particular application.

(64) While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.