Sigma-delta analog-to-digital converter

Abstract

The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a sigma-delta ADC, and to a digital control loop comprising the same. According to the present invention, part of the filtering function required for noise-shaping is implemented in the feedback path. By suitably distributing the poles over the forward and feedback paths, stable operation can be achieved while offering low latency.

Claims

1. A sigma-delta analog-to-digital converter (ADC), comprising: a first forward path connected to an input of the sigma-delta ADC comprising a filtering stage and a quantization stage, the first forward path having a transfer function H.sub.ff; a first feedback path from an output of the first forward path to the input of the sigma-delta ADC, said first feedback path comprising a digital-to-analog converter (DAC) and a digital filter for converting the output of the first forward path, said first feedback path having a transfer function H.sub.fb; wherein the sigma-delta ADC has a stable noise transfer function NTF given by: $\mathrm{NTF}=\frac{1}{1+H_{\mathrm{ff}}{H}_{\mathrm{fb}}}=\frac{1}{1+H}$ wherein H is the loop transfer function, said NTF having at least one damped zero; wherein, if H comprises undamped poles, H.sub.ff comprising all the undamped poles of H, and wherein H.sub.fb comprises at least one damped pole associated with one of said at least one damped zero; wherein the first feedback path comprises a finite impulse response (FIR) digital filter that has an impulse response that approximates the impulse response associated with H.sub.fb, wherein the first N coefficients of the impulse response are implemented as said FIR filter, wherein N is at least equal to the time constant of the most low frequent pole of H.sub.fb; wherein the FIR digital filter is combined with the DAC for forming a finite impulse response digital-to-analog converter FIRDAC.

2. The sigma-delta ADC of claim 1, wherein H.sub.fb comprises a plurality of undamped poles.

3. The sigma-delta ADC of claim 1, further comprising a correction filter connected to the output of the first forward path.

4. The sigma-delta ADC of claim 3, said correction filter having a transfer function H.sub.cor substantially given by: $H_{\mathrm{cor}}=\frac{1+H}{H_{\mathrm{ff}}}.$

5. The sigma-delta ADC of claim 1, wherein a signal band of interest is contained within the pass-band of both H.sub.ff and H.sub.fb.

6. The sigma-delta ADC of claim 1, wherein both H.sub.ff and H.sub.fb have low-pass characteristics.

7. The sigma-delta ADC of claim 1, wherein the filtering stage comprises a passive filter.

8. The sigma-delta ADC of claim 1, wherein the filtering stage comprises a plurality of passive filters and/or a plurality of integrators.

9. The sigma-delta ADC of claim 1, comprising only a single integrator in the filtering stage.

10. A digital control loop, comprising: a second forward path connected to an input of the digital control loop comprising an amplifier for amplifying a difference between a digital input signal and a second digital signal and for converting the amplified signal into an analog output signal; and a second feedback path from an output of said second forward path to the input of the digital control loop, said second feedback path comprising the sigma-delta ADC as defined in claim 1 for converting the analog output signal into said second digital signal.

11. A digital audio amplifier comprising the digital control loop as defined in claim 10 for driving a speaker, when connected to the digital audio amplifier, in accordance with the digital input signal.

12. A method for designing a sigma-delta analog-to-digital converter (ADC) comprising a forward path connected to an input of the sigma-delta ADC comprising a filtering stage and a quantization stage, the forward path having a transfer function F.sub.ff, a feedback path from an output of the forward path to the input of the sigma-delta ADC, said feedback path comprising a digital-to-analog converter (DAC) and a digital filter for converting the output of the forward path, said feedback path having a transfer function H.sub.fb, wherein the sigma-delta ADC has a stable noise transfer function NTF given by: $\mathrm{NTF}=\frac{1}{1+H_{\mathrm{ff}}{H}_{\mathrm{fb}}}=\frac{1}{1+H}$ wherein H is the loop transfer function, said NTF having at least one damped zero, wherein, if H comprises undamped poles, H.sub.ff comprising all the undamped poles of H, and wherein H.sub.fb comprises at least one damped pole associated with one of said at least one damped zero, wherein the feedback path comprises a finite impulse response (FIR) digital filter that has an impulse response that approximates the impulse response associated with H.sub.fb, wherein the first N coefficients of the impulse response are implemented as said FIR filter, wherein N is at least equal to the time constant of the most low frequent pole of H.sub.fb, wherein the FIR digital filter is combined with the DAC for forming a finite impulse response digital-to-analog converter FIRDAC, the method comprising: defining a desired stable noise transfer function NTF of the sigma-delta ADC that comprises at least one damped zero; translating NTF into a loop transfer function H of the sigma-delta ADC according to: $H=\frac{1}{\mathrm{NTF}}-1=H_{\mathrm{ff}}{H}_{\mathrm{fb}}$ extracting poles and zeros of H; splitting H into H.sub.ff and H.sub.fb, wherein, if H comprises undamped poles, H.sub.ff comprising all said undamped poles of H, and wherein H.sub.fb comprises at least one damped pole associated with one of said at least one damped zero; approximating an impulse response associated with H.sub.fb with a finite impulse response, and implementing said finite impulse response with a finite impulse response (FIR) filter; wherein the first N coefficients of the impulse response are implemented as said FIR filter, wherein N is at least equal to the time constant of the most low frequent pole of H.sub.fb; wherein the FIR digital filter is combined with the DAC or forming a finite impulse response digital-to-analog converter FIRDAC.

13. The method according to claim 12, further comprising correcting an output of the forward path using a correction filter connected to the output of the forward path.

14. The method according to claim 13, wherein the correction filter has a transfer function H.sub.cor substantially given by: $H_{\mathrm{cor}}=\frac{1+H}{H_{\mathrm{ff}}}.$

15. A method for manufacturing a sigma-delta analog-to-digital converter (ADC), comprising: designing the ADC according to claim 12; and manufacturing the ADC according to the design of the ADC.

Description

(1) Next the invention will be described in more detail referring to the accompanying drawings, in which:

(2) FIG. 1 illustrates a known sigma-delta ADC;

(3) FIG. 2 schematically illustrates an embodiment of a sigma-delta ADC according to the present invention;

(4) FIGS. 3A-3B illustrate bode plots of a possible NTF and H according to the invention, respectively;

(5) FIG. 4 depict the coefficients of a possible FIRDAC according to the invention;

(6) FIGS. 5A-5B show power spectral density plots of a possible ADC according to the invention before and after the correction filter, respectively; and

(7) FIGS. 6A and 6B illustrate different applications of the sigma-delta ADC of the present invention.

(8) FIG. 2 schematically illustrates an embodiment of a sigma-delta ADC according to the present invention. The converter comprises an integrator 10, (or in other embodiments a filtering stage of higher or lower complexity), for integrating (processing) analog difference signals that are a difference function of the analog input signal and the analog feedback signal, a quantizer 12 responsive to the signals integrated by the integrator 10 (processed by the filtering stage) for producing the digital output signals at clock intervals defined by a clock signal, a bit stream conditioner 15 that manipulates the digital output in order to be suited input for a finite impulse response digital-to-analog converter (FIRDAC) 13, and optionally a correction filter 16 that equalizes the transfer characteristics of the ADC.

(9) Although FIG. 2 illustrates a single bit converter, multi-bit converters outputting a word stream are not excluded.

(10) FIRDACs are known as good DACs. FIRDACs are relatively simple one-bit DACs that behave like multi-bit converters. They are highly insensitive to mismatch, jitter, ISI and distortion and show high suppression of out-of-band-noise.

(11) The filtering stage and/or integrator 10 takes care of that part of the filtering that is not or cannot be done in FIRDAC 13. To achieve good noise-shaping performance, the filtering stage and/or integrator should be of at least first-order and can be implemented with active and/or passive circuits.

(12) FIRDAC 13 provides the conversion from digital-to-analog while at the same time providing a filter function specified by the finite impulse response filter (FIR-filter) coefficients. Since FIRDAC 13 features a filter function, this filter function is utilized to implement components of the required loop dynamics of the system.

(13) Quantizer 12 converts the analog signal resulting from the filtering stage and/or integrator 10 in a digital representation at clock intervals defined by a clock signal. Quantizer 12 may comprise a clocked comparator.

(14) Bit stream conditioner 15 takes the digital output of quantizer 12 and manipulates these in order to be suited for FIRDAC 13. Operations that could be performed inside this block are for example conversion to return-to-zero format in order to suppress inter-symbol-interference and negation in order to have both polarities of the output signal available.

(15) Optional correction filter 16 could compensate for the signal transfer function of the ADC, thereby creating a unity gain transfer from input to output. This can be done without adding phase shift ensuring low latency of the ADC.

(16) In sigma-delta data converter design, it is common practice to start with a desired noise-transfer function NTF and calculate the required filter function to implement this NTF. The present invention identified the filter function of the FIRDAC in the feedback path as a means to implement components of the overall required filter function. As such, the FIRDAC is related to part of NTF. According to the present invention, NTF is therefore chosen in such a way that it enables a FIRDAC as part of the filter.

(17) In the prior art, filtering in the feedback path is not deliberately used for noise shaping. Instead, the feedback path in the known sigma-delta modulator is implemented such, that it would best represent the digital output code in analog form. As such, signal transfer functions in de DAC are normally designed to be as flat as possible and any deviation thereof, which would affect the signal transfer function STF, is considered unwanted and a serious risk with respect to stability of the entire system. Contrary to the prior art, the present invention identified the filter function of the FIRDAC, or other filtering means, in the feedback path as a possibility to implement components of the noise transfer function. The stability criteria still have to be maintained in order to end up with an ADC with stable behaviour. In order to come up with an optimal design in this new work space of utilizing filtering DACs while maintaining stability criteria in sigma-delta converters, a design procedure was developed, which is described next.

(18) According to the invention, the design procedure starts with the noise transfer function NTF as is common for sigma-delta converter design. The design procedure comprises the following steps:

(19) 1. Define/design a desired (stable) noise transfer function NTF(z) with the additional criteria that it contains at least one damped zero. This criteria ensures that the resulting loop transfer function H(z) can be decomposed into components with damped response that can be implemented in a FIRDAC. Traditionally a NTF is chosen without considering the possibility of decomposition into components with damped response and therefore results in a loop transfer function which does not have transfer components that can be implemented in a FIRDAC.

(20) 2. Translate the noise transfer function into a loop transfer function H(z) using:

(21) $H=\frac{1}{\mathrm{NTF}}-1=H_{\mathrm{ff}}{H}_{\mathrm{fb}}$

(22) 3. From the transfer function H, extract the zeros and poles, corresponding to the roots of the numerator and denominator polynomial respectively.

(23) 4. Split the loop transfer function H into two parts H.sub.ff and H.sub.fb, of which the product equals H again. H.sub.ff should contain all the undamped poles of H. It may further contain zeros and damped poles as desired. H.sub.fb should contain the remaining poles and zeros and should at least comprise at least one damped pole associated with one of said at least one damped zero.

(24) 5. Translate H.sub.fb to an impulse response (using normal linear-system theory) and take the first N coefficients of this impulse response to implement as finite impulse response (FIR) filter. This approach is possible because the poles for the FIRDAC are all damped which enables that their response can be approximated with a finite number of taps. N should be chosen large enough such that the actual FIRDAC transfer captures the dominant parts of H.sub.fb (N can be approximately equal to the time constant of the most low frequent pole of H.sub.fb). The gain of the FIRDAC (the magnitude of the taps together) should be chosen such that the FIRDAC can reproduce the full range of intended input signals (with some over range to avoid overloading the sigma-delta modulation).

(25) 6. Optionally: appending the ADC with a digital filter having a transfer function H.sub.cor implementing the inverse signal transfer function given by:

(26) $H_{\mathrm{cor}}=\frac{1+H}{H_{\mathrm{ff}}}$

(27) The present invention enables FIRDACs with a large number of coefficients to be used without conflicting with the stability criteria.

(28) The implementation of the impulse response in FIR coefficients can easily result in a large number of FIR coefficients and thus resulting in a FIRDAC with a large number of coefficients. Following the design procedure above, this however will not lead to stability issues. This design procedure will result in a FIRDAC with low-pass characteristics, while still satisfying the Nyquist stability criteria in order to result a stable closed loop behaviour.

IMPLEMENTATION EXAMPLE

(29) The following relatively low (3rd) order IIR filter for the noise transfer function, of which a part is implemented in the FIR-filter, was used as starting point, see FIG. 3A:

(30) $\mathrm{NTF}\left(z\right)=\frac{\left(z-1\right).Math.\left(z^2-1.975z+0.9756\right)}{\left(z-0.6499\right).Math.\left(z^2-1.519z+0.6625\right)}$

(31) This noise transfer function is translated into a loop transfer function H, see FIG. 3B:

(32) $H\left(z\right)=\frac{0.80609.Math.\left(z^2-1.614z+0.6761\right)}{\left(z^2-1.975z+0.9756\right).Math.\left(z-1\right)}$

(33) The poles of this loop transfer function (the roots of the denominator of H) are:

(34) 1, 0.987+0.012i and 0.9870.012i

(35) In this example, the first and only real pole is implemented as an integrator in the forward path. By this the first order of the 3rd order transfer function H is implemented.

(36) In this example, the remaining two complex poles are damped poles and are implemented in the FIRDAC in the feedback path. The implementation is done by translation of the transfer function with the 2 poles and the zeros, i.e. 0.8070+0.1570i and 0.80700.1570i, to an impulse response. Only the first N coefficients of the impulse response are implemented by the FIR filter in the FIRDAC, see FIG. 4. N is chosen such that the transfer still highly resembles the desired transfer. In this example, the number of coefficients N is chosen 466. With this FIRDAC the remaining poles and zeros of the 3rd order transfer function H are implemented.

(37) The resulting output of this sigma-delta converter is illustrated using the power spectral density plot in FIG. 5A, where the output is directly taken at the output of the ADC, without compensation filter. From this figure, it can be deduced that the performance quantified by the signal-to-noise-and-distortion ratio (SNDR) equals 116 dB. In this plot a high out-of-band noise power is visible, typically for a one-bit sigma-delta modulator.

(38) FIG. 5B again shows a power spectral density plot, but now with the output taken after a correction filter which corrects the transfer to get an overall in-/output transfer of substantially unity gain. From this figure it can be deduced that the out-of-band noise (20 kHz to half the clock frequency) is highly suppressed (45 dB) compared to a single bit sigma-delta modulator. It can also be deduced that the performance quantified by the signal-to-noise-and-distortion ratio (SNDR) still equals 116 dB.

(39) The choices made in the design of this example have the following benefits:

(40) 1. The feed forward path is simple since it comprises only one integrator and one comparator, wherein the comparator output is only affected by the zero crossings of its input, which highly relaxes the requirements for the integrator. Linearity of the integrator, either the amplifier or the feedback capacitor comprising the integrator, is not important or only to a limited extent. As long as the charge balance is correct, since only zero crossing are detected by the 1 bit quantizer, neither errors nor negative effects will be seen in the system. Furthermore, a single bit comparator generates a single-bit data stream, which is perfectly linear by definition due to the fact that they have only two defined levels, unlike multi-bit quantizers, reflecting in system performance such as total harmonic distortion (THD) and SNDR.

(41) 2. The combination of the signal transfer of the ADC and the correction filter at its output is powerful. This combination features a unity gain transfer without phase shift, thus having low latency. This system further has low out-of-band noise and behaves as a multi-bit (>8 bit) converter. This is an important feature for application in closed-loop digital amplifiers.

(42) 3. High in-band resolution combined with low out-of-band noise and low latency make the ADC ideally suited for use in the feedback path of a closed loop system, such as a digital amplifier.

(43) 4. A single higher order FIRDAC with a large number of taps can be used without stability issues and thus without additional measures required to maintain stable.

(44) 5. The system with the FIRDAC enables a good jitter tolerance and a very high SNDR.

(45) FIG. 6A illustrates the sigma-delta ADC of the present invention used in a digital control loop. This loop comprises a digital control algorithm 101 that controls its output based on a digital input and a digital feedback signal, a DAC 102 that converts the signal to a form suitable for the output, and the ADC according to the present invention 103.

(46) FIG. 6B illustrates the sigma-delta ADC of the present invention used in a digitally controlled audio amplifier. The amplifier comprises a filter 201 that controls its output based on the difference between a digital input signal and a digital feedback signal, an amplifier 202 that translates the digital input to an analog output with suitable power characteristics for the load, being a speaker 203, the ADC converter according to the present invention 204, and a summing junction 205 that generates a difference between the digital input signal and the digital feedback signal.

(47) The invention has been described using embodiments thereof. It should be apparent to the skilled person that modifications to these embodiments are possible without deviating from the scope of the invention which is described by the appended claims.