Cognitive signal converter

Abstract

A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

Claims

1. A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port, the cognitive signal converter comprising an analog-to-digital converter and a cognitive network, wherein: the analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and using the process clock signal to control an operational speed of the analog-to-digital converter when quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal; and the cognitive network is adapted to: receive the digital converted signal of the analog-to-digital converter; control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source; and produce the digital output signal based on the received digital converted signal.

2. The cognitive signal converter of claim 1 wherein the cognitive network is further adapted to: predict at least part of a next sample of the digital converted signal based on the received digital converted signal and one or more characteristics of the analog signal source; and control at least one of the sample clock signal and the process clock signal based on the at least partially predicted next sample.

3. The cognitive signal converter of claim 2 wherein the analog-to-digital converter is further adapted to produce the digital converted signal based on the at least partially predicted next sample.

4. The cognitive signal converter of claim 3 wherein the analog-to-digital converter is adapted to produce the digital converted signal by comparing a next sample of the analog input signal with the at least partially predicted next sample.

5. The cognitive signal converter of claim 2 wherein the cognitive network is adapted to control the sample clock in relation to a difference between the received digital converted signal and the at least partially predicted next sample.

6. The cognitive signal converter of claim 2 wherein the cognitive network is adapted to control the process clock in relation to a difference between the received digital converted signal and the at least partially predicted next sample.

7. The cognitive signal converter of claim 2 wherein the cognitive network is further adapted to control a conversion range of the analog-to-digital converter based on the at least partially predicted next sample.

8. The cognitive signal converter of claim 1 wherein the digital output signal is equal to one of: the received digital converted signal; an adjusted version of the received digital converted signal; and a classification of the analog input signal based on the received digital converted signal.

9. The cognitive signal converter of claim 1 further comprising an image processing framer adapted to subject the digital converted signal of the analog-to-digital converter to a framing operation, and wherein the cognitive network is adapted to receive the framed digital converted signal as the digital converted signal of the analog-to-digital converter.

10. The cognitive signal converter of claim 9, wherein the cognitive network is further adapted to detect a background item of the framed digital converted signal and a moving item of the framed digital converted signal and to control the framing operation of the image processing framer based on the detection.

11. The cognitive signal converter of claim 9 wherein the analog-to-digital converter is a first analog-to-digital converter and the cognitive network is a first cognitive network, the cognitive signal converter further comprising a second analog-to-digital converter and a second cognitive network, wherein the first cognitive network is adapted to control the second cognitive network.

12. An integrated circuit comprising the cognitive signal converter of claim 1.

13. An electronic device comprising the cognitive signal converter of claim 1.

14. A method of operating an analog-to-digital converter, the method comprising: receiving an analog input signal via an analog signal input port of a cognitive signal converter comprising the analog-to-digital converter; producing a sample of a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and using the process clock signal to control an operational speed of the analog-to-digital converter when quantizing the analog input signal sample, wherein the quantizing process is operated by the process clock signal; controlling at least one of the sample clock signal and the process clock signal based on the digital converted signal and one or more characteristics of the analog signal source; and producing a digital output signal based on the digital converted signal.

15. The method of claim 14 further comprising: predicting at least part of a next sample of the digital converted signal based on the digital converted signal and one or more characteristics of the analog signal source; and controlling at least one of the sample clock signal and the process clock signal based on the at least partially predicted next sample.

16. The method of claim 15 further comprising producing a next sample of the digital converted signal based on the at least partially predicted next sample.

17. An electronic device comprising the integrated circuit of claim 12.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings, in which:

(2) FIG. 1 is a block diagram illustrating an example arrangement comprising a cognitive signal converter according to some embodiments;

(3) FIG. 2 is a block diagram illustrating an example arrangement comprising a cognitive signal converter according to some embodiments;

(4) FIG. 3 is a block diagram illustrating an example arrangement comprising a cognitive signal converter according to some embodiments;

(5) FIG. 4 is a flowchart illustrating example method steps according to some embodiments;

(6) FIG. 5 is a block diagram illustrating an example analog-to-digital converter suitable for the cognitive signal converter according to some embodiments;

(7) FIG. 6 is a schematic drawing illustrating processing of an analog input signal according to some embodiments.

DETAILED DESCRIPTION

(8) In the following, embodiments will be described where an analog input signal is input to an analog-to-digital converter and where the output of the analog-to-digital converter is used by a cognitive network to produce a digital output signal and to control the analog-to-digital converter.

(9) The cognitive network is typically aware of (or is able to learn) one or more characteristics of the analog signal source. For example, the one or more characteristics may be achieved by training (self-learning) of the cognitive network and/or based on prior knowledge regarding the analog input signal made available to the cognitive network (e.g. by manual input, by automatic input from the analog signal source, by programming, by setting of parameters or algorithms, etc.).

(10) The cognitive network may also be adapted to use the output of the analog-to-digital converter to predict (at least partially) one or more future samples of the output of the analog-to-digital converter. The prediction may be according to any suitable known or future method. When a predicted sample is referred to herein, that notation is meant to also include a partially predicted sample (e.g. a prediction of a subset of the bits the sample is composed of, such as, for example, a number of most significant bits or a number of least significant bits).

(11) The cognitive network may use the output of the analog-to-digital converter (and possibly the predicted samples) to control a sample clock and/or a process clock, both used to operate the analog-to-digital converter. The sample clock is used to control the sampling of the analog input signal and the process clock is used to control the operational speed of the analog-to-digital converter when digitizing (i.e. quantizing) an analog sample to produce a sample of the output of the analog-to-digital converter.

(12) For this purpose, a clock controller may be provided internal or external to the cognitive network. The clock controller may have a system clock signal as an input and may provide the sample clock and/or the process clock as outputs (e.g. by dividing, shifting, slicing, duplicating, etc. the system clock signal in any suitable known or future manner). The clock controller is controlled by the cognitive network based on the output of the analog-to-digital converter and one or more characteristics of the analog signal source. In some embodiments, the predicted samples may also be used to control the clock controller, for example, based on the difference (e.g. sign and/or absolute value) between ADC output samples and predicted samples or based on a matching of ADC output samples and predicted samples to a characteristic signal curve.

(13) For example, if it may be assumed (based on the output of the analog-to-digital converter and the predicted samples in the light of the characteristics of the analog signal source) that the analog input signal is in a period where precision in the analog-to-digital conversion is not of essence, the sample clock rate may be decreased such that excessive sampling is avoided and/or the process clock rate may be decreased such that unnecessarily accurate quantization is avoided.

(14) If it may be assumed that the analog input signal is in a period where precision in the analog-to-digital conversion is of essence and where the analog input signal changes very slowly, the sample clock rate may be decreased while the process clock rate may be increased.

(15) If it may be assumed that the analog input signal is in a period where precision in the analog-to-digital conversion is of essence and where the analog input signal changes rapidly, the sample clock rate and the process clock rate may be increased.

(16) Numerous other situations where various combinations of increased, decreased or unchanged rates of the sample and/or process clocks are applicable may be envisioned. When reference is made to an increase or decrease of a clock rate, clock period, or any other parameter, it may be understood as compared to a nominal value or compared to a previous value as applicable.

(17) The predicted samples may be further used to control the operation of the analog-to-digital converter. For example, the predicted samples may be fed back from the cognitive network to the analog-to-digital converter. The analog-to-digital converter may, for example, use the predicted samples as a starting point for its quantization process. The quantization process may then comprise comparing the analog sample with the predicted next sample. (In some of these embodiments, estimation of one or more of the most significant bits is not needed. Instead, those bits may be extracted directly from the predicted sample.) Typically, the analog-to-digital converter needs fewer processing cycles to come to a specific result compared to if there was no prediction available. This may lead to lower energy consumption (e.g. by lowering of the processing clock rate). Alternatively or additionally, one or more processing cycles may be used to achieve a higher precision in the quantization (e.g. by letting the analog-to-digital converter operate in a narrower range). Yet alternatively or additionally, one or more processing cycles may be used to accommodate an increased sampling clock rate.

(18) Thus, in some embodiments, the cognitive network may control the analog-to-digital converter by providing a predicted sample value, an operational range, a sample clock and a process clock. In some embodiments, only a subset of these control signals may be used. For example, only the adapted sample clock and the adapted process clock may be provided to the analog-to-digital converter in some embodiments.

(19) The cognitive network is further adapted to produce the digital output signal based on the output from the analog-to-digital converter.

(20) In some embodiments, the digital output signal is equal to the output from the analog-to-digital converter or to an adjusted version of the output from the analog-to-digital converter. For example, if the analog input signal is a quadrature amplitude modulation (QAM) signal it is known that the signal is a sinusoidal signal where the amplitude and phase belongs to a limited set of amplitudes and phases. In such cases, the cognitive network may (based on earlier samples) adjust the output based on the possible amplitudes and phases.

(21) In other embodiments, the digital output signal may comprise a characterization (or classification) of the output from the analog-to-digital converter. For example, if it is known that the analog input signal is always in one of four different states, the cognitive network may be adapted to detect the current state based on the output from the analog-to-digital converter and the digital output signal may simply comprise an indication of the detected state (2 bits in this example). In the example of the quadrature amplitude modulation (QAM) signal above, the cognitive network may be able to detect (based on the possible amplitudes and phases) the QAM symbol after a few number of samples. Then, a symbol representation (classification) may be output and no more samples are needed during the current symbol period.

(22) The cognitive network may produce the digital output signal based on partial samples of the output from the analog-to-digital converter. For example, if the cognitive network is able to determine a classification based on a part of a sample (e.g. based on a number of most significant bits), the classification may be used as the digital output signal and the analog-to-digital conversion may be terminated prematurely (e.g. by adjusting the process clock so that the rest of the sample is not processed and resetting the ADC for the next sample).

(23) In some embodiments, several analog-to-digital converters may process parallel analog input signals and input them to a single cognitive network, which produces a classification based on the combination of analog-to-digital converter outputs.

(24) As mentioned before, the analog-to-digital converter may comprise one or more successive approximation register analog-to-digital converters (SAR ADC).

(25) The SAR ADC may, for example, be formed by a plurality of parallel ADC:s, which may be individually controlled by the cognitive network. For example, when the sampling rate is low, the cognitive network may put a corresponding number of the parallel ADC:s in a low activity (or sleep) mode to save energy.

(26) The SAR ADC may, for example, be a time-interleaved ADC formed by a plurality of constituent SAR ADC:s, which may be individually controlled by the cognitive network. Any interleaving errors (e.g. time offsets) may be corrected in the cognitive network.

(27) The SAR ADC may, for example, be an ADC with redundancy formed by more ADC:s than crucially needed (e.g. to be able to perform calibration of the ADC:s during run time) controlled by the cognitive network.

(28) FIG. 1 is a schematic block diagram illustrating an example arrangement comprising a cognitive signal converter 100 according to some embodiments. The arrangement also comprises an analog signal source (SRC) 101 providing an analog input signal 141 to an analog input port of the cognitive signal converter 100 and a processor (PROC) 102 that uses the digital output signal 143 of the cognitive signal converter 100 for some purpose (e.g. further processing and/or rendering; including signal demodulatione.g. Orthogonal Frequency Division Multiplexing (OFDM) demodulation of a Wireless Local Area Network (WLAN) receiver, object tracking in a video sequence, Moving Picture Experts Group (MPEG) encoding, fingerprint recognition, touch recognition for optical touch screens, etc.).

(29) The cognitive signal converter 100 comprises an analog-to-digital converter (ADC) 110, a cognitive network (CNW) 120 and a clock controller (CLK CNTR) 130. The clock controller 130 is illustrated in FIG. 1 as external to the cognitive network 120. In other embodiments, the clock controller may be comprised in the cognitive network.

(30) As has been elaborated on above, the ADC 110 processes the analog input signal 141 based on a process clock signal 147, a sample clock signal 146 and a feedback signal 149 from the cognitive network 120 to produce a digital converted signal 145. The digital converted signal 145 may be directly output to the processor 102 according to some embodiments as illustrated by 144 in FIG. 1.

(31) The digital converted signal 145 is also input to the cognitive network 120, which may use the digital converted signal 145 and (pre-coded and/or learnt) characteristics of the signal source 101 to predict a next sample of the digital converted signal 145. As elaborated on above, the predicted sample may be fed back to the ADC 110 (via the feedback signal 149). Furthermore, the digital converted signal 145 and the characteristics of the signal source (and possibly the predicted sample) may be used by the cognitive network 120 to control (via control signal 148) the sample clock signal 146 and/or the process clock signal 147 of the clock controller 130 in relation to the system clock (CLK) 142 input to the clock controller 130.

(32) FIG. 2 is a schematic block diagram illustrating an example arrangement comprising a cognitive signal converter 200 according to some embodiments. The blocks 201, 202, 210, 220 and 230 of FIG. 2 are identical to (or at least similar to) the corresponding blocks 101, 102, 110, 120 and 130 of FIG. 1. Similarly, the signals 241, 242, 243, 245, 246, 247, 248 and 249 of FIG. 2 are identical to (or at least similar to) the corresponding signals 141, 142, 143, 145, 146, 147, 148 and 149 of FIG. 1. These blocks and signals will not be elaborated on further.

(33) The cognitive signal converter 200 also comprises a framer (FR) 250, adapted to perform an image processing framing operation on the output 245 of the ADC 210 before forwarding it to the cognitive network 220 as the framed signal 252. The framed signal 252 may be directly output to the processor 202 according to some embodiments as illustrated by 244 in FIG. 2.

(34) In this cognitive signal converter 200, the cognitive network 220 may also be adapted to control the framer 250 via control signal 251. For example, the cognitive network 220 may be adapted to detect a background item and a moving item of the framed signal 252 and control the framing operation of the image processing framer based on the detection. In some examples, the cognitive network 220 may be adapted to control the framing by indicating a position, direction and velocity of a moving item, and the framer 250 may adapt which parts of the frame it needs to convert and when based on these indications.

(35) The cognitive signal converter 200 is particularly suitable for image processing applications.

(36) FIG. 3 is a schematic block diagram illustrating an example arrangement comprising a cognitive signal converter 300 according to some embodiments. The blocks 301, 302, 310, 320, 330 and 350 of FIG. 3 are identical to (or at least similar to) the corresponding blocks 201, 202, 210, 220, 230 and 250 of FIG. 2. Similarly, the signals 341, 342, 343, 344, 345, 346, 347, 348, 349, 351 and 352 of FIG. 3 are identical to (or at least similar to) the corresponding signals 241, 242, 243, 244, 245, 246, 247, 248, 249, 251 and 252 of FIG. 2. These blocks and signals will not be elaborated on further.

(37) The cognitive converter 300 also comprises a second set of blocks(ADC) 360, framer (FR) 390, cognitive network (CNW2) 370 and clock controller (CLK CNTR) 380identical to (or at least similar to) the corresponding blocks(ADC) 310, framer (FR) 350, cognitive network (CNW1) 320 and clock controller (CLK CNTR) 330respectively.

(38) The ADC 360 processes a second part of the analog input signal 361 based on a process clock signal 367, a sample clock signal 346 and a feedback signal 369 from the second cognitive network 370 to produce a digital converted signal 365.

(39) The framer (FR) 390 is adapted to perform an image processing framing operation on the output 365 of the ADC 360 before forwarding it to the second cognitive network 370 as the framed signal 392. The framed signal 392 may be directly output to the processor 302 according to some embodiments as illustrated by 364 in FIG. 3.

(40) The framed signal 392 is input to the second cognitive network 370, which may use it and (pre-coded and/or learnt) characteristics of the signal source 301 to predict the next sample of the digital converted signal, and controls (via control signal 368) the clock controller 380. The second cognitive network 370 may also be adapted to control the framer 390 via control signal 391.

(41) In the example of FIG. 3, the sample clock 346 is the same for both of the ADC:s 310, 360 and is controlled by the first cognitive network (CNW1) 320. In other embodiments, the sample clock may differ between the ADC:s 310, 360 and may be controlled by the respective cognitive network 320, 370.

(42) The first cognitive network (CNW1) 320 may be adapted to transfer information and/or control signals to the second cognitive network (CNW2) 370 via the connection 393. Thereby, predictions, detections, and control signals (or part(s) thereof) already achieved by the first cognitive network 320 need not be duplicated by the second cognitive network 370, which typically saves energy and/or processing resources.

(43) The cognitive signal converter 300 is particularly suitable for 3D image processing applications (e.g. if the source 301 comprises a first source (SRC1) 301a which may be a first image capturing device such as a camera with high resolution and a second source (SRC2) 301b which may be a second image capturing device such as a camera with low resolution, wherein the first and second image capturing devices are located in relation to each other, e.g. at a distance corresponding to a typical distance between the eyes of a human, to collectively provide a 3D image).

(44) FIG. 4 illustrate an example method according to some embodiments. The method of FIG. 4 may, for example, be performed by any of the cognitive signal converters 100, 200, 300 or FIGS. 1, 2 and 3, respectively.

(45) The method is initiated in step 410 by setting characteristics parameters that define the analog signal source to initial values. These characteristics parameters are used by the cognitive network as elaborated on above, and may be stationary or may be dynamically changed during processing of the analog signal.

(46) Then, an analog input signal of the analog source is received via an analog signal input port of the cognitive signal converter and sampled, in step 420, by the analog-to-digital converter based on the sampling clock signal. The analog-to-digital converter digitizes (e.g. by quantization) the analog sample in step 430 to produce a sample of a digital converted signal based on the process clock signal.

(47) In optional step 440, the cognitive network predicts the next sample of the digital converted signal based on the past sample(s) and the characteristics parameters. In step 450, the cognitive network controls the sample clock signal and the process clock signal based on the past sample(s) and the characteristics parameters (and possibly the predicted next sample), and in optional step 460, it feeds back the predicted sample to the analog-to-digital converter for use in the quantization of future samples.

(48) The cognitive network also produces, in step 470, a digital output signal, which may be equal to the output from the analog-to-digital converter (possibly adjusted) or may be a classification of the current state of the analog input signal.

(49) FIG. 5 is a schematic block diagram illustrating an example analog-to-digital converter (ADC) 510 suitable for the cognitive signal converter according to some embodiments. The ADC 510 may, for example, be used as any of the ADC:s 110, 210, 310 and 360 of FIGS. 1, 2 and 3.

(50) The example ADC 510 is a successive approximation register (SAR) ADC (compare with WO 2013/123578 A1) and comprises a sample and hold unit (S&H) 511, a successive approximation register (SAR) 512, a digital-to-analog converter (DAC) 513 and a comparator (COMP) 514.

(51) The sample and hold unit 511 is adapted to sample an analog input signal 541 (compare with signals 141, 241, 341 and 361 of FIGS. 1, 2 and 3) at a sampling rate defined by the sample clock signal 546 (compare with signals 146, 246 and 346 of FIGS. 1, 2 and 3).

(52) A predicted next sample 549 may be stored in the successive approximation register 512, and at a processing rate determined by the processing clock signal 547 (compare with signals 147, 247, 347 and 367 of FIGS. 1, 2 and 3) the content of the successive approximation register 512 is converted to an analog value in the DAC 513 and compared with the sampled analog input signal in the comparator 514. Each comparison determines the value of a bit of the successive approximation register 512 and the successive approximation register 512 is updated accordingly. When the respective value of all bits has been determined the quantized sample value is output at 545.

(53) FIG. 6 is a schematic drawing illustrating processing of an analog input signal 610 according to some embodiments. The signal 610 has three different states as shown in FIG. 6; a first state where the signal amplitude is close to zero (e.g. in the time spans illustrated by 621, 622, 623), a second state where the signal amplitude has a single peaked shape (e.g. in the time span illustrated by 651), and a third state where the signal amplitude has a double peaked shape (e.g. in the time span illustrated by 652).

(54) When the signal is in the first state, it may only be important to know if the signal is about to transferred to another state and the sampling rate may be rather low. When the signal is in the second or third state, it may be crucial to have high resolution in time to determine which of the second and third state the signal is in and the sampling rate should be rather high.

(55) Thus, the cognitive network may be adapted to compare the amplitude of the ADC output with a threshold value 620 and change the sampling rate from a low value to a high value if the amplitude of the ADC output is above the threshold value 620 while the amplitude of the previous ADC output was below the threshold value 620 (i.e. it predicts that this marks a transfer to the second or third state). The cognitive network may also be adapted to change the sampling rate from the high value to the low value when it has detected the second or third state. For example, the third state may be considered detected if an amplitude dip is experienced (as illustrated in time interval 652) and the second state may be considered detected if the amplitude of the ADC output falls below the threshold value 620 without any amplitude dip being experienced(as illustrated in time interval 651). Sampling times are illustrated with x in FIG. 6.

(56) Thus, when the signal is in the first state, energy may be saved since there is less samples to process for the ADC. For example, if a time-interleaved ADC is applied, one or more of the constituent ADC:s may be put in a sleep mode and/or a processing rate may be lowered.

(57) The digital output signal of the cognitive signal converter may comprise an indication of the current state of the analog input signal.

(58) The described embodiments and their equivalents may be realized in software or hardware or a combination thereof. They may be performed by general-purpose circuits, such as digital signal processors (DSP), central processing units (CPU), co-processor units, field-programmable gate arrays (FPGA) or other programmable hardware, or by specialized circuits such as for example application-specific integrated circuits (ASIC). All such forms are contemplated to be within the scope of this disclosure.

(59) Embodiments may appear within an electronic apparatus comprising circuitry/logic or performing methods according to any of the embodiments. The electronic apparatus may, for example, be a 3D tracking camera, a touch screen detector, a fingerprint classification device, an MPEG encoder/decoder, or an OFDM receiver/decoder.

(60) Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims. For example, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. In the same manner, functional blocks that are described herein as being implemented as two or more units may be implemented as a single unit without departing from the scope of the claims.

(61) Hence, it should be understood that the details of the described embodiments are merely for illustrative purpose and by no means limiting. Instead, all variations that fall within the range of the claims are intended to be embraced therein.