Amplifier topology for envelope tracking

Abstract

An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.

Claims

1. An amplifier comprising: an input port for receiving an input signal; an envelope port for receiving an envelope signal indicative of an envelope of the input signal; an output port for delivering an amplified signal; a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor, and a drain of the second transistor is coupled to the output port; an inductive element coupled between the envelope port and the drain of the second transistor; a first biasing circuit coupled to the envelope port and configured to generate a first bias voltage dependent on the envelope signal; a summing stage coupled to the input port for receiving the input signal, coupled to the first biasing circuit for receiving the first bias voltage, coupled to a gate of the first transistor, and configured to deliver a sum of the input signal and the first bias voltage to the gate of the first transistor; a second biasing circuit coupled between the envelope port and a gate of the second transistor, and configured to generate a second bias voltage dependent on the envelope signal and to deliver the second bias voltage to the gate of the second transistor, wherein the first bias voltage is dependent on the envelope signal for a range of values of the envelope signal, and is independent of the envelope signal outside of the range of values of the envelope signal.

2. The amplifier of claim 1, wherein the range of values of the envelope signal for which the first bias voltage is dependent on the envelope signal corresponds to the envelope signal being less than a threshold, the first bias voltage being constant when the envelope signal is greater than the threshold.

3. The amplifier of claim 1, wherein the first and second bias voltages dependent on the envelope signal are each an affine function of the envelope signal.

4. The amplifier of claim 1, wherein the first bias voltage, V.sub.bias1, dependent on the envelope signal is related to the envelope signal by V.sub.bias1=S.sub.1.V.sub.env+V.sub.bias1.sub._.sub.0, and wherein the second bias voltage, V.sub.bias2, is related to the envelope signal by V.sub.bias2=S.sub.2.V.sub.env+V.sub.bias2.sub._.sub.0, where V.sub.env is the envelope signal, S.sub.1 is a first constant, V.sub.bias1.sub._.sub.0 is a first quiescent voltage, S.sub.2 is a second constant and V.sub.bias2.sub._.sub.0 is a second quiescent voltage.

5. The amplifier of claim 4, wherein the first biasing circuit comprises a first voltage divider configured to generate a first divided envelope signal S.sub.i.V.sub.env by dividing the envelope signal, and the second biasing circuit comprises a second voltage divider configured to generate a second divided envelope signal S.sub.2.V.sub.env by dividing the envelope signal.

6. The amplifier of claim 5, wherein the first voltage divider comprises a first resistive element having a variable resistance for establishing the first constant, and wherein the second voltage divider comprises a second resistive element having a variable resistance for establishing the second constant.

7. The amplifier of claim 4, wherein the first and second biasing circuits are configured to generate the first and second bias voltages by providing values for the first and second quiescent voltages and the first and second constants, such that, if the input signal is absent, a current drawn by the amplifier varies by less than 10% in response to a variation of the envelope signal across a maximum operating range of the amplifier.

8. The amplifier of claim 1, further comprising an envelope tracking stage configured to generate the envelope signal in response to the input signal.

9. The amplifier of 8, wherein the envelope tracking stage is configured to generate the envelope signal quantized to have fewer values than the envelope of the input signal.

10. A method of amplification, comprising: providing a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor and a drain of the second transistor is coupled to an output port; providing an inductive element coupled between an envelope port and the drain of the second transistor; receiving an input signal; receiving at the envelope port an envelope signal indicative of an envelope of the input signal; generating a first bias dependent on the envelope signal; delivering a sum of the first bias voltage and the input signal to a gate of the first transistor; generating a second bias voltage dependent on the envelope signal, and delivering the second bias voltage to a gate of the second transistor; and delivering an amplified signal at the output port, wherein the first bias voltage is dependent on the envelope signal for a range of values of the envelope signal, and is independent of the envelope signal outside of the range of values of the envelope signal.

11. The method of amplification of claim 10, wherein the range of values of the envelope signal for which the first bias voltage is dependent on the envelope signal corresponds to the envelope signal being less than a threshold, and wherein the first bias voltage is constant when the envelope signal is greater than the threshold.

12. The method of amplification of claim 10, wherein the first bias voltage, V.sub.bias1, dependent on the envelope signal is related to the envelope signal by V.sub.bias1=S.sub.1.V.sub.env+V.sub.bias1.sub._.sub.0, and wherein the second bias voltage, V.sub.bias2, is related to the envelope signal by V.sub.bias2=S.sub.2.V.sub.env+V.sub.bias2.sub._.sub.0, where V.sub.env is the envelope signal, S.sub.1 is a first constant, V.sub.bias1.sub._.sub.0 is a first quiescent voltage, S.sub.2 is a second constant and V.sub.bias2.sub._.sub.0 is a second quiescent voltage.

13. The method of claim 10, further comprising: calibrating at least one of a first bias voltage circuit and a second bias voltage circuit configured to provide the first and the second bias voltage, respectively, to achieve a target value of a quiescent current.

14. The method of claim 13, wherein the first bias voltage circuit or the second bias circuit is calibrated by varying a variable resistance of a voltage divider included in the first or the second bias circuit that is calibrated.

15. The method of claim 13, wherein both the first bias voltage circuit and the second bias circuit are calibrated.

16. The method of claim 15, wherein the second bias circuit is calibrated after calibrating the first bias circuit.

17. An amplifier comprising: an input port for receiving an input signal; an envelope port for receiving an envelope signal indicative of an envelope of the input signal; an output port for delivering an amplified signal; a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor, and a drain of the second transistor is coupled to the output port; an inductive element coupled between the envelope port and the drain of the second transistor; a first biasing circuit coupled to the envelope port and configured to generate a first bias voltage dependent on the envelope signal; a summing stage coupled to the input port for receiving the input signal, coupled to the first biasing circuit for receiving the first bias voltage, coupled to a gate of the first transistor, and configured to deliver a sum of the input signal and the first bias voltage to the gate of the first transistor; a second biasing circuit coupled between the envelope port and a gate of the second transistor, and configured to generate a second bias voltage dependent on the envelope signal and to deliver the second bias voltage to the gate of the second transistor, wherein the first bias voltage, V.sub.bias1, dependent on the envelope signal is related to the envelope signal by V.sub.bias1=S.sub.tV.sub.env+V.sub.bias1.sub._.sub.0 , and wherein the second bias voltage, V.sub.bias2, is related to the envelope signal by V.sub.bias2=S.sub.2.V.sub.env+V.sub.bias1.sub._.sub.0 , where V.sub.env is the envelope signal, S.sub.1 is a first constant, V.sub.bias1.sub._.sub.0 is a first quiescent voltage, S.sub.2 is a second constant and .sub.V bias1.sub._.sub.0 is a second quiescent voltage, and the first and second biasing circuits are configured to generate the first and second bias voltages by providing values for the first and second quiescent voltages and the first and second constants, such that, if the input signal is absent, a current drawn by the amplifier varies by less than 10% in response to a variation of the envelope signal across a maximum operating range of the amplifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Preferred embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

(2) FIG. 1 is a schematic diagram of a prior art amplifier;

(3) FIG. 2 is a schematic diagram of a prior art amplifier with envelope tracking;

(4) FIG. 3 illustrates the power efficiency of the prior art amplifiers;

(5) FIG. 4 is a graph of gain and output power for the prior art amplifiers;

(6) FIG. 5 is a graph of power added efficiency for the prior art amplifiers;

(7) FIG. 6 is a first embodiment of an amplifier in accordance with the present disclosure;

(8) FIG. 7 illustrates load lines for different values of the envelope signal;

(9) FIG. 8 is a graph of gain and output power as a function of input power for an amplifier with tracking bias voltages in accordance with the present disclosure;

(10) FIG. 9 is a graph of gain and output power as a function of input power without tracking bias voltages;

(11) FIG. 10 is a graph of current as a function of output power;

(12) FIG. 11 is a Smith chart illustrating input impedance;

(13) FIG. 12 is a graph of Rollet stability factor;

(14) FIG. 13 is a graph of small signal gain as a function of frequency;

(15) FIG. 14 is a flow chart of a method of amplification;

(16) FIG. 15 is a flow chart of a method of calibrating an amplifier;

(17) FIG. 16 is a second embodiment of an amplifier in accordance with the present disclosure; and

(18) FIG. 17 is a block schematic diagram of an electronic apparatus comprising an amplifier.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(19) This section commences with further description of some of the characteristics of the prior art amplifiers 10, 20 for the purpose of identifying the differences and advantages of the amplifier and method of amplification according to the present disclosure. Referring to FIG. 4, curves G.sub.1, G.sub.5 and G.sub.10 are plots of gain of the amplifier 10 of FIG. 1, as a function of input power P.sub.in of the signal source 11, for different values of the constant supply voltage V.sub.dd of, respectively 1, 5 and 10V. It can be seen that the gain is dependent on the constant supply voltage V.sub.dd, being lower for lower values of the constant supply voltage V.sub.dd, but for each value of the constant supply voltage V.sub.dd, for low values of the input power P.sub.in, up to about 0 dBm, the gain is fairly constant, and as the input power P.sub.in is increased to 25 dBm, the gain rises, and then falls again as the amplifier 10 goes into compression. When envelope tracking is used, as in the amplifier 20 of FIG. 2, the variation in gain becomes even greater, because for a high input power P.sub.in the non-constant supply voltage V.sub.env is high and the curve G.sub.10 is applicable, whilst for a low input power P.sub.in the non-constant supply voltage V.sub.env is low and the curve G.sub.1 is applicable. Therefore, the gain of the amplifier 20 of FIG. 2 can vary significantly with the voltage variation of the non-constant supply voltage V.sub.env, in effect moving between the curves G.sub.1, G.sub.10 and intermediate curves. Consequently, the use of envelope tracking can degrade linearity of the amplifier 20. Moreover the compression point of the amplifier 20 of FIG. 2 degrades, by shifting to lower levels of input power P.sub.in as the as the non-constant supply voltage V.sub.env increases.

(20) Similarly, graphs P.sub.1, P.sub.5 and P.sub.10 are plots of output power P.sub.out of the amplifier 10 of FIG. 1, as a function of input power P.sub.in of the signal source 11, for different values of the constant supply voltage V.sub.dd of, respectively 1, 5 and 10V. The output power P.sub.out is dependent on the input power P.sub.in and the constant supply voltage V.sub.dd, being lower for lower values of the constant supply voltage V.sub.dd, due to the lower gain, but for each value of the constant supply voltage V.sub.dd, for low values of the input power P.sub.in, up to about 10 dBm, the ratio of output power P.sub.out to input power P.sub.in, that is, gain, is fairly constant, but reduces as the input power P.sub.in is increased further to 25 dBm. This behaviour is illustrated alternatively in FIG. 5 which illustrates, in curves PAE.sub.1, PAE.sub.5 and PAE.sub.10, the Power Added Efficiency (PAE) of the amplifier 10 of FIG. 1 as a function of output power P.sub.out for different values of the constant supply voltage V.sub.dd of, respectively 1, 5 and 10V. When envelope tracking is used, as in the amplifier 20 of FIG. 2, the PAE can be maintained within an optimum range by increasing the non-constant supply voltage V.sub.env such that a higher peak PAE can be reached when operating at a higher power level, and decreasing the non-constant supply voltage V.sub.env such that a higher PAE can be reached when operating at a low power level.

(21) It has been found that, when using the amplifier 20 illustrated in FIG. 2, when the amplitude of the input signal changes, the input impedance of the amplifier 20 can also change due to poor isolation between the gate and drain of the transistor 12. It has also been found that, if the amplifier 20 is designed for linear and power-efficient operation at a high power level, at a low power level the amplifier 20 can be inefficient and linearity degraded by the use of the envelope tracking. For optimum linearity and PAE, the gain of the amplifier 20 should be constant at all input power levels.

(22) Referring to FIG. 6, an amplifier 100 has an input port 102 for receiving an input signal V.sub.i, an envelope port 104 for receiving an envelope signal V.sub.env indicative of an envelope of the input signal V.sub.i, and an output port 106 for delivering an amplified signal, also referred to as an output signal. The input port 102 is coupled to a signal source 11, which delivers the input signal V.sub.i, by means of an input coupling capacitor C.sub.i. The envelope port 104 is coupled to the signal source 11 by means of an envelope tracking stage 18. The envelope tracking stage 18 receives the input signal V.sub.i from the signal source 11 and generates the envelope signal V.sub.env, which it delivers to the envelope port 104. The output port 106 is coupled to a load R.sub.L by means of an output coupling capacitor C.sub.o.

(23) The amplifier 100 has a first transistor M1 and a second transistor M2. A drain d.sub.1 of the first transistor M1 is coupled to a source s.sub.2 of the second transistor M2, the first and second transistors M1, M2 being coupled in a cascode configuration, with the first transistor M1 in a common source configuration and the second transistor M2 in a common gate configuration. A gate g.sub.1 of the first transistor M1 is coupled to an output 143 of a first summing stage 140, and a drain d.sub.2 of the second transistor M2 is coupled to the output port 106. A source s.sub.1 of the first transistor M1 is coupled to a first voltage supply rail 30, which may be ground. An inductive element L is coupled between the envelope port 104 and the drain d.sub.2 of the second transistor M2, for applying the envelope signal V.sub.env to the cascode arrangement of the first and second transistors M1, M2. The first summing stage 140 has a first input 141 coupled to the input port 102 for receiving the input signal V.sub.i, a second input 142 for receiving a first bias voltage Vbias1, and the output 143 of the summing stage 140 delivers a sum of the input signal V.sub.i and the first bias voltage V.sub.bias1.

(24) A first biasing circuit 120 is coupled between the envelope port 104 and the second input 142 of the first summing stage 140, and generates the first bias voltage V.sub.bias1 dependent on the envelope signal V.sub.env. In particular, the first biasing circuit 120 may comprise a first resistive element R.sub.1 and a second resistive element R.sub.2 coupled in series between the envelope port 104 and the first voltage rail 30 thereby forming a first voltage divider providing, at a junction between the first and second resistive elements R.sub.1, R.sub.2, a first divided envelope signal S.sub.1.V.sub.env, where S.sub.1 is a first constant less than unity. A second summing stage 125 is coupled to the junction between the first and second resistive elements R.sub.1, R.sub.2 and adds a first quiescent bias voltage V.sub.bias1.sub._.sub.0 to the first divided envelope signal S.sub.1.V.sub.env thereby forming the first bias voltage V.sub.bias1 which is delivered to the second input 142 of the first summing stage 140. The second resistive element R.sub.2 has a variable resistance whose value may be selected by a calibration process as described below, but alternatively, or additionally, the first resistive element R.sub.1 may have a variable resistance.

(25) A second biasing circuit 130 is coupled between the envelope port 104 and the gate g.sub.2 of the second transistor M2, and generates a second bias voltage V.sub.bias2 dependent on the envelope signal V.sub.env, and provides the second bias voltage V.sub.bias2 to the gate g.sub.2 of the second transistor M2. In particular, the second biasing circuit 130 may comprise a third resistive element R.sub.3 and a fourth resistive element R.sub.4 coupled in series between the envelope port 104 and the first voltage rail 30 thereby forming a second voltage divider providing, at a junction between the third and fourth resistive elements R.sub.3, R.sub.4, a second divided envelope signal S.sub.2.V.sub.env, where S.sub.2 is a second constant less than unity. A third summing stage 135 is coupled to the junction between the third and fourth resistive elements R.sub.3, R.sub.4 and adds a second quiescent bias voltage V.sub.bias2.sub._.sub.0 to the second divided envelope signal S.sub.2.V.sub.env thereby forming the second bias voltage V.sub.bias2 which is delivered to the gate g.sub.2 of the second transistor M2. The fourth resistive element R.sub.4 has a variable resistance whose value may be selected by calibration as described below, but alternatively, or additionally, the third resistive element R.sub.3 may have a variable resistance.

(26) The first and second bias voltages V.sub.bias1, V.sub.bias2 are therefore dependent on the envelope signal V.sub.env, both tracking the envelope signal V.sub.env, and therefore both tracking each other. In particular, the first and second bias voltages V.sub.bias1, V.sub.bias2 are each related to the envelope signal V.sub.env by an affine function.

(27) The dependence of the first and second bias voltages V.sub.bias1, V.sub.bias2 on the envelope signal V.sub.env may be expressed as, respectively,
V.sub.bias1=S.sub.1.V.sub.env+V.sub.bias1.sub._.sub.0 (1)
V.sub.bias2=S.sub.2.V.sub.env+V.sub.bias2.sub._.sub.0 (2)
The first and second constants S.sub.1, S.sub.2 and the first and second quiescent bias voltages V.sub.bias1.sub._.sub.0 and V.sub.bias2.sub._.sub.0 may be selected by a calibration process as described below. The first and second quiescent bias voltages V.sub.bias1.sub._.sub.0 and V.sub.bias2.sub._.sub.0 correspond to values of, respectively, the first and second bias voltages V.sub.bias1, V.sub.bias2 when the input signal V.sub.0 is absent or has a zero amplitude or envelope, that is, the envelope signal V.sub.env is zero. Typically, the first and second quiescent bias voltages V.sub.bias1.sub._.sub.0, V.sub.bias2.sub._.sub.0 may be about 0.65V and 2V.

(28) The first constant S.sub.1 is determined by the ratio of the resistance of the second resistive element R.sub.2 to the sum of the resistances of the first and second resistive elements R.sub.1, R.sub.2, that is, the first constant S.sub.1 may be represented as S.sub.1=R.sub.2/(R.sub.1+R.sub.2), where R.sub.1 and R.sub.2 represent the respective resistance values. Likewise, the second constant S.sub.2 is determined by the ratio of the resistance of the fourth resistive element R.sub.4 to the sum of the resistances of the third and fourth resistive elements R.sub.3, R.sub.4, that is, the second constant S.sub.2 may be represented as S.sub.2R.sub.4/(R.sub.3+R.sub.4), where R.sub.3 and R.sub.4 represent the respective resistance values.

(29) The amplifier has a first capacitive element C.sub.1 coupled between the first voltage rail 30 and the junction of the first and second resistive elements R.sub.1, R.sub.2. Likewise, there is a second capacitive element C.sub.2 coupled between the first voltage rail 30 and the junction of the third and fourth resistive elements R.sub.3, R.sub.4. The capacitance of the first capacitive element C.sub.1 and the capacitance of the second capacitive element C.sub.2 are chosen to provide low impedance to the input signal V.sub.i and to the envelope signal V.sub.env.

(30) In operation, the first transistor M1 amplifies the input signal, which may be at RF, and the second transistor M2, in conjunction with the inductive element L, follows, that is, tracks, the voltage at the first drain d.sub.1 of the first transistor M1, increasing the voltage swing at the output port 106, and consequently increasing the output power. The coupling of the first and second transistors M1, M2 in a cascode configuration provides increased isolation between the input port 102 and the output port 106, compared with the use of a single transistor as in the amplifier 20 of FIG. 2, thereby reducing the variation in input impedance of the amplifier 100 as the envelope signal V.sub.env varies. The voltage at the output port 106 is the sum of the drain-to-source voltages of the first and second transistors M1, M2, and the first and second transistors M1, M2 both drive a load current in the load R.sub.L in the same direction.

(31) FIG. 7 illustrates load lines for the amplifier 100 for the case of the load R.sub.L having a resistance of 4.5, superimposed on a plot of voltage-current characteristics of the amplifier 100, where the vertical axis of the voltage-current characteristics represents the current flowing through both the first and second transistors M1, M2 between the drain d.sub.2 of the second transistor M2 and the first voltage rail 30, and the horizontal axis represents the output signal V.sub.o, that is, the voltage at the drain d.sub.2 of the second transistor M2. The output signal V.sub.o reaches a maximum value of 9V, corresponding to the sum of a 3V drain-source voltage across the first transistor M1, and a 6V drain-source voltage across the second transistor M2. The position of the load lines is dependent on the envelope signal V.sub.env, and three load lines (a), (b) and (c) are illustrated in FIG. 7 for three values of the envelope signal V.sub.env, the load line (a) being applicable when the envelope signal V.sub.env has a relatively low voltage, and load line (c) being applicable when the envelope signal V.sub.env has a relatively high voltage. As the envelope signal varies, the second bias voltage V.sub.bias2 varies. With no further action, this variation would tend to cause the gain of the amplifier 100 to vary in the manner illustrated in FIG. 4, resulting in a low gain when the envelope signal V.sub.env has a low voltage. However, the first bias signal V.sub.bias1 applied to the gate g.sub.1 of the first transistor M1 also varies and acts to compensate this variation in gain by increasing the bias point of the first transistor M1.

(32) Referring to FIG. 8, there are plotted curves of gain, and curves of output power P.sub.out, that is, the power of the output signal V.sub.0, both as a function of input power P.sub.in, that is, the power of the input signal V.sub.i. The gain is the ratio of output power P.sub.out to input power P.sub.in. The curves of gain and output power P.sub.out are each plotted for four different constant values of the envelope signal V.sub.env, respectively 1.8, 2.8, 3.8 and 4.8V. FIG. 8 relates to the amplifier topology described with reference to FIG. 6, except that, for the purpose of illustration, the envelope signal V.sub.env is held constant at each of the respective values and does not vary as the input power P.sub.in varies. Nevertheless, the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the respective constant values of the envelope signal V.sub.env. It can be seen that at low levels of input power P.sub.in the gain is fairly constant and the output power P.sub.out rises linearly with increasing input power P.sub.in, until the onset of compression. Compression occurs at a higher level of input power P.sub.in as the constant envelope signal V.sub.env is increased. At low levels of the input power P.sub.in, a high gain can be provided by a low value of the constant envelope signal V.sub.env, whilst at high levels of the input power P.sub.in, for high gain and low compression, a high value of the constant envelope signal V.sub.env is advantageous. Therefore, an improved combination of high gain and constant gain over a wide range of input power P.sub.in levels is provided by the amplifier 100 when the envelope signal V.sub.env tracks the envelope of the input signal V.sub.i and the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the envelope signal V.sub.env according to equations (1) and (2).

(33) For comparison, the corresponding curves to those in FIG. 8 for the amplifier 100 of FIG. 6 are plotted in FIG. 9 for an amplifier comprising cascaded transistors but where the first and second bias voltages V.sub.bias1, V.sub.bias2 are maintained constant and do not track the envelope signal V.sub.env. It can be seen from FIG. 9 that, as the level of the envelope signal reduces, the gain reduces substantially, and that the onset of compression occurs at a lower level of input power P.sub.in. Therefore, for such operation of an amplifier, in which the first and second bias voltages V.sub.bias1, V.sub.bias2 are maintained constant, there is a large variation in gain as the input power P.sub.in of the input signal V.sub.i varies and the envelope signal V.sub.env tracks the envelope of the input signal V.sub.i. This demonstrates the benefit of generating the first and second bias voltages V.sub.bias1, V.sub.bias2, dependent on the envelope signal V.sub.env.

(34) Referring to FIG. 10, there are plotted curves of current drawn by the amplifier 100 as a function of output power P.sub.out, that is, the power of the output signal V.sub.o. The curves are plotted for different constant values of the envelope signal V.sub.env. As for FIG. 8, FIG. 10 relates to the amplifier topology described with reference to FIG. 6, except that, for the purpose of illustration, the envelope signal V.sub.env is held constant at each of the respective values and does not vary as the input power P.sub.in, and consequently the output power P.sub.out, varies. Nevertheless, the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the respective constant values of the envelope signal V.sub.env. It can be seen that, as the curves are close together, the current is largely independent of the value of the envelope signal V.sub.env, and this characteristic enables a low variation in input impedance when the output signal and load impedance varies, thereby presenting a constant load to the signal source 11, and consequently improved linearity and stability of the signal source, when the envelope signal V.sub.env tracks the envelope of the input signal V.sub.i and the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the envelope signal V.sub.env according to equations (1) and (2).

(35) Referring to FIG. 11, there is plotted on a Smith chart the variation of input impedance of the amplifier 100 over a range of frequencies from 2.5 GHz to 2.6 GHz. There are several curves plotted, each for a different constant amplitude of the input signal V.sub.i, and consequently for a different constant value of the envelope signal V.sub.env. Nevertheless, the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the respective constant values of the envelope signal V.sub.env. It can be seen that, as the curves are close together, the input impedance is largely independent of the constant envelope signal V.sub.env, indicating that input impedance is largely constant when the envelope of the input signal V.sub.o, and consequently the envelope signal V.sub.env, output signal and load impedance vary, thereby contributing to linear and stable operation of the input source 11.

(36) The high stability of the amplifier 100 is also demonstrated in FIG. 12 in which the Rollett factor is plotted over a range of frequencies for different constant values of the envelope signal V.sub.env.

(37) Referring to FIG. 13, there is plotted the gain of the amplifier 100 as a function of frequency, with several curves plotted, each for a different constant amplitude of the input signal V.sub.i, and consequently for a different constant value of the envelope signal V.sub.env. Nevertheless, the first and second bias voltages V.sub.bias1, V.sub.bias2 are dependent on the respective constant values of the envelope signal V.sub.env. It can be seen that, around the centre frequency where the gain is highest, as the curves are close together, the gain is largely independent of the constant envelope signal V.sub.env, indicating that gain is largely constant when the envelope of the input signal V.sub.o, and consequently the envelope signal V.sub.env, varies. This characteristic can contribute to high stability of the amplifier 100.

(38) Referring to FIG. 14, a method of amplification comprises, at step 300, providing the first transistor M1 and the second transistor M2 in a cascode arrangement, that is, the drain d.sub.1 of the first transistor M1 is coupled to the source s.sub.2 of the second transistor M2 and the drain d.sub.2 of the second transistor M2 is coupled to the output port 106. Step 300 also comprises providing the inductive element L coupled between the envelope port 104 and the drain d.sub.2 of the second transistor M2.

(39) At step 305, the input signal V.sub.i is received. At step 310, the envelope signal V.sub.env, indicative of an envelope of the input signal, is received at the envelope port 104.

(40) At step 315, the first bias voltage V.sub.bias1 is generated which is dependent on the envelope signal. In some embodiments, this dependence may be limited to a range of values of the envelope signal V.sub.env, with the first bias voltage V.sub.bias1 being independent of the envelope signal V.sub.env outside of this range.

(41) At step 320, the sum of the first bias voltage V.sub.bias1 and the input signal V.sub.i, that is, V.sub.bias1+V.sub.env is delivered to the gate g.sub.1 of the first transistor M1.

(42) At step 325, the second bias voltage V.sub.bias2 is generated which is dependent on the envelope signal, and at step 330 the second bias voltage V.sub.bias2 is delivered to the gate g.sub.2 of the second transistor M2.

(43) At step 335, the amplified signal, that is, the input signal after amplification, is delivered at the output port 106. Flow then returns to step 305 and the loop is repeated continuously while the input signal V.sub.i is being received and is required to be amplified.

(44) The values of the first and second constant S.sub.1, S.sub.2 may be determined by calibration to minimise the variation in gain of the amplifier 100 as the input power P.sub.in varies. FIG. 15 illustrates a calibration scheme, although other calibration schemes may be used. The objective of the calibration scheme is to maintain the current drawn by the amplifier 100 as constant as possible at low input power, and therefore for low values of the envelope signal, which can minimise the variation in gain of the amplifier 100 as the input power P.sub.in varies. The calibration scheme illustrated in FIG. 15 involves the setting of voltages, the measurement of current, and the control of the variable resistance of the second and fourth resistive elements R.sub.2. R.sub.4. In the following description of the calibration scheme, calibration apparatus for performing such calibration steps is considered be external to the amplifier 100, and is not illustrated in FIG. 6, although other embodiments may incorporate such calibration apparatus.

(45) Referring to FIG. 15, step 400 consists of initialising the value of variable parameters. At step 400, the input signal V.sub.i is removed from the amplifier 100 by switching off the signal source 11, or otherwise decoupling the signal source 11 from the input port 102 and from the envelope tracking stage 18. Also at step 400, the envelope signal V.sub.env, first bias voltage V.sub.bias1 and second bias voltage V.sub.bias2 are set to respective typical operational values. For example, such typical operational values may be near the centre of the typical operational voltage range of the first and second transistors M1, M2. The values of the first and second bias voltages V.sub.bias1, V.sub.bias2 may be set by selecting a value for the envelope signal V.sub.env, and then adjusting the first and second quiescent bias voltages V.sub.bias1.sub._.sub.0 and V.sub.bias2.sub._.sub.0. In particular, the typical operation value of the envelope signal V.sub.env may be near the centre of the range of voltages to be supplied by the envelope tracking stage 18. In one example, the maximum voltage to be supplied by the envelope tracking stage 18 may be 5V, and the typical operational value of the envelope signal V.sub.env may be 3.6V. In addition, at step 400, the resistances of the second and fourth resistive elements R.sub.2, R.sub.4, which are variable, are set near the centre of their respective resistance ranges.

(46) At step 405, the quiescent current drawn by the amplifier 100, or by the cascode arrangement of the first and second transistors M1, M2, from a power supply is measured and compared with a target value of the quiescent current. Such a target value of the quiescent current may be near the centre of the typical operational range of currents acceptable for the first or second transistors M1, M2. In one example, the target value of the quiescent current may be 50 mA.

(47) At step 410, the resistance of the fourth resistive element R.sub.4 is adjusted, thereby adjusting the second constant S.sub.2 of equation (2) and consequently the second bias voltage V.sub.bias2, in order to adjust the quiescent current to its target value.

(48) At step 415, the envelope voltage V.sub.env is increased to a value higher than the typical operation value set at step 400, for example near the top of the operational voltage range, or near the highest voltage to be supplied by the envelope tracking stage 18. In one example this higher value may be in the range 4V to 5V. This action will result in an increase in the second bias voltage V.sub.bias2, and so, also at step 415, the second bias voltage V.sub.bias2 is measured again.

(49) At step 420, if the second bias voltage V.sub.bias2 measured at step 415 is unacceptably high for the first or second transistors M1, M2, the fourth resistive element R.sub.4 is re-adjusted to reduce the second bias voltage V.sub.bias2 to an acceptable value. This action determines the final resistance of the fourth resistive element R.sub.4.

(50) At step 425, the resistance, or setting, of the fourth resistive element R.sub.4 is recorded. This value, in conjunction with the resistance of the third resistive element R.sub.3, determines the final value of the second constant S.sub.2 in equation (2). This recorded resistance, or setting, can be employed subsequently for the fourth resistive element R.sub.4 when amplifying the input signal V.sub.i.

(51) At step 430, the envelope signal V.sub.env is reset to the typical voltage set at step 400, and at step 435, the quiescent current drawn by the amplifier 100, or by the cascode arrangement of the first and second transistors M1, M2, from a power supply is measured and compared with the target value of the quiescent current, as in step 405.

(52) The re-adjustment of the fourth resistive element R.sub.4 at step 420 may have affected the quiescent current, and so at step 440, the resistance of the second resistive element R.sub.2 is adjusted, thereby adjusting the first constant S.sub.1 of equation (1) and consequently the first bias voltage V.sub.bias1, in order to restore the quiescent current to its target value.

(53) At step 445, the envelope voltage V.sub.env is decreased to a value lower than the typical operation value set at step 400, for example near the bottom of the operational voltage range, or near the lowest voltage to be supplied by the envelope tracking stage 18. In one example this lower value may be 1.8V. This action will result in a reduction in the quiescent current, and so at step 450 the resistance of the second resistive element R.sub.2 is re-adjusted to restore the quiescent current to its target value. This action determines the final resistance of the second resistive element R.sub.2.

(54) At step 455, the resistance, or setting, of the second resistive element R.sub.2 is recorded. This value, in conjunction with the resistance of the first resistive element R.sub.1, determines the final value of the first constant S.sub.1 in equation (1). This recorded resistance, or setting, can be employed subsequently for the second resistive element R.sub.2 when amplifying the input signal.

(55) Referring to FIG. 16, an amplifier 200 has an input port 202 for receiving an input signal V.sub.i, an envelope port 204 for receiving an envelope signal V.sub.env indicative of an envelope of the input signal V.sub.i, and an output port 206 for delivering an amplified signal V.sub.o. The input port 202 is coupled to a signal source 11, which delivers the input signal V.sub.i, by means of an input coupling capacitor C.sub.i. The envelope port 204 is coupled to the signal source 11 by means of an envelope tracking stage 18. The envelope tracking stage 18 receives the input signal V.sub.i from the signal source 11 and generates the envelope signal V.sub.env, which it delivers to the envelope port 204. The output port 206 is coupled to a load R.sub.L by means of an output coupling capacitor C.sub.o.

(56) The amplifier 200 has a first transistor M1 and a second transistor M2. A drain d.sub.1 of the first transistor M1 is coupled to a source s.sub.2 of the second transistor M2, the first and second transistors M1, M2 being coupled in a cascode configuration, with the first transistor M1 in a common source configuration and the second transistor M2 in a common gate configuration. A gate g.sub.1 of the first transistor M1 is coupled to an output 243 of a first summing stage 240, and a drain d.sub.2 of the second transistor M2 is coupled to the output port 206. A source s.sub.1 of the first transistor M1 is coupled to a first voltage supply rail 30, which may be ground. An inductive element L is coupled between the envelope port 204 and the drain d.sub.2 of the second transistor M2, for applying the envelope signal V.sub.env to the cascode arrangement of the first and second transistors M1, M2. The first summing stage 240 has a first input 241 coupled to the input port 202 for receiving the input signal V.sub.i, a second input 242 for receiving a first bias voltage Vbias1, and the output 243 of the first summing stage 240 delivers a sum of the input signal V.sub.i and the first bias voltage V.sub.bias1.

(57) A first biasing circuit 220 is coupled between the envelope port 204 and the second input 242 of the first summing stage 240, and generates a first bias voltage V.sub.bias1. The first bias voltage V.sub.bias1 is dependent on the envelope signal V.sub.env, when the envelope signal V.sub.env is less than a reference voltage V.sub.ref, and has a constant value V.sub.dd when the envelope signal V.sub.env is greater than the reference voltage V.sub.ref. In particular, the first biasing circuit 220 may comprise a first resistive element R.sub.1 and a second resistive element R.sub.2 coupled in series between a first terminal of a first switch X.sub.1 and the first voltage rail 30. A second terminal of the first switch X.sub.1 is coupled to the envelope port 204. Therefore, the first and second resistive elements R.sub.1, R.sub.2 form a first voltage divider providing, when the first switch X.sub.1 is closed, that is, provides a short circuit, a first divided envelope signal S.sub.1.V.sub.env by dividing the envelope signal V.sub.env present at the envelope port 204, and delivers the first divided envelope signal S.sub.1.V.sub.env at a junction between the first and second resistive elements R.sub.1, R.sub.2. The junction between the first and second resistive elements R.sub.1, R.sub.2 is coupled to a first terminal T.sub.1 of a second switch X.sub.2 by means of a second summing stage 225 which adds a first quiescent bias voltage Vbias.sub.1.sub._.sub.0 to the first divided envelope signal S.sub.1.V.sub.env. When the second switch X.sub.2 is in a first switch position, an output of the second summing stage 225 is coupled to the second input 242 of the first summing stage 240 by means of a fifth resistive element R.sub.5, in which case the first bias voltage V.sub.bias1 is the sum of the first divided envelope signal S.sub.1.V.sub.env and the first quiescent bias voltage V.sub.bias1.sub._.sub.0. When the second switch X.sub.2 is in a second switch position, the second summing stage 225 is decoupled from the second input 242 of the first summing stage 240, and instead the second switch X.sub.2 couples a second voltage rail 32, having a constant voltage V.sub.dd and coupled to a second terminal T.sub.2 of the second switch X.sub.2, to the second input 242 of the summing stage 240 by means of the fifth resistive element R.sub.5. A comparator 212 has a first input coupled to the envelope port 204 and a second input coupled to the reference voltage V.sub.ref. An output of the comparator 212 is coupled to control the first and second switches X.sub.1, X.sub.2 such that, when the envelope signal V.sub.env is less than the reference voltage V.sub.ref, the first switch X.sub.1 is closed and the second switch X.sub.2 is in the first switch position. In this state, the first bias voltage V.sub.bias1 is dependent on the envelope signal V.sub.env. When the envelope signal V.sub.env is greater than the reference voltage V.sub.ref, the output of the comparator 212 causes the first switch X.sub.1 to open, thereby decoupling the first voltage divider, consisting of the first and second resistive elements R.sub.1, R.sub.2, from the envelope port 204 and preventing any current drain through the first voltage divider, and the second switch X.sub.2 to adopt the second switch position. In this state, the first bias voltage V.sub.bias1 delivered to the second input 242 of the summing stage 240 by the first biasing circuit 220 is constant, being at the voltage V.sub.dd of the second voltage rail 32, and therefore independent on the envelope signal V.sub.env. The first, or alternatively or additionally the second, resistive element R.sub.1, R.sub.2 has a variable resistance whose value may be selected by calibration as described below.

(58) A second biasing circuit 230 is coupled between the envelope port 204 and the gate g.sub.2 of the second transistor M2, and generates a second bias voltage V.sub.bias2 dependent on the envelope signal V.sub.env, and provides the second bias voltage V.sub.bias2 to the gate g.sub.2 of the second transistor M2. In particular, the second biasing circuit 230 may comprise a third resistive element R.sub.3 and a fourth resistive element R.sub.4 coupled in series between the envelope port 204 and the first voltage rail 30 thereby forming a second voltage divider providing, at a junction between the third and fourth resistive elements R.sub.3, R.sub.4, a second divided envelope signal S.sub.2.V.sub.env, where S.sub.2 is a second constant less than unity. A third summing stage 235 is coupled to the junction between the third and fourth resistive elements R.sub.3, R.sub.4 and adds a second quiescent bias voltage V.sub.bias2.sub._.sub.0 to the second divided envelope signal S.sub.2.V.sub.env, thereby forming the second bias voltage V.sub.bias2 which is delivered to the gate g.sub.2 of the second transistor M2. The fourth, or alternatively or additionally the third, resistive element R.sub.4, R.sub.3 has a variable resistance whose value may be selected by calibration as described below.

(59) The first and second bias voltages V.sub.bias1, V.sub.bias2 are, when the envelope signal V.sub.env is less than the reference voltage V.sub.ref, therefore dependent on the envelope signal V.sub.env, both tracking the envelope signal V.sub.env, and therefore both tracking each other. In particular, in this circumstance, the first and second bias voltages V.sub.bias1, V.sub.bias2 are related to the envelope signal V.sub.env by an affine function. As in the case of the amplifier 100 described with respect to FIG. 6, the dependence of the first and second bias voltages V.sub.bias1, V.sub.bias2 on the envelope signal V.sub.env may be expressed generally by, respectively, equations (1) and (2). When the envelope signal V.sub.env exceeds the reference voltage V.sub.ref, only the second bias voltage V.sub.bias2 is dependent on the envelope signal V.sub.env, and tracks the envelope signal V.sub.env, and the first bias voltage V.sub.bias1 is constant. This embodiment of FIG. 16 can be used in circumstances where, when the envelope signal V.sub.env is greater than the reference voltage V.sub.ref, the tracking of the envelope signal V.sub.env by only the second bias voltage V.sub.bias2 provides a sufficiently constant gain, with the tracking of the envelope signal V.sub.env by also the first bias voltage V.sub.bias2 being added only when the envelope signal V.sub.env is less than the reference voltage V.sub.ref to prevent the gain decreasing too much.

(60) The amplifier 200 has a first capacitive element C.sub.1 coupled between the first voltage rail 30 and the junction of the first and second resistive elements R.sub.1, R.sub.2. Likewise, there is a second capacitive element C.sub.2 coupled between the first voltage rail 30 and the junction of the third and fourth resistive elements R.sub.3, R.sub.4. The capacitance of the first capacitive element C.sub.1 and the capacitance of the second capacitive element C.sub.2 are chosen to provide low impedance to the input signal V.sub.i and to the envelope signal V.sub.enc.

(61) Calibration of the amplifier 200 may be performed using the calibration scheme described above with reference to FIG. 15, with an additional step to select the reference voltage V.sub.ref.

(62) Referring to FIG. 17, there is illustrated an electronic apparatus 500 comprising the amplifier 100, although the amplifier 200 may alternatively be employed. In this example, the electronic apparatus 500 is a wireless communication device such as a mobile phone. An antenna 505, for receiving an RF signal is coupled to an input of a low noise amplifier (LNA) 510 for amplifying the RF signal received by the antenna 505. An output of the LNA 510 is coupled to a down-conversion stage 515 for down-converting the RF signal to baseband signals by mixing the RF signal with a local oscillator signal supplied to the down-conversion stage 515 by a local oscillator 520. An output of the down-conversion stage 515 is coupled to a baseband processing stage (BB) 525 for demodulating and decoding the baseband signal. The BB 525 is coupled to an up-conversion stage 530 for up-converting to RF a baseband signal to be transmitted, by mixing the baseband signal with a local oscillator signal supplied to the up-conversion stage 530 by the local oscillator 520. An output of the up-conversion stage 530 is coupled to an input 102 of the amplifier 100, which may be a power amplifier (PA), to deliver the RF signal after up-conversion as an input signal V.sub.i to the amplifier 100. The output of the up-conversion stage 530 is also coupled to an envelope tracking stage 18 for generating the envelope signal V.sub.env. An output of the envelope tracking stage 18 is coupled to an envelope input 104 of the amplifier 100 for delivering the envelope signal V.sub.env. An output of the amplifier 100 is coupled to the antenna 505 for emitting the amplified RF signal.

(63) In the amplifier 100 described with reference to FIG. 6 and the amplifier 200 described with reference to FIG. 16, each of the first, second and third summing stages 140, 240, 125, 225, 135, 235 may be implemented as, for example, a plurality of resistive elements coupled to a common node.

(64) Although embodiments have been described in which the envelope tracking stage 18 is external to the amplifier 100, alternatively the amplifier 100 or amplifier 200 may comprise the envelope tracking stage 18. Likewise, the method of amplification may comprise generating the envelope signal V.sub.env from the input signal V.sub.i. In some embodiments, the envelope tracking stage 18 may be arranged to generate the envelope signal V.sub.env quantised to have fewer values than the envelope of the input signal V.sub.i. Likewise, the method of amplification may comprise generating the envelope signal V.sub.env quantised to have fewer values than the input signal V.sub.i.

(65) Although embodiments have been described which the transistors are NMOS transistors, alternatively PMOS transistors may be used.

(66) Although embodiments have been described with reference to an input signal V.sub.i that is at a radio frequency, the disclosure is also applicable at other frequencies.

(67) Although embodiments have been described in which two transistors are coupled in a cascode arrangement, the disclosure is not limited to two transistors, and more than two transistor may be coupled in a cascode arrangement, and the gate of each transistor provided with a bias voltage dependent on the envelope signal V.sub.env.

(68) Other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features which are already known and which may be used instead of, or in addition to, features described herein.

(69) Features that are described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, features which are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

(70) It should be noted that the term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality, a single feature may fulfil the functions of several features recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims. It should also be noted that the Figures are not necessarily to scale; emphasis instead generally being placed upon illustrating the principles of the present invention.