Method of making threshold voltage tuning using self-aligned contact cap

Abstract

Methods of forming a PFET dielectric cap with varying concentrations of H.sub.2 reactive gas and the resulting devices are disclosed. Embodiments include forming p-type and n-type metal gate stacks, each surrounded by SiN spacers; forming an ILD surrounding the SiN spacers; planarizing the ILD, the metal gate stacks, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layers in the respective first cavities; and forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity.

Claims

1. A method comprising: forming a p-type metal gate stack and a n-type metal gate stack, each surrounded by silicon nitride (SiN) spacers; forming an interlayer dielectric (ILD) surrounding the SiN spacers; planarizing the ILD, the p-type metal gate stack and n-type metal gate stack, and the SiN spacers; determining at least one desired threshold voltage for the p-type metal gate stack; forming a first cavity in the p-type metal gate stack for each desired threshold voltage and forming a second cavity in the n-type metal gate stack; selecting a first nitride layer for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity; forming the first nitride layer in respective first cavities; forming a second nitride layer, with a hydrogen rich reactive gas, in the second cavity; forming the first nitride layer in the second cavity to a thickness of 3 nanometers (nm) to 5 nm concurrently with forming each first nitride layer in each respective first cavity; and removing the first nitride layer from the second cavity, prior to forming the second nitride layers.

2. The method according to claim 1, comprising: forming a single cavity and selecting the first nitride layer with a hydrogen free reactive gas.

3. The method according to claim 2, comprising planarizing the ILD, the p-type and n-type metal gate stacks, and the SiN spacers by chemical mechanical polishing (CMP).

4. The method according to claim 2, comprising forming the first nitride layer using nitrogen (N.sub.2) and forming the second nitride layer using ammonia/hydrogen gas (NH.sub.3/H.sub.2).

5. The method according to claim 1, comprising forming the first cavity in the p-type metal gate stack and forming the second cavity in the n-type metal gate stack by a halide-based etch process.

6. The method according to claim 5, comprising etching each of the first and second cavities to a depth of 20 nm to 50 nm.

7. The method according to claim 1, further comprising removing a portion of the SiN spacers to a depth of 20 nm to 50 nm prior to forming each of the first and second cavities in the p-type and n-type metal gate stacks, respectively.

8. A method comprising: forming p-type and n-type metal gate stacks, each surrounded by silicon nitride (SiN) spacers; forming an interlayer dielectric (ILD) surrounding the SiN spacers; planarizing the ILD, the p-type and n-type metal gate stacks, and the SiN spacers; forming a first cavity in the p-type metal gate stack and forming a second cavity in the n-type metal gate stack; forming a nitride liner, with a high density plasma (HDP) process using nitrogen gas (N.sub.2), in each of the first and second cavities; forming a bulk nitride layer, by HDP using ammonia (NH.sub.3), on the nitride liner; and planarizing the bulk nitride layer down to the ILD.

9. The method according to claim 8, comprising forming the nitride liner to a thickness of 3 nanometers (nm) to 10 nm.

10. The method according to claim 8, further comprising removing a portion of the SiN spacers surrounding each gate stack prior to removing the portion of the first and second metal gate stacks.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

(2) FIGS. 1 through 7 schematically illustrate steps of a method of forming PFET and NFET dielectric cap liners with H.sub.2-free reactive gas, in accordance with an exemplary embodiment;

(3) FIGS. 8 through 11 schematically illustrate sequential steps of a method of forming a PFET dielectric cap liner with H.sub.2-free reactive gas and an NFET dielectric cap with H.sub.2-rich reactive gas, in accordance with an exemplary embodiment;

(4) FIGS. 12 through 14 schematically illustrate sequential steps of a method of forming a PFET dielectric cap with H.sub.2-free reactive gas and an NFET dielectric cap with H.sub.2-rich reactive gas, in accordance with an exemplary embodiment; and

(5) FIGS. 15A and 15B schematically illustrate the relationship between the H.sub.2 reactive gas concentration and the resultant threshold voltage (VTlin).

DETAILED DESCRIPTION

(6) In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

(7) The present disclosure addresses and solves the current problem of Vt shift or Vt roll-up issues attendant upon forming a gate stack dielectric cap by a hydrogen plasma process. By forming PFET and NFET gate stack dielectric caps with H.sub.2-free and H.sub.2-rich gases, respectively, Vt shift or Vt roll-up issues are prevented.

(8) Methodology in accordance with embodiments of the present disclosure includes forming p-type and n-type metal gate stacks, each surrounded by SiN spacers. An ILD is formed surrounding the SiN spacers. The ILD, the p-type and n-type metal gate stacks, and the SiN spacers are planarized. At least one desired threshold voltage is determined for the p-type metal gate stack. A first cavity is formed in the p-type metal gate stack for each desired threshold voltage and a second cavity is formed in the n-type metal gate stack. A first nitride layer is selected for each first cavity, the first nitride layer for each cavity having a concentration of hydrogen reactive gas based on the desired threshold voltage associated with the cavity. The first nitride layers are formed in the respective first cavities. A second nitride layer, with a hydrogen rich reactive gas, is formed in the second cavity.

(9) Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

(10) FIGS. 1 through 7 schematically illustrate sequential steps of a method of forming PFET and NFET dielectric cap liners with H.sub.2-free reactive gas, in accordance with an exemplary embodiment. Adverting to FIG. 1, source/drain regions 101 are formed on a semiconductor substrate 103, e.g., planar or FIN, on opposite sides of metal gate stacks 105 and 106, each surrounded by SiN spacers 107. Metal gate stacks 105 and 106 may, for example, be a PFET and an NFET, respectively. An ILD 109 is also formed on a SiN liner 111 formed on top of the source/drain regions 101. The ILD 109, the metal gate stacks 105 and 106, and the SiN spacers 107 are then planarized by CMP.

(11) A portion of each of the metal gate stacks 105 and 106 and a portion of the SiN spacers 107 are removed by a halide-based etch process to a depth of 20 nm to 50 nm, e.g., 40 nm, forming cavities 201 and 203, respectively, as depicted in FIG. 2. Alternatively, a portion 301 of the SiN spacers 107 can be removed to a depth of 20 nm to 50 nm, e.g., 40 nm, prior to removing the portion of each of the metal gate stacks 105 and 106, as illustrated in FIG. 3.

(12) Adverting to FIG. 4, a nitride liner 401 is formed to a thickness of 3 nm to 5 nm in each of the cavities 201 and 203 by a HDP process using a H.sub.2-free reactive gas, e.g., N.sub.2 or NH.sub.3. Next, a bulk nitride layer 501 is formed on the nitride liner 401 by HDP using NH.sub.3, as depicted in FIG. 5. Thereafter, the bulk nitride layer 501 and the nitride liner 401 are planarized by CMP down to the ILD 109, as illustrated in FIG. 6. Adverting to FIG. 7, a second ILD 701 is formed over the ILD 109, the nitride liner 401, and the bulk nitride layer 501. Then source/drain contacts 703 are formed through the ILDs 109 and 701 down to the source/drain regions 101. The nitride liner 401 blocks hydrogen from diffusing into the PFET gate electrode, preventing the PFET Vt shift.

(13) FIGS. 8 through 11 schematically illustrate sequential steps of a method of forming a PFET dielectric cap liner with H.sub.2-free reactive gas and an NFET dielectric cap with H.sub.2-rich reactive gas, in accordance with another exemplary embodiment. Adverting to FIG. 8, after removing a portion of each of the metal gate stacks 105 and 106 and a portion of the SiN spacers 107, as depicted in FIG. 2, a nitride layer 801 is formed in the cavity 201 to a thickness of 3 nm to 5 nm using a H.sub.2-free reactive gas, e.g., N.sub.2. Alternatively, the nitride layer 801 can also be formed in the cavity 203 to a thickness of 3 nm to 5 nm using an H.sub.2-free reactive gas, e.g., N.sub.2, concurrently with forming the nitride layer 801 in the cavity 201 (not shown for illustrative convenience) and then removed from the cavity 203.

(14) Thereafter, a nitride layer 901 is formed over the nitride layer 801 in the cavity 201 and in the cavity 203 using an H.sub.2-rich reactive gas, e.g., NH.sub.3/H.sub.2, as depicted in FIG. 9. Adverting to FIG. 10, the nitride layer 901 and the nitride layer 801 are planarized by CMP down to the ILD 109. Next, a second ILD 1101 is formed over the ILD 109, the nitride layer 801, and the nitride layer 901 and then source/drain contacts 1103 are formed through the ILDs 109 and 1101 down to the source/drain regions 101, as depicted in FIG. 11. The nitride liner in the PFET dielectric cap prevents PFET Vt shift. At the same time, eliminating the nitride liner in the NFET dielectric cap (though requiring an additional patterning step), allows hydrogen to penetrate into the NFET gate stack and act as an oxygen scavenging source, eliminating Vt roll-up.

(15) FIGS. 12 through 14 schematically illustrate sequential steps of a method of forming a PFET dielectric cap with H.sub.2-free reactive gas and an NFET dielectric cap with H.sub.2-rich reactive gas, in accordance with another exemplary embodiment. Adverting to FIG. 12, after removing a portion of each of the metal gate stacks 105 and 106 and a portion of the SiN spacers 107 as depicted in FIG. 12, a nitride layer 1201 is formed with an H.sub.2-free reactive gas, e.g., NH.sub.3, in the cavity 201 and a nitride layer 1203 is formed with an H.sub.2-rich reactive gas, e.g., NH.sub.3/H.sub.2, in the cavity 203. The nitride layer 1201 and the nitride layer 1203 are then planarized by CMP down to the ILD 109, as depicted in FIG. 13. Adverting to FIG. 14, a second ILD 1401 is formed over the ILD 109, the nitride layer 1201, and the nitride layer 1203. Then source/drain contacts 1403 are formed through the ILDs 109 and 1401 down to the source/drain regions 101. The nitride in cavity 201 blocks hydrogen from penetrating into the PFET, whereas the nitride in cavity 203 allows hydrogen to penetrate into the NFET, which simultaneously eliminates Vt shift in the PFET and VT roll-up in the NFET. However, an extra masking step may be required for the separate deposition of the two types of nitride.

(16) Although FIGS. 12 through 14 illustrate forming an H.sub.2-free reactive gas for the PFET dielectric cap, nitride layer 1201 may alternatively be formed with a concentration of H.sub.2 reactive gas based on a desired threshold voltage of the PFET. For example, FIGS. 15A and 15B schematically illustrate the relationship between the H.sub.2 reactive gas concentration (FIG. 15A) and the resultant VTlin (FIG. 15B). For example, nitrides 1503 and 1507 have relatively high H.sub.2 contents and relatively high resultant VTlins, whereas nitrides 1501 and 1505 have relatively low H.sub.2 contents and relatively low resultant VTlins. Therefore, the greater the H.sub.2 concentration that is used to form the particular nitride, the greater the resultant Vtlin. For multiple threshold voltages, multiple cavities (not shown for illustrative convenience) may be formed in metal gate stack 105, and a different nitride (i.e., with a different H.sub.2 reactive gas concentration) may be formed in each cavity. In other words, the nitride for the PFET dielectric cap may be selected to tune the threshold voltage of the PFET. In addition, a H.sub.2-free nitrogen layer, e.g., nitride layer 801, may be formed in one or more of the cavities of the metal gate stack 105 and then removed from a specific cavity that is desired to be tuned with a particular nitride having a particular hydrogen concentration.

(17) The embodiments of the present disclosure can achieve several technical effects including forming a PFET dielectric cap with an H.sub.2-free reactive gas, thereby preventing H.sub.2 radicals from degrading the PFET Vt, which can cause Vt shift. At the same time, the introduction of an H.sub.2-rich reactive gas in forming an NFET dielectric cap can prevent NFET Vt roll-up issues, since the H.sub.2 can penetrate into gate stack as an oxygen scavenging source while the nitride layer/liner acts as an H.sub.2 blocker on the PFET side. Alternatively, the PFET can be formed with different nitrides having different concentrations of H.sub.2-rich reactive gas so as to enable tuning of the threshold voltage of the PFET. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of semiconductor devices with SACs, particularly for 14 nm technology nodes and beyond, or sub-64 nm CPP devices.

(18) In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.