Tag with advanced clock extraction

Abstract

A receiver exposed to a magnetic field with a specified carrier frequency in the RF frequency area and configured to extract an internal clock signal for processing of data with a receiver IC. The receiver includes an antenna configured to receive an antenna signal and a tuning circuit and configured to provide a first received signal at a first pin of the receiver IC and a second receiver signal at a second pin of the receiver IC. The receiver IC includes a harvesting stage configured to rectify a differential received signal provided between the first pin and the second pin of the receiver IC and configured to provide a supply voltage referenced to a ground potential for the receiver IC, and a clock extraction stage configured to provide a first threshold level to switch the internal clock signal with a rectangular signal shape between high and low potential.

Claims

1. A receiver configured to be exposed to a magnetic field with a specified carrier frequency and built to extract an internal clock signal for processing of data with a receiver IC of the receiver, which receiver comprises: an antenna built to receive an antenna signal and a tuning circuit and built to provide a first received signal at a first pin of the receiver IC and a second receiver signal at a second pin of the receiver IC, which receiver IC comprises: a harvesting stage built to rectify a differential received signal provided between the first pin and the second pin of the receiver IC and built to provide a supply voltage referenced to a ground potential for the receiver IC; and a clock extraction stage built to provide a first threshold level to switch the internal clock signal with a rectangular signal shape between high and low potential, wherein the clock extraction stage is built to provide a second threshold level and to provide a low threshold level, which is closer to ground potential than the first threshold level and the second threshold level, which clock extraction stage is built to switch the internal clock signal from low potential to high potential, if a voltage of the first received signal referenced to ground potential is above or passes above the first threshold level and a voltage of the second received signal referenced to ground potential is below or passes below the low threshold level and, which clock extraction stage is built to switch the internal clock signal from high potential to low potential, if the voltage of the first received signal referenced to ground potential is below or passes below the low threshold level and the voltage of the second received signal referenced to ground potential is above or passes above the second threshold level.

2. The receiver according to claim 1, wherein the receiver IC comprises a threshold adaption circuit built to adapt the first threshold level, if a peak voltage of the first received signal changes over time and/or built to adapt the second threshold level, if a peak voltage of the second received signal changes over time.

3. The receiver according to claim 2, wherein the threshold adaption circuit is built to increase a voltage of the first threshold level to a fixed first voltage below an actual peak voltage of the first received signal, if the actual peak voltage of the first received signal is higher than the actual voltage of the first threshold level plus the fixed first voltage and/or wherein the threshold adaption circuit is built to increase a voltage of the second threshold level a fixed second voltage below an actual peak voltage of the second received signal, if the actual peak voltage of the second received signal is higher than the actual voltage of the second threshold level plus the fixed second voltage.

4. The receiver according to claim 2, wherein the threshold adaption circuit is built to continuously reduce the voltage of the first threshold level and/or built to continuously reduce the voltage of the second threshold level based on a time constant.

5. The receiver according to claim 1, wherein the low threshold level is fixed and not adopted over time.

6. The receiver according to claim 2, wherein the clock extraction stage is realized with a first threshold inverter to observe the first threshold level, which first threshold inverter is connected with its input to the first pin of the receiver IC and with its supply to a voltage of the first threshold level referenced to ground potential and/or wherein the clock extraction stage is realized with a second threshold inverter to observe the second threshold level, which second threshold inverter is connected with its input to the second pin of the receiver IC and with its supply to a voltage of the second threshold level referenced to ground potential.

7. The receiver according to claim 1, wherein the receiver comprises a PLL stage connected to the output of the clock extraction stage.

8. The receiver according to claim 1, wherein the antenna and tuning circuit is built to receive the antenna signal with the carrier frequency of the system defined NFC resonance frequency of 13.56 MHz.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a receiver with a clock extraction stage according to the state of the art.

(2) FIG. 2 shows good quality received signals and the internal clock signal extracted with the state of the art clock extraction stage of FIG. 1.

(3) FIG. 3 shows distorted received signals and the bad quality internal clock signal extracted with the state of the art clock extraction stage of FIG. 1.

(4) FIG. 4 shows an embodiment of a receiver IC of a clock extraction stage according to the invention.

(5) FIG. 5 shows example signals how the clock extraction stage of FIG. 4 sets and resets the internal clock signal.

(6) FIG. 6 shows signals of a first computer simulation how the clock extraction circuit of FIG. 4 sets and resets the internal clock signal even with distorted received antenna signals.

(7) FIG. 7 shows signals of a second computer simulation of a comparison of the internal clock signal extracted by the state of the art the clock extraction circuit of FIG. 1 and by the inventive clock extraction circuit of FIG. 4.

DETAILED DESCRIPTION OF EMBODIMENTS

(8) FIG. 4 shows a clock extraction stage 18 of a receiver 19 exposed to a magnetic field with a specified carrier frequency in the RF frequency area and built to extract an internal clock signal CLK for processing of data with a receiver IC 20 of the receiver 19. Reference is made to the explanation of the state of the art receiver 3 in FIG. 1, because reference numbers of all circuits and stages disclosed and explained there, that have the same technical function, will be used in the description of the inventive receiver 19. The inventive receiver 19 differs from the state of the art receiver 3 in the concept of the clock extraction stage 18 shown in FIG. 4 and that the clock extraction stage 18 comprises a first input pin 21, connected to the first pin 10 of receiver IC 20, and comprises a second input pin 22, connected to the second input pin 11 of receiver IC 20.

(9) Clock extraction stage 18 is built to provide a first threshold level TH1 to switch the internal clock signal CLK with a rectangular signal shape between high and low potential to set and reset the internal clock signal CLK. Clock extraction stage 18 is furthermore built to provide a second threshold level TH2 and to provide a low threshold level THL, which low threshold level THL is closer to ground potential GRD than the first threshold level TH1 and the second threshold level TH2. The clock extraction stage 18 is built to switch the internal clock signal CLK from low potential to high potential (set CLK), if the voltage U.sub.RS1 of the first received signal RS1 referenced to ground potential GRD is above or passes above the first threshold level TH1 and the voltage U.sub.RS2 of the second received signal RS2 referenced to ground potential GRD is below or passes below the low threshold level THL. The clock extraction stage is furthermore built to switch the internal clock signal CLK from high potential to low potential (reset CLK), if the voltage U.sub.RS1 of the first received signal RS1 referenced to ground potential GRD is below or passes below the low threshold level THL and the voltage U.sub.RS2 of the second received signal RS2 referenced to ground potential GRD is above or passes above the second threshold level TH2. Above described logic to set and reset the internal clock signal CLK is shown in below table:

(10) TABLE-US-00001 Condition Internal Clock Signal CLK (U.sub.RS1 > U.sub.TH1) AND (U.sub.RS2 < U.sub.THL) SET (U.sub.RS2 > U.sub.TH2) AND (U.sub.RS1 < U.sub.THL) RESET

(11) FIG. 4 shows one concrete implementation to realize this logic to set and reset the internal clock signal CLK with six inverters 23 to 28 and two NAND gates 29 and 30 and a flip flop 31 and a buffer 32. The function of this implementation will explained based on the first received signal RS1 and the second received signal RS2 and the therefrom extracted internal clock signal CLK shown in FIG. 5.

(12) Clock extraction stage 18 furthermore comprises a threshold adaption circuit 33 built to adapt the first threshold level TH1, if a peak voltage U.sub.PEEK RS1 of the first received signal RS1 changes over time, and/or built to adapt the second threshold level TH2, if a peak voltage U.sub.PEEK RS2 of the second received signal RS2 changes over time. The actual peak voltage U.sub.PEEK of these received signal RS is the highest peak of the amplitude during the past periods of the received signal RS as can be seen in FIG. 5.

(13) To adapt the first threshold level TH1 the threshold adaption circuit 33 is built to increase a voltage U.sub.TH1 of the first threshold level TH1 to a fixed first voltage P1 below the actual peak voltage U.sub.PEEK RS1 of the first received signal RS1, if the actual peak voltage U.sub.PEEK RS1 of the first received signal RS1 is higher than the actual voltage U.sub.TH1 of the first threshold level TH1 plus the fixed first voltage P1. The fixed first voltage P1 and/or the fixed second voltage P2 for instance may be 0.1V or 0.3V or 0.5V or 0.75V or 1V and ensures that a voltage U.sub.TH1 of the first threshold level TH1 is below the peak voltage U.sub.PEEK RS1 of the first received signal RS1 and that the voltage U.sub.TH2 of the second threshold level TH2 is below the peak voltage U.sub.PEEK RS2 of the second received signal RS2 as can be seen in FIG. 5. This mechanism to increase the voltage U.sub.TH1 of the first threshold level TH1 is shown in FIG. 5 where the dashed line of the continuously adopted voltage U.sub.TH1 of the first threshold level TH1 runs with the distance of the fixed first voltage P1 parallel to a dashed line that starts from the peak voltage U.sub.PEEK RS1 and decreases from there until it is increased again. In the same way the threshold adaption circuit 33 is built to increase a voltage U.sub.TH2 of the second threshold level TH2 a fixed second voltage P2 below an actual peak voltage U.sub.PEEK RS2 of the second received signal RS2, if the actual peak voltage U.sub.PEEK RS2 of the second received signal RS2 is higher than the actual voltage U.sub.TH2 of the second threshold level TH2 plus the fixed second voltage P2. This mechanism ensures that first threshold level TH1 and the second threshold level TH2 are increased if the magnetic field gets stronger with larger amplitudes of the first received signal RS1 and the second received signal RS2.

(14) Threshold adaption circuit 33 furthermore is built to continuously reduce the first threshold level TH1 and the second threshold level TH2 based on a time constant. The time constant may be realized with a RC stage in threshold adaption circuit 33 for each threshold level where the peak voltage U.sub.PEEK RS is used to load a capacitor that is unloaded over an ohmic resistance over time. FIG. 5 shows this unloading which reduces and thereby adopts a voltage U.sub.TH1 of the first threshold level TH1 and adopts a voltage U.sub.TH2 of the second threshold level TH2. This ensures that first threshold level TH1 and the second threshold level TH2 are reduced over time if the magnetic field gets weaker with smaller amplitudes of the first received signal RS1 and the second received signal RS2. The time constant for the continuous reduction of the threshold levels has to be chosen based on the clock frequency of the internal clock signal CLK and how fast the threshold level should react on changes of the peak amplitude/voltage of the received signals RS1 and RS2.

(15) The function of the implementation of clock extraction stage 18 will now be explained. The first received signal RS1 is input to the clock extraction stage 18 at the first input pin 21 and provided to inverter 23 and inverter 26 and threshold adaption circuit 33. The second received signal RS2 is input to the clock extraction stage 18 at the second input pin 22 and provided to inverter 24 and inverter 25 and threshold adaption circuit 33. Threshold adaption circuit 33 evaluates voltage U.sub.TH1 of the first threshold level TH1 and voltage U.sub.TH2 of the second threshold level TH2 as explained above with continuously increasing and decreasing voltages as shown in FIG. 5. Inverter 25 and inverter 26 realize together with NAND gate 30 the logic equation (U.sub.RS1>U.sub.TH1) AND (U.sub.RS2<U.sub.THL) of above table to set the internal clock signal CLK. Furthermore inverter 23 and inverter 24 realize together with NAND gate 29 the logic equation (U.sub.RS2>U.sub.TH2) AND (U.sub.RS1<U.sub.THL) of above table to reset the internal clock signal CLK. Inverters 27 and 28 supplied with VDD convert the output voltage level of inverters 24 and 26, that depend on the changing voltages U.sub.TH1 and U.sub.TH2 of the threshold levels TH1 and TH2, to the voltage of logic levels used in the clock extraction circuit 18. The set and reset output voltages of NAND gates 29 and 30 are used to set or reset flip flop 31 and buffer 32 amplifies the current output level of flip flop 31 to provide internal clock signal CLK at an output pin of clock extraction stage 18.

(16) FIG. 5 shows how this implementation of clock extraction stage 18 sets and resets the internal clock signal CLK. At time instance t1 the condition (U.sub.RS1>U.sub.TH1) AND (U.sub.RS2<U.sub.THL) is met and internal clock signal CLK is set. At time instance t2 the first receiver signal RS1 and the second receiver signal RS2 have a distortion, but none of the conditions to set or reset the internal clock signal CLK is given, what enables a robust internal clock signal CLK. At time instance t3 the condition (U.sub.RS2>U.sub.TH2) AND (U.sub.RS1<U.sub.THL) is met and internal clock signal CLK is reset.

(17) FIG. 6 shows signals of a first computer simulation how the clock extraction circuit 18 of FIG. 4 sets and resets the internal clock signal CLK even with a distorted first received signal RS1 and a distorted second received signal RS2. The upper time diagram of FIG. 6 shows the voltage U.sub.RS1 of the first received signal RS1 and the voltage U.sub.RS2 of the second received signal RS2, which signals are both distorted, and upper time diagram of FIG. 6 shows the internal clock signal CLK extracted by the clock extraction circuit 18. The middle and lower part of the time diagram of FIG. 6 show the input signals of NAND gates 29 and 30 with the logic equations (U.sub.RS1>U.sub.TH1) and (U.sub.RS2<U.sub.THL) and (U.sub.RS2>U.sub.TH2) and (U.sub.RS1<U.sub.THL) that are used to set or reset the internal clock signal CLK. At time instance t1 the condition (U.sub.RS1>U.sub.TH1) AND (U.sub.RS2<U.sub.THL) is met and internal clock signal CLK is set. At time instance t2 the condition (U.sub.RS2>U.sub.TH2) AND (U.sub.RS1<U.sub.THL) is met and internal clock signal CLK is reset. As can be seen in FIG. 6, there are several distortions of voltages U.sub.RS1 and U.sub.RS2 of the received signals RS1 and RS2, but the internal clock signal CLK is stable and comprises a high quality.

(18) FIG. 7 shows signals of a second computer simulation of a comparison of the internal clock signal CLK extracted by the state of the art clock extraction circuit 16 of FIG. 1 and the inventive clock extraction circuit 18 of FIG. 4. The upper time diagram of FIG. 7 shows the voltage U.sub.RS1 of the first received signal RS1 and the voltage U.sub.RS2 of the second received signal RS2, which signals are both distorted. The middle part of the time diagram of FIG. 7 shows the robust and correct internal clock signal CLK extracted by the inventive clock extraction circuit 18. The lower part of the time diagram of FIG. 7 shows the internal clock signal CLK extracted by the state of the art clock extraction circuit 16 with the only one threshold level U.sub.TH and with several clock fails.

(19) It is furthermore advantageous that receiver 19 comprises a PLL stage 17 connected to the output of the clock extraction stage 18 to improve the quality of the internal clock signal CLK extracted by the inventive clock extraction circuit 18.

(20) RF frequency area mentioned above has to be understood to cover kHz up to GHz frequency areas.