Method for processing a semiconductor device with two closely spaced gates

Abstract

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

Claims

1. A method for processing a semiconductor device comprising two gates separated by a lateral spacing, the method comprising: forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the lateral spacing; forming a gate layer on and around the template structure; removing a part of the gate layer formed on the template structure; forming an etch mask on a portion of a remaining gate layer; etching based on the etch mask the remaining gate layer to form a gate structure including the two gates, wherein the etch mask is aligned to the template structure; and selectively removing the template structure, wherein the lateral spacing between the two gates is formed by removal of the at least one sub-structure of the template structure; and wherein the lateral spacing is 50 nm or less.

2. The method according to claim 1, wherein: the lateral spacing is 30 nm or less.

3. The method according to claim 2, wherein: the template structure is formed by at least one of: electron beam lithography, optical lithography, or extreme ultraviolet lithography.

4. The method according to claim 3, wherein forming the template structure by electron beam lithography comprises printing a shape of the template structure into a negative tone resist by electron beam.

5. The method according to claim 3, wherein forming the template structure comprises: providing a template layer; coating the template layer with a negative tone resist; patterning the negative tone resist by electron beam printing and negative tone development; and etching the template layer using a patterned negative tone resist as a mask.

6. The method according to claim 5, wherein: the negative tone resist comprises a spin on carbon (SOC) layer or a spin on glass (SOG) layer.

7. The method according to claim 1, wherein: the template structure is formed by at least one of: electron beam lithography, optical lithography, or extreme ultraviolet lithography.

8. The method according to claim 1, wherein: the template structure comprises amorphous silicon covered by a hardmask layer.

9. The method according to claim 8, wherein: the hardmask layer comprises at least one of: a Si.sub.3N.sub.4 layer, a SOC/SOG layer stack, or a SiOC/Advanced Patterning Film (APF) layer stack.

10. The method according to claim 1, wherein: the part of the gate layer (3) formed on the template structure (1) is removed by chemical mechanical polishing, CMP.

11. The method according to claim 10, wherein: the template structure comprises amorphous silicon covered by a hardmask layer, the hardmask layer comprises at least one of: a Si.sub.3N.sub.4 layer, a SOC/SOG layer stack, or a SiOC/Advanced Patterning Film (APF) layer stack, and the hardmask layer serves as an etch stop for the CMP.

12. The method according to claim 11, wherein: patterning a remaining gate layer into the gate structure comprises etching the gate layer, wherein the hardmask layer serves as an etch stop for the gate layer etching.

13. The method according to claim 1, wherein: the template structure comprises amorphous silicon covered by a hardmask layer, the hardmask layer comprises at least one of: a Si.sub.3N.sub.4 layer, a SOC/SOG layer stack, or a SiOC/Advanced Patterning Film (APF) layer stack, the hardmask layer comprises at least one of: a Si.sub.3N.sub.4 layer, a SOC/SOG layer stack, or a SiOC/Advanced Patterning Film (APF) layer stack, and patterning a remaining gate layer into the gate structure comprises etching the gate layer, wherein the hardmask layer serves as an etch stop for the gate layer etching.

14. The method according to claim 1, wherein: the gate layer comprises titanium nitride.

15. The method according to claim 1, wherein: the template structure is removed by wet etching using a hot phosphoric acid, or is removed by selective dry etching.

16. The method according to claim 1, wherein: the etch mask comprises a spin on carbon (SOC) layer and a spin on glass (SOG) layer.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The above, as well as additional features, will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

(2) FIG. 1 shows two gates of a semiconductor device spaced close to each other.

(3) FIG. 2 illustrates steps of a method for forming a semiconductor device, in accordance with an example embodiment.

(4) FIG. 3 illustrates further steps of the method, in accordance with an example embodiment.

(5) FIG. 4 illustrates a further step of the method, in accordance with an example embodiment.

(6) FIG. 5 illustrates a further step of the method, in accordance with an example embodiment.

(7) FIG. 6 shows steps of a detailed method for forming a semiconductor device, in accordance with an example embodiment.

(8) FIG. 7 shows further steps of the detailed method, in accordance with an example embodiment.

(9) FIG. 8 illustrates critical structural features of gates of a semiconductor device, in accordance with an example embodiment.

(10) FIG. 9 shows a semiconductor device, in accordance with an example embodiment.

(11) All the figures are schematic, not necessarily to scale, and generally only show parts that are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

(12) Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout. Further. in the claims as well as in the description, the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality.

(13) FIG. 2-FIG. 5 show a method 20 according to an embodiment. In particular, steps 21-25 of the method 20 are illustrated. The method 20 is suitable for processing a semiconductor device 90 (e.g., see FIG. 9), wherein the semiconductor device 90 comprises at least two gates 41 and 43 (e.g., see FIG. 4 or FIG. 9) separated by a spacing 4a (see FIG. 5).

(14) FIG. 2 shows a step 21 of the method 20. In particular, in step 21, a template structure 1 is formed. The template structure 1 includes at least one sub-structure 2a that has a dimension less than a CD. For instance, in an example, the CD is 50 nm or less. In another example, the CD is 30 nm or less.

(15) The particular template structure 1 shown in FIG. 2 is merely an example. This template structure 1 comprises two sub-structures 2a, which are on the order of 5-30 nm. Further, the example template structure 1 comprises a second sub-structure 2b, which has a width of around 50 nm. The example template structure 1 further comprises a plurality of gaps 2c, each of which has a gap width of 30 nm. This example template structure 1 is suitable to process a spin-qubit semiconductor device 90, as shown in FIG. 9. However, other template structures 1 for processing other types of semiconductor devices can likewise be used to implement the method 20.

(16) The template structure 1 may also be referred to as a G0 layer, which is formed prior to a gate layer 3 (see FIG. 3), which may be referred to as a G1 layer. The template structure 1 can be printed by a NTD resist, which makes electron beam lithography feasible for obtaining the particular shape of the template structure 1. That is, the template structure 1, in particular the sub-structures 2a, 2b and the gaps 2c, can be printed by an electron beam into the NTD resist, which may then be developed and etched, or the like, to obtain the desired template structure 1 shape.

(17) Structures of critical CD in the gate layer 3 can be defined by the template structure 1. The template structure 1 may comprise amorphous silicon, Si.sub.3N.sub.4, a SOC/SOG layer stack, and/or a SiOC/APF layer stack.

(18) FIG. 3 shows steps 22 and 23 of the method 20. In particular, in step 22, a gate layer 3 (e.g., the G1 layer) is formed on and around the template structure 1. Then, in step 23, the part of the gate layer 3 formed on the template structure 1 is removed. FIG. 3 shows the intermediate structure after step 23. The template structure 1 is exposed where the gate layer 3 is removed. The part of the gate layer 3 that is formed on the template structure 1 may be removed by CMP.

(19) FIG. 4 shows step 24 of the method 20. In step 24, the remaining gate layer 3 (i.e., after the removing step 23) is patterned into a gate structure including the at least two gates (i.e., gate electrodes), here example gates 41-45. In FIG. 4, a gate structure comprising, for instance, the two gates 41 and 43, is formed. The substructure 2a of the template structure 1 is arranged between the gates 41 and 43. Further, a gate 40 is formed, which has a width that corresponds to the width of the gap 2c in the template structure 1. Further, gates 42 and 43 are formed and the substructure 2b of the template structure 1 is arranged between these gates 42 and 43. The gates 44 and 45 may be like the gates 40 and 41.

(20) The patterning of the gate layer 3 may be carried out by lithography, and in an example, by optical lithography, i.e., using a light field. The patterning of the gate layer 3 does not involve patterning of CDs (all structures with CD or less are fabricated by the steps of method 20 using the template structure 1). The patterning of the gate layer 3 may be self-aligned on the template structure 1. The patterning of the gate layer 3 may comprise etching of the gate layer 3, wherein the gate layer etch may be selective to the material of the template structure 1, i.e., the template structure 1 may act as an etch stop for the gate layer etch, i.e., withstands the gate layer etch.

(21) FIG. 5 shows step 25 of the method 20. In particular, in step 25, the template structure 1 is selectively removed. It can be seen that removing the template structure 1 forms spacings in the gate layer 3. For instance, the spacing 4a is formed between the two gates 41 and 43 due to the removal of the sub-structure 2a. Further, the spacing 4b is formed between the gates 42 and 43 due to the removal of the sub-structure 2b. Thus, the method 20 facilitates structuring gates with very small spacings, i.e., equal to or below the CD, in a simple manner and with high reliability.

(22) FIG. 6a-FIG. 7d show a specific method according to an embodiment, which builds on the method 20 shown in FIG. 2-FIG. 5.

(23) FIG. 6a shows a layer structure that may be used to form the template structure 1 by lithography. In particular, the layer structure comprises a substrate 7 (e.g., silicon), an oxide layer 8 (e.g., silicon oxide), a template layer 1a, 1b, and a NTD resist 6a, 6b. The template layer 1a, 1b may comprise amorphous silicon 1b covered by a hardmask layer 1a. The hardmask layer 1a may comprise a Si.sub.3N.sub.4 layer, a SOC/SOG layer stack, or a SiOC/APF layer stack. The NTD resist 6a, 6b may comprise a SOC layer 6a and a SOG layer 6b. The NTD resist 6a, 6b may coat the template layer 1a, 1b.

(24) The NTD resist 6a, 6b may then be patterned by electron beam printing and NTD. Notably, in case of such electron beam lithography, the SOC/SOG structure of the NTD resist is beneficial. If optical lithography or extreme ultraviolet lithography would be used instead, the NTD resist 6a, 6b may be formed by different, suitable layers.

(25) FIG. 6b then shows the patterning of the template layer 1a, 1b into the template structure 1, i.e., corresponds to step 21. In particular, the patterning may comprise etching the template layer 1a, 1b using the patterned negative tone resist 6a, 6b as a mask to form the template structure 1. For instance, SOC/SOG may be etched first, followed by etching the hardmask layer 1a and the amorphous silicon 1b. A thickness of the hardmask layer 1a and amorphous silicon 1b may be selected to optimize the etching. The etching of the hardmask layer 1a and amorphous silicon may be selected to the oxide layer 8, i.e., the oxide layer 8 may act as an etch stop.

(26) FIG. 6c shows the formation of the gate layer 3 on and around the template structure 1, i.e., corresponds to step 22. In particular, the gate layer 3 (e.g., TiN) may be deposited onto and surrounding the template structure 1. The gate layer 3 is deposited to be thicker (higher in FIG. 6) as the template structure 1.

(27) FIG. 6d then shows the removal of the part of the gate layer 3 formed on the template structure 1, which corresponds to step 23. To this end, CMP can be used on the gate layer 3 material (e.g., TiN). The hardmask layer 1a (e.g., Si.sub.3N.sub.4) may thereby serve as an etch stop for the CMP. The template structure 1 surface is thereby exposed. The gate layer 3 and template structure 1 may form a common planar surface.

(28) FIGS. 7a and 7b show patterning the gate layer 3 into a gate structure, thus corresponding to step 24. In particular, FIG. 7a shows a lithography of the gate layer 3. To this end, a resist comprising SOC and SOG may be coated onto the gate layer 3 and template structure 1, and patterned into an etch mask.

(29) FIG. 7b shows etching the gate layer 3 using the etch mask. Further, in order to preserve the template structure 1, the hardmask layer 1a of the template structure may not be affected by the gate layer 3 etch, and also the oxide layer 8 may serve as an etch stop.

(30) FIG. 7c shows removing the template structure 3, and thus corresponds to step 25. By removing the template structure 1, the spacings between the gate structure are formed, e.g., the spacings 4a and 4b shown in FIG. 4. The template structure 1 may be selectively removed by wet etching using a hot phosphoric acid, or by selective dry etching.

(31) FIG. 7d is optional and shows the deposition of a gate dielectric 10 (e.g., silicon oxide, in a range of 5-10 nm) onto the gate structure.

(32) FIG. 8 shows a resulting gate structure (structured gate layer 3) for a semiconductor device 90, which is shown in FIG. 9. The semiconductor device 90 is fabricated by using the method 20. The semiconductor device 90 of FIG. 9 comprises two SETs, which are coupled to a string of QDs. The gate structure of FIG. 8 shows that two gates 40 and 41 are formed for a first SET, and two gates 44 and 45 are formed for a second SET. Further, two confinement gates 42 and 43 are formed for defining the string of QDs.

(33) A spacing 4a between a gate 41 of a SET and a confinement gate 43 is in the range of 30 nm or smaller (the same holds for the tip-to-tip distances of the other SET gates 40, 41, 44, 45 to the respective close confinement gate 42, 43). That is, the spacing 4a (formed by removing the sub-structure 2a) separates a gate 41 of the SET from a confinement gate 43. Further, a spacing 4b between the two confinement gates 42 and 43 is in the range of 50 nm or smaller. That is, the two confinement gates 42 and 43 are separated by the second spacing 4b (e.g., formed by removing the second sub-structure 2b). Further, a gate length 4c of the SET gate 40 (and each other SET gate 41, 44, 45) may be on the order of 30 nm (defined by the width of the respective gate electrode, and initially by the gap 2c).

(34) As described, the method 20 facilitates fabricating a semiconductor device 90. In particular, the method 20 facilitates the fabrication of a semiconductor device having, in an example, a tunable tip-to-tip spacing of 5-50 nm, and in another example, a tunable tip-to-tip spacing of 5-30 nm. Further optimization is feasible to achieve tip-to-tip spacings below 5 nm gaps. In addition, the method 20 reduces the charge noise in the semiconductor device 90 by reducing the number of gate layers (and by consequence gate dielectrics). Further, the patterning of the gate layer 3 can be self-aligned on the template structure 1, leading to a simpler process. Furthermore, the patterning of the gate layer 3 into the gate structure can be simplified and less critical.

(35) While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.