Polarization-engineered heterogeneous semiconductor heterostructures

Abstract

Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (In.sub.xAl.sub.1-xN), In.sub.xGa.sub.1-xN, Al.sub.xGa.sub.1-xN, In.sub.xAl.sub.yGa.sub.1-x-yN, where (0<x1, 0<y1, 0<x+y1).

Claims

1. A method for making a polarization-engineered semiconductor device, the method including the steps of: providing a first semiconductor material layer having a corresponding first polarity, first crystallographic orientation, and first spontaneous polarization constant indicative of a spontaneous polarization of the first semiconductor material layer; providing a second semiconductor material layer different from the first semiconductor material layer, the second semiconductor material layer having a corresponding second polarity, second crystallographic orientation, and second spontaneous polarization constant indicative of a spontaneous polarization of the second semiconductor material layer; and directly bonding a bonding surface of the first semiconductor material layer to a bonding surface of the second semiconductor material layer without use of any interfacial bonding materials; wherein a difference between the spontaneous polarization of the first semiconductor material layer and the spontaneous polarization of the second semiconductor material layer is indicative of the formation of a corresponding two-dimensional electron gas (2DEG) or a two dimensional hole gas (2DHG) at an interface between the bonding surface of the first semiconductor material layer and the bonding surface of the second semiconductor material layer; and wherein the first semiconductor material layer, the second semiconductor material layer, a crystallographic orientation of the bonding surface of the first semiconductor material layer relative to a direction of the polarity of the first semiconductor material layer, and a crystallographic orientation of the bonding surface of the second semiconductor material layer relative to a direction of the polarity of the second semiconductor material layer are selected to produce a predetermined 2DEG or 2DHG at the interface between the bonding surface of the first semiconductor material layer and the bonding surface of the second semiconductor material layer.

2. The method according to claim 1, further including the steps of: polishing exposed surfaces of the first and second semiconductor material layers to a root-mean-square (RMS) roughness of less than 0.5 nm, thereby generating polished surfaces of the first and second semiconductor material layers; cleaning the polished surfaces of the first and second semiconductor material layers to remove contaminants and/or particles from the polished surfaces, thereby generating polished and cleaned surfaces of the first and second semiconductor material layers; and activating the polished and cleaned surfaces of the first and second semiconductor material layers so that the first and second semiconductor materials layers are attracted to one another.

3. The method according to claim 1, wherein the crystallographic orientation of the bonding surface of the first semiconductor material layer is opposite the direction of the polarity of the first semiconductor material layer and the crystallographic orientation of the bonding surface of the second semiconductor material layer is in the direction of the polarity of the second semiconductor material layer; wherein a predetermined 2DEG is produced at the interface between the bonding layers of the first and second semiconductor material layers.

4. The method according to claim 3, wherein the first semiconductor material layer is Ga-polar GaN and the second semiconductor material layer is N-polar AlN; and wherein an N-face of the Ga-polar GaN is bonded to an N-face of the AlN-polar AlN so as to produce a predetermined 2DEG at the interface between the GaN and the AlN material layers.

5. The method according to claim 1, wherein the crystallographic orientation of the bonding surface of the first semiconductor material layer is in the direction of the polarity of the first semiconductor material layer and the crystallographic orientation of the bonding surface of the second semiconductor material layer is in the direction of the polarity of the second semiconductor material layer; and wherein a predetermined 2DEG is produced at the interface between the bonding surfaces of the first and second semiconductor material layers.

6. The method according to claim 5, wherein the first semiconductor material layer is N-polar GaN and the second semiconductor material layer is N-polar AlN; and wherein a Ga-face of the N-polar GaN is bonded to an N-face of the N-polar AlN so as to produce a predetermined 2DEG at the interface between the GaN and the AlN material layers.

7. The method according to claim 1, wherein the crystallographic orientation of the bonding surface of the first semiconductor material layer is opposite the direction of the polarity of the first semiconductor material layer and the crystallographic orientation of the bonding surface of the second semiconductor material layer is opposite the direction of the polarity of the second semiconductor material layer; and wherein a predetermined 2DHG is produced at the interface between the bonding layers of the first and second semiconductor material layers.

8. The method according to claim 7, wherein the first semiconductor material layer is Ga-polar GaN and the second semiconductor material layer is Al-polar AlN; and wherein an N-face of the Ga-polar GaN is bonded to an Al-face of the Al-polar AlN so as to produce a predetermined 2DHG at the interface between the GaN and the AlN material layers.

9. The method according to claim 1, wherein the crystallographic orientation of the bonding surface of the first semiconductor material layer is in the direction of the polarity of the first semiconductor material layer and the crystallographic orientation of the bonding surface of the second semiconductor material layer is opposite the direction of the polarity of the second semiconductor material layer; wherein a predetermined 2DHG is produced at the interface between the bonding layers of the first and second semiconductor material layers.

10. The method according to claim 8, wherein the first semiconductor material layer is N-polar GaN and the second semiconductor material layer is Al-polar AlN; and wherein a G-face of the N-polar GaN is bonded to an Al-face of the Al-polar AlN so as to produce a predetermined 2DHG at the interface between the GaN and the AlN material layers.

11. The method according to claim 1, wherein at least one of the first and second semiconductor material layers is a III-nitride material.

12. The method according to claim 1, wherein at least one of the first and second semiconductor material layers is InN, AlN, or GaN.

13. The method according to claim 1, wherein at least one of the first and second semiconductor material layers is a binary, ternary, or quaternary alloy incorporating N-polar, In-polar, Al-polar, or Ga-polar materials having In, Al, or Ga in a crystal lattice.

14. The semiconductor device according to claim 1, wherein at least one of the first and second semiconductor material layers is (Sc, B, Al, In, Ga) N, epsilon-phase (Al,In) Ga2O3, 2HSiC, ZnO, BeO, InN, LiNbO3, LaA1O3, or SrTiO3.

15. The method according to claim 1, wherein at least one of the first and second semiconductor material layers is an epitaxial material layer.

16. The method according to claim 1, wherein the device is an AlN/GaN HEMT comprising a thin AlN layer disposed on an upper surface of a GaN layer.

17. The method according to claim 1, wherein the device is a GaN/AlN high electron mobility transistor (HEMT) comprising a thin GaN layer disposed on an upper surface of an AlN layer.

18. The method according to claim 1, wherein both the first and second semiconductor material layers are strain-relaxed.

19. The method according to claim 1, wherein one of the first and second semiconductor material layers is a non-polar material.

20. The method according to claim 1, wherein at least one of the first and second semiconductor material layers is strained to increase the polarization magnitude defined by a piezoelectric polarization of the strained material layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A-1C illustrate aspects of the crystalline quality of AlN films formed on sapphire substrates.

(2) FIGS. 2A-2E illustrate aspects of the effect of laser lift-off and transfer of nitride-based heterostructures from one substrate to another.

(3) FIGS. 3A-3C illustrate aspects of chemical-mechanical polishing of GaN and AlN films on the RMS roughness of the film surface.

(4) FIGS. 4A-4C illustrate aspects of the effects of bonding on nitride-based heterostructures.

(5) FIGS. 5A-5C illustrate aspects of the effect of bonding of GaAs to GaAs and bonding of GaAs to InP.

(6) FIGS. 6A-6B further illustrate aspects of bonded nitride-based heterostructures.

(7) FIGS. 7A-7B illustrate aspects of the polarity and performance of a first exemplary embodiment of an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with the present invention.

(8) FIGS. 8A-8B illustrate aspects of the polarity and performance of a second exemplary embodiment of an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with the present invention.

(9) FIGS. 9A-9B illustrate aspects of the polarity and performance of a third exemplary embodiment of an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with the present invention.

(10) FIGS. 10A-10B illustrate aspects of the polarity and performance of a fourth exemplary embodiment of an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with the present invention.

(11) FIG. 11 is a block schematic illustrating an exemplary AlN/GaN HEMT having an embedded 2DEG or 2DHG in accordance with the present invention.

(12) FIG. 12 is a block schematic illustrating an exemplary process flow in a method for fabricating a GaN/AlN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with the first embodiment of the present invention.

(13) FIG. 13 is a block schematic illustrating an exemplary process flow in a method for fabricating a GaN/AlN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with the second embodiment of the present invention.

(14) FIG. 14 is a block schematic illustrating an exemplary process flow in a method for fabricating a GaN/AlN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with the third embodiment of the present invention.

(15) FIG. 15 is a block schematic illustrating an exemplary process flow in a method for fabricating a GaN/AlN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with the fourth embodiment of the present invention.

(16) FIG. 16 is a block schematic illustrating an exemplary process flow in a method for fabricating an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with another exemplary embodiment of the present invention.

(17) FIG. 17 is a block schematic illustrating an exemplary process flow in a method for fabricating an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DEG formed in accordance with another exemplary embodiment of the present invention.

(18) FIG. 18 is a block schematic illustrating an exemplary process flow in a method for fabricating an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with another exemplary embodiment of the present invention.

(19) FIG. 19 is a block schematic illustrating an exemplary process flow in a method for fabricating an AlN/GaN heterostructure having strain-relaxed bonded interfaces and a 2DHG formed in accordance with another exemplary embodiment of the present invention.

DETAILED DESCRIPTION

(20) The aspects and features of the present invention summarized above can be embodied in various forms. The following description shows, by way of illustration, combinations and configurations in which the aspects and features can be put into practice. It is understood that the described aspects, features, and/or embodiments are merely examples, and that one skilled in the art may utilize other aspects, features, and/or embodiments or make structural and functional modifications without departing from the scope of the present disclosure.

(21) For example, although the present disclosure and FIGURES are presented herein in the context of embodiments of GaN/AlN-based heterostructures, one skilled in the art will readily recognize that other embodiments may include one or more suitable materials such as binary ternary, or quaternary Sc, B, In, Al, or Ga-nitride alloys incorporating N-polar, In-polar, Al-polar, or Ga-polar materials having In, Al, or Ga in the crystal lattice, e.g., (In.sub.xAl.sub.1-xN), In.sub.xGa.sub.1-xN, Al.sub.xGa.sub.1-xN, In.sub.xAl.sub.yGa.sub.1-x-yN, where (0<x1, 0<y1, 0<x+y1). Incorporation of Al causes the energy gap to increase; incorporation of In causes the energy gap to decrease. Heterostructures in accordance with the present invention can also include other suitable materials that exhibit spontaneous polarization or can form a 2DEG or 2DHG, such as ZnO, BeO, InN, LiNbO.sub.3. See F. Bernardini et al, Spontaneous polarization and piezoelectric constants of III-V nitrides, Phys. Rev. B 56, R10024(R); W. Troy et al, Spontaneous Polarization Calculations in Wurtzite II-Oxides, III-Nitrides, and SiC Polytypes through Net Dipole Moments and the Effects of Nanoscale Layering, Nanomaterials 11, no. 8: 1956 (2021); S. B. Cho et al, Epitaxial engineering of polar -Ga.sub.2O.sub.3 for tunable two-dimensional electron gas at the heterointerface, Appl. Phys. Lett. 112, 162101 (2018); P. Ranga et al, Highly tunable, polarization-engineered two-dimensional electron gas in -AlGaO3/-Ga2O3 heterostructures, Applied Physics Express 13, 061009 (2020); and W. Li et al, Two-dimensional carrier gas at complex oxide interfaces: Control of functionality, Journal of Applied Physics 130, 024103 (2021). Other materials that can be used include epsilon-phase (Al,In)Ga.sub.2O.sub.3, 2HSiC, and LaAlO.sub.3, where structures such as LaAlO.sub.3/SrTiO.sub.3 heterojunctions formed from such materials can lead to the formation of a 2DEG and/or a 2DHG at their interface, and oxides such as BaTiO.sub.3 and PbTiO.sub.3. See G. Singh-Bhalla, et al, Built-in and induced polarization across LaAlO.sub.3/SrTiO.sub.3 heterojunctions, Nature Phys. 7, 80-86 (2011); and M. Noor-A-Alam, et al., Ferroelectricity and Large Piezoelectric Response of AlN/ScN Superlattice, ACS Applied Materials & Interfaces 2019 11 (22), 20482-20490. In still other embodiments, one of the materials used in the heterostructure may be non-polar, i.e., have a polarity at or near zero. These and any other suitable materials, heterostructures formed therefrom, and methods for forming such heterostructures in accordance with the spirit of the present disclosure are deemed to be within the scope of the present invention.

(22) The purpose of the proposed invention is to dramatically increase the power density of microwave devices via a new approach to heterostructure synthesis to simultaneously achieve high breakdown voltage, high carrier density and high carrier mobility/velocity as well as overcoming current thermal limitations. The disclosed concept, in this embodiment for lateral transport applications, gives tremendous flexibility to microwave device designers by eliminating the restraint of the epitaxial barrier layer critical thickness and all the aforementioned challenges it presents. Other devices that may benefit from the present invention include power switching transistors, power rectifiers, and other high power semiconductor devices.

(23) Prior examples of the thin AlN/GaN heterojunction have shown very high sheet charge and good mobility but suffered low breakdown voltage due to the limited thickness of the AlN barrier. See A. M. Dabiran et al, Very high channel conductivity in low-defect AlN/GaN high electron mobility transistor structures, Appl. Phys. Lett. 93, 082111 (2008). In accordance with the present invention, device designers can leverage arbitrary layer thicknesses and optimize the device structure for the application.

(24) As noted above, every nitride-based high electron mobility transistor (HEMT) device currently in use consists of a thin, strained heteroepitaxial barrier expected to generate sufficient spontaneous and piezoelectric polarization to support the formation of a two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) channel having high carrier density and high carrier mobility in such devices, with such devices having high breakdown voltage and high reliability while simultaneously being constrained by high piezoelectric stress, high electric field, and high temperature near the surface caused by the presence of the barrier layer. The present invention gives tremendous flexibility to microwave device designers by eliminating the restraint of the epitaxial barrier layer critical thickness and all the aforementioned challenges it presents. Although the present invention is often described herein in the context of embodiments for lateral transport applications, one skilled in the art will readily understand that the structure and method described herein can be used to fabricate electronic devices suitable for numerous other applications.

(25) The present invention builds on the work of the inventors described above regarding crystal growth of nitride semiconductors, particularly AlN and GaN, laser lift-off of such nitride semiconductors from their growth substrates and bonding thereof to new substrates, and wafer bonding of nitride semiconductors to one another to provide a method for forming heterogeneous nitride heterostructures having engineered polarities that can provide significant improvement in breakdown voltage, thermal management, and carrier density/mobility over existing semiconductor structures.

(26) The present invention provides a method for forming a nitride-based heterostructure by means of atomic layer bonding without the use of any interfacial layers as has previously been required for bond formation.

(27) Formation of III-N heterostructures via the traditional epitaxial growth approach inherently leads to piezoelectric polarization due to lattice mismatch in the III-N layers. Although the presence of this polarization increases charge density, it also introduces reliability concerns at high electric fields due to defects that may form under piezoelectrically induced stress. See J. A. del Alamo et al, GaN HEMT reliability, Microelectronics Reliability 49, 1200 (2009).

(28) The approach in accordance with the present invention avoids the lattice mismatch issue altogether, paving the way for the formation of robust, highly reliable, high power III-N heterostructures.

(29) The absence of piezoelectric polarization is not a detriment to this invention because strong spontaneous polarizations (P.sub.SP) in III-nitride layers results in high sheet charge. Thicker layers will also result in less surface-sensitive channel and reduced need for passivation as the channel is further isolated from the heterostructure surface.

(30) The present invention thus enables the formation of direct bonded AlN/GaN HFET heterostructures having a much higher breakdown voltage leading to increase in power density at X-band. See S. H. Sohel et al, X-Band Power and Linearity Performance of Compositionally Graded AlGaN Channel Transistors, IEEE Electron Device Letters, Vol. 39, No. 12, December 2018. See also X. Luo et al, Scaling and high-frequency performance of AlN/GaN HEMTs, 2011 IEEE International Symposium on Radio-Frequency Integration Technology, 2011, pp. 209-212.

(31) As described in more detail below, the overall bonding approach used in accordance with the present invention uses direct wafer bonding to join two III-nitride materials. In many cases, bonding can be accomplished at low temperatures, low bonding force that allow such bonding to be conducted on a wafer-scale.

(32) Direct wafer bonding as used in accordance with the present invention requires that the surfaces of the two wafers be smooth and flat, with a root mean square (RMS) roughness of less than 0.5, and be exceptionally clean and free of contaminants and particles. The wafer surfaces typically also must be activated such that the wafers are attracted to each other. This can be done by chemical treatments that leave active species of e.g., OH.sup. or H.sup.+ bound to the surface. Such species produce a van der Waal bond that attracts the wafer surfaces and closes the gap.

(33) Following wafer bonding, thermal annealing is required to drive out the reaction gases and produce covalent bonds at the bond interface. Other methods of activation, which result in immediate covalent bonding, include exposure to an energetic plasma of e.g., nitrogen, argon, ammonia, or chlorine gases. Exposure to a plasma creates dangling bonds on the surface that are attracted to dangling bonds on the opposite surface.

(34) Joining these two activated surfaces results in immediate covalent bonding at room temperature. The plasma energy and duration of exposure must be controlled to avoid substantial damage to the wafer surfaces. Some level of damage can be removed by thermal annealing following bonding. Another approach to surface activation is the use of fast atom beams of e.g., argon ion beams. Similar to plasma exposure, conditions must be controlled as to avoid substantial damage. In the case of plasma or fast atom beam, activation and wafer bonding could take place in a suitable vacuum chamber such that the wafer surfaces are not exposed to air after activation and prior to bonding.

(35) As noted above, the present invention builds on the success of the inventors' previous approaches regarding bonding of semiconductor structures, and uses direct bonding of GaN to AlN without a dielectric interlayer to exploit the spontaneous polarization of both GaN and AlN and thus benefits from intimate contact between the GaN and AlN. Using this approach, the heterogeneous nitride heterostructures produced in accordance with the present invention can leverage the electronic properties of the combined polarization at the interface to produce a robust heterostructure with high carrier densities.

(36) The key to the disclosed invention is the use of direct wafer bonding of strain-relaxed AlN and GaN layers to achieve a spontaneous-polarization induced charge density 2-3 times that in conventional AlGaN/GaN HEMTs. As shown in Table I of O. Ambacher et al, Two dimensional electron gases induced by spontaneous and piezoelectric polarization in undoped and doped AlGaN/GaN heterostructures, J. Appl. Phys., Vol. 87, No. 1, pp. 334-344 (2000), the spontaneous and piezoelectric polarization constants of AlN are nearly three times as high as those of GaN; specifically, the spontaneous polarization constants of GaN and AlN are listed as 0.029 and 0.081 C/m.sup.2, respectively. This negative sign of the spontaneous polarization is for a cation (Ga or Al)-polar crystal orientated along the [0001] axis, whereas the spontaneous polarization constants of an N-polar GaN or AlN, orientated along the [000-1] axis, would be positive, i.e., +0.029 and +0.081 C/m.sup.2, respectively.

(37) To maintain charge neutrality, charge (negative electrons or positive holes) of the opposite sign of the polarization charge will accumulate at the interface. The signs of the GaN and AlN polarization charges are both negative for cation (Ga or Al)-polar material and both positive for N-polar material. Thus, the largest difference in spontaneous polarization occurs at the interface of GaN and AlN materials of the opposite polar orientation. The net spontaneous polarization charge and the resulting formation of a 2DEG or a 2DHG at the interface of GaN and AlN is determined by the difference in the spontaneous polarization constants P.sub.SP of the two orientation-dependent materials, with a net positive difference being indicative of the formation of a 2DEG and a net negative difference being indicative of a 2DHG.

(38) FIGS. 7A/7B, 8A/8B, 9A/9B, and 10A/10B illustrate aspects of four different exemplary embodiments of a GaN/AlN HEMT formed by direct bonding of polar GaN and polar AlN in accordance with the present invention. As shown in these FIGURES, depending on the polar orientation of the initial GaN and AlN layers, the spontaneous polarization P.sub.SP induced by the bonding of these material will produce a 2DEG or a 2DHG at the bonded interface between them. In accordance with the present invention, the semiconductor materials and the orientation of the bonded surfaces of the semiconductor materials relative to their respective polarity can be selected to produce a predetermined 2DEG or 2DHG at the interface between the bonded first and second semiconductor material layers.

(39) Thus, in a first exemplary embodiment, aspects of which are shown by the block schematic in FIG. 7A, the N-face of strain-relaxed [0001] Ga-polar oriented GaN is bonded to the N-face of strain-relaxed [000-1] N-polar oriented AlN. This bonding of Ga-polar GaN on N-polar AlN produces a heterostructure having GaN and AlN layers whose spontaneous polarizations P.sub.SP are 0.029 and +0.081 C/m.sup.2, respectively. In this case, as shown by the plot of simulated energy-band diagrams in FIG. 7B, the difference in spontaneous polarizations P.sub.SP for [0001] Ga-polar GaN on [000-1] N-polar AlN is positive, i.e., ((+0.081)(0.029)), reflecting the formation of a two-dimensional electron gas (2DEG) having an electron concentration as high as 10.sup.20 cm.sup.3 at the GaN/AlN interface. This high electron concentration makes devices having this GaN/AlN structure particularly suitable for use in HEMTs and HFETs.

(40) In a second exemplary embodiment, aspects of which are shown by the block schematic in FIG. 8A, the Ga-face of strain-relaxed [000-1] N-polar GaN is bonded to the N-face of strain-relaxed [000-1] N-polar AlN. As with the first exemplary embodiment shown in FIGS. 7A/7B, in this case the difference in the spontaneous polarization constants of the GaN and AlN layers also is positive, i.e., ((+0.081)(+0.029)), reflecting the formation of a two-dimensional electron gas (2DEG) at the GaN/AlN interface. As shown by the plot in FIG. 8B, the 2DEG in this configuration also has an electron concentration as high as 10.sup.20 cm.sup.3, making devices having this GaN/AlN structure also particularly suitable for use in HEMTs and HFETs.

(41) In a third exemplary embodiment, aspects of which are shown by the block schematic in FIG. 9A, the N-face of a strain-relaxed [0001] Ga-polar GaN layer is bonded to the Al-face of a strain-relaxed [0001] Al-polar AlN layer. The spontaneous polarization constants P.sub.SP of the GaN and AlN layers as described above, but in this case their difference is negative, i.e., ((0.081)(0.029)), reflecting the formation of a two-dimensional hole gas (2DHG) at the bonding interface between them. As shown in the plot in FIG. 9B, this 2DHG at the GaN/AlN interface has a hole concentration as high as 10.sup.20 cm.sup.3, making devices having this GaN/AlN structure particularly suitable for applications in which hole-based charge transport is required, particularly in complementary metal-oxide-semiconductor (CMOS) devices.

(42) Finally, in a fourth exemplary embodiment, aspects of which are shown by the block schematic in FIG. 10A, the Ga-face of a strain-relaxed [000-1] N-polar GaN layer is bonded to the Al-face of a strain-relaxed [0001] Al-polar AlN layer. In this case as in the third embodiment described above, the difference in spontaneous polarization P.sub.SP constants of the GaN and AlN layers, i.e., ((0.081)(+0.029)) is negative, reflecting the formation of a two-dimensional hole gas (2DHG) at the AlN/GaN interface, as shown by the plot in FIG. 10B. As with the GaN/AlN heterostructures in accordance with the third embodiment described above, the hole concentration in this 2DHG is as high as 10.sup.20 cm.sup.3, making devices having the GaN/AlN structure in accordance with this embodiment also particularly suitable for applications in which hole-based charge transport is required, particularly in CMOS devices.

(43) In the structures described above, the GaN material layer is on top such that the electrical connection is made via the GaN layer, as illustrated by the block schematic in FIG. 11. Optionally, a regrown or implanted contact process can be implemented to further reduce contact resistance.

(44) In addition to these embodiments, structures that can be formed by direct bonding of AlN to GaN include structures in which the AlN is on top to form AlN/GaN HEMTs. As described below, the spontaneous polarization induced in such structures also produces 2DEGs or 2DHGs in a manner similar to that described above with respect to GaN/AlN HEMTs.

(45) The present invention also provides methods for forming the direct-bonded AlN/GaN and GaN/AlN heterostructures described above. As noted above, the method for forming the heterostructures in accordance with the present invention relies on direct bonding of the two material layers, in which the surfaces of the two material layer films are smooth, flat, and free of contaminants and particles, with a root mean square (RMS) roughness of less than 0.5 nm. Typically, the wafer surfaces must be activated such that the wafers are attracted to each other such that joining the two activated surfaces results in immediate covalent bonding at room temperature.

(46) The block schematics in FIGS. 12-15 illustrate exemplary method steps used to form GaN on top GaN/AlN heterostructures in accordance with the four exemplary embodiments described above, while the schematics in FIGS. 16-19 illustrate method steps used in formation of corresponding exemplary AlN on top AlN/GaN heterostructures.

(47) In these FIGURES, except where noted, the method steps shown are the same in each FIGURE, with the reference numbers in each FIGURE following the same numbering scheme except as changed to reflect the FIG. 1n which they are shown. For example, steps 1301a/1301b, 1302, etc., in FIG. 13 are the same as the corresponding steps 1201a/1201b, 1201, etc. shown and described with respect to FIG. 12. For the sake of brevity and to avoid unnecessary duplication, except as necessary to describe the steps and features of the different structures reflected in each FIGURE, the method steps will only be described in detail with respect to FIG. 12 and will not be repeated in the description of the other FIGURES.

(48) The block schematics in FIG. 12 illustrate method steps used to form the exemplary GaN/AlN heterostructure described above with respect to FIGS. 7A and 7B. As shown in FIG. 12, the method starts in steps 1201a with the growth of a Ga-polar GaN layer on a first substrate and in step 1201b with the growth of an N-polar AlN film on a second substrate. As shown in FIG. 12, the Ga-polar GaN layer is relatively thick, typically having a thickness of about 0.5 to about 15 m. The first substrate used for the GaN layer is preferably sapphire, silicon, silicon carbide, or gallium nitride, while the second substrate used for the AlN layer is preferably sapphire, though other substrates for the GaN and the AlN layers can be used as appropriate.

(49) In step 1202, a temporary carrier wafer is applied to the Ga-face of the Ga-polar GaN layer, e.g., using a high-temperature adhesive layer. In step 1203, the first substrate is then removed, e.g., by etching or other suitable means, leaving the N-face of the Ga-polar GaN layer exposed. The exposed faces of the GaN layer and the AlN layer are then polished and cleaned as described above to prepare them for direct bonding to one another, and in step 1204, the N-face of the Ga-polar GaN is directly bonded to the N-face of the N-polar AlN to form the single heterostructure shown in step 1205 having a 2DEG at the bonding interface as a result of the spontaneous polarization that intrinsically occurs within the Ga-polar GaN and the N-polar AlN layers.

(50) Next, in step 1206, the temporary carrier wafer is removed from the top of the GaN/AlN heterostructure to expose the GaN layer so that electrical contact can be made to the structure. Finally, in step 1207, the GaN layer, which typically had an original thickness of, e.g., approximately 0.5-15 m, is thinned, e.g., by chemical mechanical polishing (CMP), to a final thickness of, e.g., approximately 0.1-2 m, so that the 2DEG at the GaN/AlN interface can be more readily accessed.

(51) The block schematics in FIG. 13 illustrate aspects of a method for forming the GaN/AlN heterostructure described above with respect to FIGS. 8A/8B, in which an N-polar GaN layer is directly bonded to an N-polar AlN layer. The steps of this method are the same as those described above with respect to FIG. 12, except that in step 1302 shown in FIG. 13, the temporary carrier wafer is applied to the N-face of the GaN layer and the Ga-face of the GaN is directly bonded to the N-face of the AlN in step 1304 to form a GaN/AlN heterostructure having a 2DEG at the interface between the GaN and the AlN layers.

(52) The block schematics in FIG. 14 illustrate aspects of a method for forming the GaN/AlN heterostructure described above with respect to FIGS. 9A/9B, in which a Ga-polar GaN layer is directly bonded to an Al-polar AlN layer. The steps of this method are the same as those described above with respect to FIG. 12, except that in in step 1404, the N-face of the Ga-polar GaN is directly bonded to the N-face of the AlN to form the GaN/AlN heterostructure. As described above with respect to FIG. 9A/9B, in this case, the GaN/AlN heterostructure has a 2DHG at the interface of the GaN and AlN layers as a result of the spontaneous polarization induced by the direct bonding of the two materials.

(53) Finally, the block schematics in FIG. 15 illustrate aspects of a method for forming the GaN/AlN heterostructure described above with respect to FIGS. 10A/10B, in which an N-polar GaN layer is directly bonded to an Al-polar AlN layer. As with the other method FIGURES noted above, the method steps shown in FIG. 15 are the same as those described above with respect to FIG. 12, except that in in step 1502, the temporary carrier wafer is applied to the N-face of the GaN layer and in step 1504, the Ga-face of the Ga-polar GaN is directly bonded to the Al-face of the AlN to form the GaN/AlN heterostructure. As described above with respect to FIG. 10A/10B, in this case, the GaN/AlN heterostructure has a 2DHG at the interface of the GaN and AlN layers as a result of the spontaneous polarization induced by the direct bonding of the two materials.

(54) As noted above, in addition to the GaN/AlN heterostructures described above, structures that can be formed by directly bonding polar GaN to polar AlN include AlN on top AlN/GaN heterostructures. These structures generally correspond to the structures shown in FIGS. 7-10 above, but with the layers reversed.

(55) The block schematics in FIGS. 16-19 illustrate aspects of the formation of these heterostructures. As with FIGS. 12-15 above, except where noted, the method steps shown are the same in each FIGURE, with the reference numbers in each FIGURE following the same numbering scheme except as changed to reflect the FIG. 1n which they are shown, and the sake of brevity and to avoid unnecessary duplication, except as necessary, the method steps will only be described in detail with respect to FIG. 16 and will not be repeated in the description of the other FIGURES.

(56) Thus, the block schematics in FIG. 16 illustrate aspects of a method for forming a structure in which Al-polar AlN is directly bonded to N-polar GaN. In this case, in step 1601a, a thick (e.g., approximately 0.5-15 m) Al-polar AlN material layer is grown on a substrate and in step 1601b, a thick (e.g., approximately 0.5-15 m) N-polar GaN material layer is grown on a substrate. As with the GaN on top embodiments described above, in most cases, the AlN layer is grown on sapphire, while the GaN layer is grown on sapphire, silicon, silicon carbide, or gallium nitride, although other substrates can be used as appropriate.

(57) In step 1602, a temporary carrier layer, also typically sapphire, is applied to the Al-face of the AlN layer by means of a high-temperature adhesive layer. In step 1603, the initial sapphire substrate is then removed from the AlN layer, e.g. through use of an excimer laser, to expose the N-face of the Al-polar AlN layer.

(58) In step 1604, the exposed N-face of the AlN layer is directly bonded to the N-face of the GaN layer to form a GaN/AlN heterostructure shown at step 1605 in which the AlN layer is on top and a 2DEG is formed at the AlN/GaN interface.

(59) At step 1606, the sapphire temporary carrier layer and adhesive layer are removed to expose the Al-face of the top AlN layer, and finally, at step 1607, the AlN layer is thinned, e.g., by means of chemical mechanical polishing or other appropriate means, so that contact to the 2DEG can be easily accomplished.

(60) The block schematics in FIG. 17 illustrate aspects of a method for forming an AlN/GaN heterostructure in which an Al-polar AlN layer is directly bonded to a Ga-polar GaN layer. The steps of this method are the same as those described above with respect to FIG. 16, except that the Ga-face of the GaN is directly bonded to the N-face of the AlN in step 1704 to form an AlN/GaN heterostructure having a 2DEG at the AlN/GaN interface.

(61) The block schematics in FIG. 18 illustrate aspects of a method for forming an AlN/GaN heterostructure in which an N-polar AlN layer is directly bonded to an N-polar GaN layer. The steps of this method are the same as those described above with respect to FIG. 16, except that the Al-face of the AlN layer is exposed when the sapphire substrate is removed from the N-polar AlN layer such that the Al-face of the AlN layer is directly bonded to the N-face of the GaN in step 1804 to form the AlN/GaN heterostructure shown in step 1805, with the spontaneous polarizations P.sub.SP of the AlN and GaN layers producing a 2DHG at the AlN/GaN interface.

(62) Finally, the block schematics in FIG. 19 illustrate aspects of a method for forming an AlN/GaN heterostructure in which N-polar AlN is directly bonded to Ga-polar GaN. As with the other method FIGURES noted above, the method steps shown in FIG. 19 are the same as those described above with respect to FIG. 16, except that in in step 1902, the sapphire temporary carrier is applied to the N-face of the AlN layer. In step 1903, the sapphire substrate is removed to expose the Al-face of the AlN layer so that the Al-face of the AlN layer is directly bonded to the Ga-face of the GaN layer in step 1904 to form the AlN/GaN heterostructure shown in step 1905, with the spontaneous polarizations P.sub.SP of the AlN and GaN layers producing a 2DHG at the AlN/GaN interface.

(63) Advantages and New Features

(64) The present disclosure describes semiconductor devices that leverage the strong spontaneous polarization of the GaN/AlN heterostructure formed by joining strain-relaxed GaN and AlN epitaxial films by direct wafer bonding along specific crystallographic directions. Bonding the N-polar of AlN with the N-polar of GaN, for example, exhibits the advantage of (1) strong spontaneous polarization to generate a 2DEG charge density estimated to be 3.1713 cm.sup.2 (see Ambacher et al, supra); (2) high electric field capability up to 5 MV/cm (see I. Abid et al, High Lateral Breakdown Voltage in Thin Channel AlGaN/GaN High Electron Mobility Transistors on AlN/Sapphire Templates, Micromachines 2019, 10(10), 690); (3) reduced piezoelectric stress leading to reduced stress-related device failure; (4) thicker AlN barrier with less sensitivity to surface effects easing passivation requirements; and (5) higher composite thermal conductivity approaching that of bulk AlN (see Koh et al, supra).

(65) The spontaneous polarization which generates a high 2DEG charge should lead to more reliable AlN/GaN HEMTs with mobility greater than 1500 cm.sup.2/(Vs), breakdown field approaching 5 MV/cm, and defect density at the heterogeneous heterojunction <110.sup.10 cm.sup.2 for next-generation very high-power devices. Alternate bonding orientations are also quite intriguingfor example, a 2DHG is possible with Al-polar AlN bonded to GaN, which in turn, could potentially enable the development of GaN-based CMOS devices.

(66) Alternatives

(67) Today, every nitride-based high electron mobility transistor (HEMT) device consists of a thin, strained heteroepitaxial barrier expected to generate sufficient spontaneous and piezoelectric polarization to support the 2DEG channel with high density, high mobility, high breakdown voltage, and high reliability, while simultaneously constrained by high piezoelectric stress, high electric field, and high temperature near the surface.

(68) The final device structures in accordance with the present invention will comprise these m-thick layers of the GaN and AlN. Other bulk substrates can be lapped and polished, but the lift-off approach with the sapphire-based structures provides a facile means to transfer layers having m thickness. AlN layers deposited on sapphire exhibit higher thermal conductivity than layers on other bulk substrates, thus improving the heat transfer from the device-active regions. In addition, growth on sapphire provides a more scalable process than for GaN and AlN substrates, (although combinations such as a bulk GaN substrate and an AlN layer on sapphire can readily be incorporated in this approach). Once bonded and thinned on the GaN side, device fabrication follows established HEMT device fabrication protocols, e.g., mesa etch, regrowth of n+ GaN for Ohmic contacts, contact metallization, SiN passivation.

(69) As noted above, other materials that may be used in heterostructures that can produce 2DEG and/or a 2DEG at their interface include binary ternary, or quaternary Sc, B, In, Al, or Ga-nitride alloys incorporating N-polar, In-polar, Al-polar, or Ga-polar materials having In, Al, or Ga in the crystal lattice, e.g., (In.sub.xAl.sub.1-xN), In.sub.xGa.sub.1-xN, Al.sub.xGa.sub.1-xN, In.sub.xAl.sub.yGa.sub.1-x-yN, where (0<x1, 0<y1, 0<x+y1). Other suitable materials may include ZnO, BeO, InN, LiNbO.sub.3, LaAlO.sub.3, and SrTiO.sub.3. Still other materials that can be used include epsilon-phase (Al,In)Ga.sub.2O.sub.3, 2HSiC, and LaAlO.sub.3, where structures such as LaAlO.sub.3/SrTiO.sub.3 heterojunctions formed from such materials can lead to the formation of a 2DEG and/or a 2DHG at their interface, and oxides such as BaTiO.sub.3 and PbTiO.sub.3. In still other embodiments, one of the materials used in the heterostructure may be non-polar, i.e., have a polarity at or near zero.

(70) In other embodiments, multiple heterostructures can be formed on a single carrier substrate, where all of the multiple heterostructures exhibit the production of a 2DEG or a 2DHG, or where one or more of the heterostructures exhibits production of a 2DEG while one or more other heterostructures exhibits production of a 2DHG. In any of these embodiments, the materials used in the various heterostructures may be the same or they may be different, as the various applications to which they are intended may dictate. For example, in some embodiments, one heterostructure may exhibit production of a 2DEG, while another heterostructure situated adjacent thereto exhibits production of a 2DHG; such a configuration of adjoining structures may be particularly useful in devices such as complementary metal-oxide semiconductor (CMOS) devices or other similar multifunctional applications.

(71) Although particular embodiments, aspects, and features have been described and illustrated, one skilled in the art would readily appreciate that the invention described herein is not limited to only those embodiments, aspects, and features but also contemplates any and all modifications and alternative embodiments that are within the spirit and scope of the underlying invention described and claimed herein. The present application contemplates any and all modifications within the spirit and scope of the underlying invention described and claimed herein, and all such modifications and alternative embodiments are deemed to be within the scope and spirit of the present disclosure.