PHOTOVOLTAICS ON SILICON

Abstract

Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.

Claims

1. A structure for use in photonic applications, the structure comprising: a mask layer disposed above a top surface of a substrate and including an opening extending from a top surface of the mask layer to the top surface of the substrate; a crystalline material disposed in the opening; and a photonic device disposed above the crystalline material, the photonic device having an active junction including a surface that extends in a direction substantially away from the top surface of the substrate.

2. The structure of claim 1, wherein the surface of the active junction is substantially perpendicular to the top surface of the substrate.

3. The structure of claim 1, wherein the photonic device includes an active junction having a sidewall surface coupled to a top surface, the sidewall surface of the active junction extending substantially away from the top surface of the substrate.

4. The structure of claim 1, wherein the photonic device includes a plurality of active junctions, each active junction having a surface that extends in a direction substantially away from the top surface of the substrate.

5. The structure of claim 4, wherein the active junction surfaces are substantially perpendicular to the top surface of the substrate.

6. The structure of claim 4, wherein each active junction includes a sidewall surface coupled to a top surface, the sidewall surfaces extending in a direction substantially away from the top surface of the substrate.

7. The structure of claim 4, wherein each active junction includes a portion adjacent the top surface of the mask layer and the mask layer electrically isolates each active junction from the substrate.

8. The structure of claim 1, wherein a portion of the active junction is adjacent the top surface of the mask layer and the mask layer electrically isolates the active junction from the substrate.

9. The structure of claim 1, wherein the crystalline material comprises at least one of a III-V compound, a II-VI compound, or a group IV element or compound.

10. The structure of claim 9, wherein the III-V compound comprises a III-nitride material.

11. The structure of claim 1, wherein the photonic device comprises a photovoltaic device.

12. The structure of claim 1, wherein the photonic device comprises a plurality of multi-junction photovoltaic devices.

13. The structure of claim 1, wherein the photonic device comprises an LED.

14. The structure of claim 1, wherein the photonic device comprises a plurality of LEDs connected in parallel.

15. A structure comprising: a first semiconductor material disposed on a substrate, the first semiconductor material including a sidewall extending away from the substrate; a second semiconductor layer disposed on a portion of the sidewall to define an active device junction region; and a mask layer disposed on the substrate adjacent to a bottom region of the sidewall, the mask layer electrically isolating the second semiconductor layer from the substrate.

16. The structure of claim 15, wherein a surface of the active junction region is substantially perpendicular to a top surface of the substrate.

17. The structure of claim 15, wherein the mask layer comprises a non-crystalline material, a top surface of the substrate comprises a first crystalline material, the first semiconductor material comprises a second crystalline material that is lattice mismatched to the first crystalline material, the second crystalline material being disposed in and above openings of the mask layer.

18. The structure of claim 17, wherein the a first semiconductor material comprises an n-type base layer over the second crystalline material, the n-type base layer extending above a top surface of the mask layer, and wherein the second semiconductor layer comprises is a p-type emitter layer over and contacting the n-type base layer, the p-type emitter layer having a bottom surface contacting the top surface of the mask layer.

19. A structure comprising: a mask layer disposed above a top surface of a substrate, the mask layer comprising a non-crystalline material and having a plurality of openings extending from a top surface of the mask layer to the top surface of the substrate, the top surface of the substrate comprising a first crystalline material, wherein each opening of the plurality of openings is defined by non-crystalline sidewalls having a height h and has a width w and length l along the top surface of the substrate, and the width w is smaller than the length l, and the height h is smaller than half the length l; a second crystalline material disposed in and above the plurality of openings, the second crystalline material being lattice mismatched to the first crystalline material; and a photovoltaic cell disposed above the second crystalline material, the photovoltaic cell comprising active cell junctions above the second crystalline material, each of the active cell junctions being over one of the plurality of openings and over the top surface of the mask layer, each of the active cell junctions having a top surface and lateral sidewall surfaces, the lateral sidewall surfaces being substantially perpendicular to the top surface of the substrate.

20. The structure of claim 19, wherein each of the active cell junctions comprise: an n-type base layer directly over the second crystalline material, the n-type base layer extending above the top surface of the mask layer; and a p-type emitter layer over and contacting the n-type base layer, the p-type emitter layer having a bottom surface contacting the top surface of the mask layer.

Description

BRIEF DESCRIPTION OF FIGURES

[0033] In the drawings, like reference characters generally refer to the same features throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

[0034] FIG. 1a is a schematic cross-sectional view of device formed by selective growth of a semiconductor material on a lattice-mismatched trenched surface by ART in accordance with an embodiment of the invention;

[0035] FIG. 1b is a schematic top view of openings disposed over a top surface of a substrate;

[0036] FIG. 2 is a schematic cross-sectional view of a two junction solar cell module formed after coalescence growth in accordance with another embodiment of the invention;

[0037] FIG. 3 is a schematic cross-sectional view of a one junction solar cell module formed without coalescence growth in accordance with another embodiment of the invention;

[0038] FIG. 4 is a schematic cross-sectional view of a photovoltaic device formed over a coalesced layer in a one-step epitaxy process;

[0039] FIGS. 5a-5c are a schematic cross-sectional views of a photovoltaic device formed over a coalesced layer in a two-step epitaxy process including planarization;

[0040] FIGS. 6a-6b and 7a-7c are schematic cross-sectional views of devices formed over coalesced layers in which a crystalline material includes a material from the same group as a component of a substrate;

[0041] FIGS. 8a-8c and 9a-9d are schematic cross-sectional views illustrating processes combining homo-epitaxial and hetero-epitaxial growth;

[0042] FIG. 10 is a schematic cross-sectional view illustrating a method for forming a virtual wafer by bonding;

[0043] FIGS. 11-13 are schematic cross-sectional views illustrating the formation of arrays of PVDs;

[0044] FIG. 14 is a cross-sectional view illustrating the formation of an array of PVDs on a Si(111) substrate;

[0045] FIGS. 15-17 are schematic cross-sectional views illustrating alternative features that may be incorporated in the structures illustrated in FIGS. 4-14;

[0046] FIGS. 18 and 19 are schematic cross-sectional views illustrating exemplary ART-based dual junction cells; and

[0047] FIG. 20 is a flow chart illustrating a process flow for forming a photovoltaic device by ART.

DETAILED DESCRIPTION

[0048] A significant feature of embodiments of the present invention is the provision of a pathway to overcome the material incompatibility between lattice-mismatched materials, such as III-V compounds formed on a Si substrate. This approach is based on ART technology for selective epitaxy. See, e.g., U.S. patent application Ser. No. 11/436,062.

[0049] Referring to FIGS. 1a and 1b, an insulating material such as SiO.sub.2, is used to define openings, e.g., trenches, above a semiconductor substrate. Semiconductor substrate may include, e.g., silicon. The openings are configured using ART techniques so that when a lattice-mismatched material, e.g., GaAs is epitaxially grown, defects in the lattice-mismatched GaAs layer are trapped in the lower region of the trenches and the GaAs region at the top of the trenches is relatively defect free.

[0050] More specifically, a substrate 10 includes a first crystalline semiconductor material S1. The substrate 10 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. The substrate 10 may include or consist essentially of the first semiconductor material S1, such as a group IV element, e.g., germanium or silicon. In various embodiments, substrate 10 includes or consists essentially of monocrystalline silicon, e.g., (111) silicon or p- or n-type (100) silicon; polycrystalline silicon; or amorphous silicon. In other embodiments, substrate 10 may include or consist essentially of a group IV compound, III-V compound or a II-VI compound.

[0051] A mask layer 35 is formed over the semiconductor substrate 10. The mask layer 35 may include or consist essentially of a non-crystalline material, such as dielectric material, e.g., a nitride of silicon like silicon nitride or an oxide of silicon like silicon dioxide. The mask layer 35 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). As discussed below, the mask layer may have a thickness t.sub.1 corresponding to a desired height h of crystalline material to be deposited in an opening 30, e.g., trench formed through the mask layer. In some embodiments, the thickness t.sub.1 of the mask layer 35 may be selected from a range of, e.g., 25-1000 nm. In a preferred embodiment, the thickness t.sub.1 is 500 nm.

[0052] A mask (not shown), such as a photoresist mask, is formed over the substrate 10 and the mask layer 35. The mask is patterned to expose at least a portion of the underlying mask layer 35. The exposed portion of the mask layer 35 is removed by, e.g., reactive ion etching (RIE) to define an opening 30, e.g., a trench. The opening 30 may be defined by at least one sidewall 25, and may extend to a top surface 15 of the substrate 10. The height h of the sidewall 25 corresponds to the thickness t.sub.1 of the mask layer 35, and may be at least equal to a predetermined distance H from the top surface 15 of the substrate. The height h may be less than about 1 micrometer. In another embodiment, the height h may be greater than about 1 micrometer. The height h may be greater than the width w of the opening. The width w of the opening may be selected from a range of about 100 nanometers to about 1 micrometer, e.g., from a range of about 10 nanometers to about 50 nanometers, or from a range of about 50 nanometers to about 100 nanometers.

[0053] In an embodiment, the opening 30 is a trench that may be substantially rectangular in terms of cross-sectional profile, a top view, or both, and have a width w that is smaller than a length l (not shown) of the trench. For example, the width w of the trench may be less than about 500 nm, e.g., about 10-100 nm, and the length l of the trench may exceed each of w and H. A ratio of the height h of the trench to the width w of the trench 30 may be 0.5, e.g., 1.

[0054] In other embodiments, the opening 30 may define a generally circular shape or a generally rectangular shape on the top surface of the substrate. The opening may define a generally columnar shape. The opening 30 may have a length l and a width w.sub.3, the width being less than or equal to about 1 micrometer. The length may be less than about 1 micrometer, or may be greater than about 1 millimeter. The length may be greater than twice the width, i.e., the width may be less than half the length. The width may be less than one tenth the length.

[0055] The opening 30 may be one of a plurality of openings 30.

[0056] A second crystalline semiconductor material S2, i.e., a crystalline material 40, is formed in the opening 30. The crystalline material 40 may include or consist essentially of a group IV element or compound, a III-V compound, or a II-VI compound. Examples of suitable group IV elements or compounds include germanium, silicon germanium, and silicon carbide. Examples of suitable III-V compounds include gallium antimonide, gallium arsenide, gallium phosphide, aluminum antimonide, aluminum arsenide, aluminum phosphide, indium antimonide, indium arsenide, indium phosphide, and their ternary or quaternary compounds. Suitable III-V compounds may include III-nitrides, such as gallium nitride, aluminum nitride, and indium nitride. Examples of suitable II-VI compounds include zinc selenide, zinc sulfide, cadmium selenide, cadmium sulfide, and their ternary or quaternary compounds.

[0057] In some embodiments, an intermediate crystalline material (not shown) may be disposed in the opening between the crystalline material 40 and the substrate, such that the intermediate crystalline material is disposed adjacent to the top surface of the substrate and has a thickness sufficient to permit a majority of defects arising in the intermediate crystalline material near the top surface of the substrate to exit the intermediate crystalline material at a height below the top surface of the mask layer.

[0058] The crystalline material 40 may be formed by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low-(or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example, hydrogen. The reactor chamber may be heated by, for example, RF-heating. The growth temperature in the chamber may range from about 300 C. to about 900 C., depending on the composition of the crystalline material. The growth system may also utilize low-energy plasma to enhance the layer growth kinetics.

[0059] The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, an Aixtron 2600 multi-wafer system available from Aixtron, based in Aachen, Germany; an EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif.; or an EPSILON single-wafer epitaxial reactor available from ASM International based in Bilthoven, The Netherlands.

[0060] The crystalline material 40 may be lattice-mismatched to the substrate 10. In some embodiments, the crystalline material 40 is selected from a different group than the material of substrate 10. For example, substrate 10 may include a group IV element, e.g., Si, and the crystalline material 40 may include a III-V compound, e.g., GaAs.

[0061] In an exemplary process, a two-step growth technique is used to form high-quality crystalline material 40, e.g., consisting essentially of GaAs, in the opening 30. First, the substrate 10 and mask layer 35 are thermally annealed with hydrogen at approximately 1000 C. for approximately 10 minutes to desorb a thin volatile oxide from that substrate surface 15 that may be produced during pre-epitaxy wafer preparation. Chamber pressure during annealing may be in the range of approximately 50-100 torr, for example 75 torr. After annealing, the chamber temperature is cooled down with hydrogen flow. In order to suppress anti-phase boundaries (APDs) on substrate surface 15, a pre-exposure to As for about 1 to 2 minutes is performed. This step helps ensure uniform coverage of the trench surface with an AsAs monolayer. This pre-exposure is achieved by flowing arsine (AsH.sub.3) gas through the reactor at a temperature of approximately 460 C. Then, the precursor triethylgallium (TEG) or trimethylgallium (TMG) is introduced into the chamber together with AsH.sub.3 gas at a higher growth temperature, e.g., approximately 500 C. to 550 C. promote the initial GaAs nucleation process on the As pre-layer surface. This high temperature process helps ensure that the Ga atoms are sufficiently mobile to avoid GaAs cluster formation. A slow growth rate of about 2 to 4 nm per minute with VIII ratio of about 50 may be used to obtain this initial GaAs layer, with a thickness in the range of about 10 to 100 nm.

[0062] Then a layer of n-type GaAs having a thickness of 1 to 2 m is grown at a constant growth temperature of approximately 680 C. and a VIII ratio of approximately 200 to obtain defect-free GaAs material inside the opening 30. During this step, the crystalline material 40, i.e., GaAs epitaxial layer, may be formed such that its thickness t.sub.2 may be greater than the dielectric mask thickness t.sub.1. The crystalline material 40 may have a mushroom-type cross-sectional profile with lateral over growth over the mask layer 35; the top portion of the crystalline material 40 may coalesce with crystalline material formed in neighboring trenches (not shown) to form an epitaxial layer. A width w.sub.2 of the crystalline material 40 extending over a top surface 45 of the mask layer 35 may be greater than the width w of the opening 30. In this case, a small void may be formed between the laterally grown crystalline material layer and the top surface 45 of the mask layer 35. The overall layer thickness t.sub.2 of the crystalline material 40 may be monitored by using pre-calibrated growth rates and in situ monitoring equipment, according to methods known in the art.

[0063] Dislocation defects 20 in the crystalline material 40 reach and terminate at the sidewalls of the opening 30 in the dielectric material 35 at or below the predetermined distance H from the surface 15 of the substrate, such that dislocations in the crystalline material 40 decrease in density with increasing distance from the bottom portion of the opening 30. Accordingly, the upper portion of the crystalline material is substantially exhausted of dislocation defects. Various dislocation defects such as threading dislocations, stacking faults, twin boundaries, or anti-phase boundaries may be substantially eliminated from the upper portion of the crystalline material.

[0064] Thus, in some embodiments, the crystalline material 40 has a first region 40a disposed above and proximal to a portion of the top surface of the substrate 10 and a second region 40b disposed above the first region and above the portion of the top surface of the substrate, with the second region 40b having substantially fewer defects than the first region 40a. In other words, the crystalline material 40 may have two portions: a lower portion for trapping dislocation defects and an upper portion that either (i) incorporates the PV cell's epitaxial layers or (ii) serves as a template for the subsequent epitaxial growth of the PV cell's epitaxial layers. The height h of the crystalline material 40 thus has two components: the height h.sub.trapping of the lower portion (where defects are concentrated) and the height h.sub.upper of the upper portion (which is largely free of defects). The height h.sub.trapping of the trapping portion may be selected from a range of about wh.sub.trapping2w, to ensure effective trapping of dislocation defects. The actual value of h.sub.trapping required may depend upon the type of dislocation defects encountered, which may depend on the materials used, and also upon the orientation of the trench sidewalls. In some instances, the height h.sub.trapping can be greater than that required for effective defect trapping, in order to ensure that the dislocation defects are trapped at a sufficient distance away from the upper portion, so that deleterious effects of dislocation defects upon device performance are not experienced. For example, h.sub.trapping may be, e.g., 10-100 nm greater than required for effective trapping of defects. For the upper portion, the height h.sub.upper may be selected from the range of approximately wh.sub.upper10w.

[0065] In the embodiment of FIG. 1a and referring also to FIG. 4, epitaxial growth of the crystalline material 40 continues so that the crystalline material 40 within the opening 30 grows out and coalesces with crystalline material 40 formed in adjacent openings 30 to form a single contiguous crystalline material, e.g., GaAs, layer 50 above the openings in the mask layer. PVDs (also called referred to herein as solar cells) are then built above the crystalline material using various materials and techniques as are known in the art. For example, see Ringel, et al., Single junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers (Prog. Photovolt: Res. Appl 2002; 10:417-426 (DOI: 10.1002/pip.448)), Yamaguchi, et al., Super-high-efficiency Multi junction Solar Cells (Prog. Photovolt: Res. Appl. 2005; 13:125-132 (DOI: 10.1002/pip.606)) and Yamaguchi, et al., GaAs Solar Cells Grown on Si Substrates for Space Use (Prog. Photovolt: Res. Appl. 2001; 9:191-201 (DOI:10.1002/pip.366)), all of which are incorporated by reference herein in their entireties.

[0066] A planarization step such as, e.g., CMP may be used to planarize a top surface 55 of the contiguous crystalline material layer 50, to allow the formation of good quality films thereon. Alternatively, the top surface 55 may be left unplanarized, as a rough surface may be advantageous for capturing light in some devices.

[0067] By using ART techniques to trap defects that arise when epitaxially growing lattice-mismatched crystalline material over a substrate, e.g., forming a GaAs layer over a Si substrate, the top surface 55 of the crystalline layer has a suitably low defect level for building efficient PVDs with various materials for active PV regions, such as conventional III-V crystalline materials, III-nitride compounds or group IV-VI materials. PVDs built with these materials provide performance characteristics, such as efficiency and reliability that are superior to PVDs that use polycrystalline Si for active PV regions. The use of ART-configured openings to provide a relatively defect free top surface of crystalline material upon which to build PVDs is illustrative, and various other techniques are possible to provide a lattice-mismatched layer on a substrate that has a suitably low level of defects, such as, for example, other ART techniques disclosed in the references discussed above.

[0068] Referring to FIG. 2, an exemplary photovoltaic cell is illustrated that may be formed over the structure including the crystalline material 40 discussed with reference to FIG. 1a. A photovoltaic cell, or photonic device, may be a two junction solar cell device 200 including a starting template layer 110, a first (bottom) cell 120, a tunnel junction 130, and a second (top) cell 140. In use, when solar radiation strikes the solar cell device 200, the top cell 140 and bottom cell 120 each absorbs a portion of the solar radiation and converts the energy in the form of photons of the solar radiation to useable electric energy, measured in photovoltage and photocurrent. The illustrated two junction solar cell device 200 is configured to absorb light in two incremental steps. Thus, photons in the received sun light having energy greater than the designed band gap of the active top cell, i.e., second cell 140 (e.g., greater than about 1.75 eV), will be absorbed and converted to electricity across semiconductor junction 150 or may pass through the tunnel junction 130 to the next cell, i.e., first cell 120. Photons having less energy than the designed band gap of the top second cell 140 (e.g., less than about 1.75 eV) will pass through the top cell 140 to the next active cell, i.e., first cell 120. Such lower energy sun light may be absorbed and converted to electricity across junction 155.

[0069] In an exemplary process, the solar cell device 200 may be formed as follows. Device 200 is formed by epitaxial structural growth on a template layer 110. This template layer may include crystalline material 40, e.g., either p-type or n-type GaAs (or Ge) planarized with CMP or a coalesced layer formed above a patterned mask layer 35, as discussed above with reference to FIGS. 1a and 1b. A back surface field layer (BSF) 160 including, e.g., p-InGaP, is formed over the template layer 110 for photon absorption enhancement. The solar cell device includes a GaAs base layer 165 disposed over the BSF layer 160 and having a thickness of about 2-3 m, doped with a p-type dopant, such as zinc, to a concentration of about 1-310.sup.17/cm.sup.3. An emitter layer 170 of the first cell 120 may be n-type doped, e.g., GaAs doped with Si, to a concentration of about 1-210.sup.18/cm.sup.3 and may have a thickness of about 100 nm. A window layer 175 is formed over the emitter layer 65. The window layer 175 may include n-type InGaP doped with Si to a concentration of 1-210.sup.18/cm.sup.3, and may be grown to a thickness of about 100 nm. Window layer 175 is preferably an optically transparent layer that acts as an electrical barrier to avoid possible photocurrent backflow. The heavily doped tunnel junction 130, including n-type layer 177 and p-type layer 180, is used to facilitate the flow of photocurrent between top second cell 140 and first cell 120. The tunnel junction 130 may include a thin layer of any of a variety of materials that allow current to pass between first and second cells 120, 140 without generating a voltage drop large enough to significantly decrease the conversion efficiency of the device 200.

[0070] In the illustrated example, the top cell 140 is used for absorbing light with optical energy about 1.75 eV, and preferably includes a material lattice matched to GaAs, e.g., a ternary InGaP alloy. A desired band gap of top cell 140 may be realized by properly adjusting the compositional ratio of indium and gallium during InGaP growth. A p-type InGaP base layer 190 may have a thickness of about 500 nm and may be doped with zinc, to a concentration of 1-210.sup.17/cm.sup.3, and is disposed over a 50 nm thick bottom layer 185, which is doped to lower resistance, e.g., doped with zinc at a concentration of about 310.sup.18/cm.sup.3. Emitter layer 195 may include n-type InGaP with an n-type doping level of 1-210.sup.18/cm.sup.3 and a thickness of 100 nm. Window layer 197, disposed over layer 195, is thin enough to allow solar light pass through but thick enough to prevent photo-generated electron carrier recombination. Window layer 197 may include, e.g., a 30 nm thick AlInP window layer, doped with Si to a doping level of about 310.sup.17. An n-type cap layer 199, e.g., GaAs doped with Si to a doping level of 610.sup.18 with a thickness of about 100 nm, is used to form an ohmic contact. An electrical load (not shown) may be connected to the solar cell device 200 via grid electrical contacts on top of the solar cell device 200.

[0071] At least one active cell junction of the solar cell device may have a width w.sub.4 less than about 1 micrometer in a plane defined by the top surface of the substrate. The width w.sub.4 may be approximately equal to a wavelength of light selected from a range of 300 nm to 1800 nm, e.g., equal to 300 nm or 1800 nm. The width may be equal to a wavelength of light visible to a human eye. A length of the solar cell device may be approximately equal to a wavelength of light selected from a range of 300 nm to 1800 nm. The length may be greater than 1 millimeter. The solar cell device may include an active cell junction extending substantially away from the plane of the substrate.

[0072] FIG. 3 is a schematic cross-section drawing of another photovoltaic device that may be formed over crystalline material 40, i.e., a single solar cell device. Device 300 is a single cell structure, i.e., a cell element, confined within a micro-scaled dimension. It may be essentially completely fabricated within an opening in the mask layer 35 before coalescence growth occurs. This approach allows one to build micro- or submicrometer-scale PV cells (super lattice structure or quantum well configurations) inside localized defect-free area, which possesses advanced nano- or quantum-size characteristics in device performance.

[0073] Device 300 may be formed by epitaxy. In an exemplary process, prior to growth of device layers, a 500 nm SiO.sub.2 film is thermally deposited on substrate 10, and 0.2-0.5 m wide openings, e.g., along [110] direction of the substrate, are formed using conventional photolithography and RIE. Post-RIE, the patterned substrate is cleaned sequentially in Piranha, SC2, and diluted HF solutions. Near-surface damage to the Si crystal resulting from the RIE process may be reduced by a sacrificial oxidation and strip procedure. For example, a 25 nm sacrificial oxide layer may be formed on the surface including the openings, and subsequently removed by diluted HF prior to epitaxial growth. As a final component to the pre-epitaxial growth cleaning procedure, the patterned substrate may be thermally cleaned in an H.sub.2 ambient at an elevated temperature, for example, 1000 C. for 10 minutes using a commercially available MOCVD reactor at 70 torr.

[0074] In an embodiment, device 300 is formed as follows. An n or p-type GaAs buffer layer 205 is epitaxially grown at about 400 C. followed by the growth of a high temperature transition layer 210 at 700 C. The growth rates may be 7 nm/minute for the buffer layer 205 and 50 nm/minute for the transition layer 210. A back surface field layer 215 for enhancing solar light photo absorption, e.g., an n-type InGaP layer with a thickness of 50 nm, may be grown under the same temperature, doped with Si with a doping level of 310.sup.17/cm.sup.3. A GaAs base layer 220, with a thickness of, e.g., 300-600 nm, depending on oxide layer thickness, is grown with a slightly n-type doping concentration of Si of 510.sup.16/cm.sup.3, followed by the formation of an emitter layer 225. Emitter layer 225 may have a thickness of 150 nm and may include GaAs with a p-type concentration of Zn of about 110.sup.18/cm.sup.3. Similarly to the process described with respect to FIG. 2, a top window layer 230 and a cap layer 235 for making ohmic contact are grown to finish the cell structure. In particular, the top window layer 230 may be a p-type InGaP layer doped with Zn to a doping level of 210.sup.18/cm.sup.3.

[0075] The single cell structure illustrated herein is a simple model. The essential concept it provides may be used to derive various alternative structures, such as multi junction submicrometer PV cells, submicron or nano-scale 2-D and 3-D III-V/Si solar cells.

[0076] The exemplary modules illustrated in FIGS. 2 and 3 and variations thereof may be used in all of the following described embodiments of the invention. To simplify the description, the two junction solar cell device 200 shown in FIG. 2 is used to illustrate the structures shown in FIGS. 4-10 and 15-17 and the single solar cell device 300 shown in FIG. 3 is used to illustrate the structures shown in FIG. 11-14.

[0077] Epitaxial growth of the exemplary cell structures shown both in FIGS. 2 and 3 is preferably performed using conventional MOCVD growth methods. Appropriate metal organic precursors include TMG, TEG, trimethylindium (TMIn) and trimethylaluminum (TMA). Hydride precursors include phosphine and arsine. Typical materials that may be used as conductivity dopants in III-V materials are zinc, cadmium, magnesium, carbon, selenium and silicon. Since carbon is a p-type dopant for GaAs but an n-type donor for InP, use of zinc as a p-type dopant for both GaAs and InGaP cells may be preferable to prevent heterointerface mixing during monolithic structural growth between GaAs and InGaP layers. The growth temperature for devices 200 and 300 are varied within the range of approximately 580-720 C., depending on individual growth reactor design.

[0078] Referring to FIG. 4, in a one-step epitaxial growth process, coalesced contiguous crystalline material layer 50 is grown to a sufficient thickness above the substrate 10 so that the surface roughness and defect levels of the coalesced contiguous crystalline material layer 50 are suitable for constructing solar cell devices 200 thereon without any need for an additional planarization step. For example, the surface roughness may be less than 100 nm, and the defect level may be less than 10.sup.6/cm.sup.2 with the thickness t.sub.3 of the coalesced contiguous crystalline material layer 50 being, e.g., 2 micrometers.

[0079] Referring to FIGS. 5a-5c, in a two-step epitaxy process, after growing the crystalline material 40 to a predetermined thickness to define coalesced contiguous crystalline material layer 50 (FIG. 5a), a top surface of the coalesced layer 50 may be planarized by, e.g., CMP (FIG. 5b). This method may allow the formation of a device with a thinner underlying crystalline layer than that of a device made in accordance with the embodiment illustrated in FIG. 4. Referring to FIG. 5c, after the planarization step, in a second step, an additional layer 500, e.g., a regrowth layer including a crystalline material of the same type as the contiguous crystalline material layer 50, is regrown on top of the planarized crystalline material surface before fabrication of PVDs thereover.

[0080] The crystalline material 40 may include a material from the same group as a component of the substrate. Referring to FIG. 6a, for example, crystalline material 40 may include Ge grown in the ART-configured openings 30 defined by mask layer 35, e.g., SiO.sub.2, above substrate 10 consisting essentially of Si. The height of the Ge is less than the height of the SiO.sub.2 openings but, based on ART techniques, the height is sufficient for the top surface of the Ge layer to be relatively defect free. Referring to FIG. 6b, GaAs may then be grown above the Ge to create a coalesced contiguous crystalline material layer 50 consisting essentially of GaAs that is a suitable base for growing or depositing subsequent layers for PVD devices 200. As discussed with respect to the embodiment of FIG. 5, the GaAs contiguous crystalline material layer 50 may be planarized and regrown. The lattice-constant of Ge is relatively close to the lattice constant of GaAs, thereby reducing the density of stress-related defects in the GaAs.

[0081] Referring to FIG. 7a, in another embodiment, two growth steps are combined with planarization. Crystalline material 40, e.g., Ge, is epitaxially grown above the ART-configured openings 30 defined in masking layer 35 to form contiguous crystalline material layer 50. Referring to FIG. 7b, a planarization step, e.g., a CMP step is performed to planarize the surface of the coalesced crystalline material layer 50. Referring to FIG. 7c, a regrowth layer 700 including, e.g., GaAs, is subsequently epitaxially grown on the planarized surface of the Ge contiguous crystalline material layer 50. The regrowth layer 700 provides a foundation for the formation of PVDs 200.

[0082] In some embodiments, the masking layer 35 may be removed during processing, and additional crystalline material may be grown in the resulting openings. Referring to FIG. 8a, in a two step homo-epitaxial process, crystalline material 40, e.g., a III-V compounds such as GaAs, may be grown over substrate 10, e.g., Si, in openings 30 using ART techniques, such that defects in the crystalline material 40 exit at the sidewalls of the mask layer 35, e.g., SiO.sub.2. Then, as shown in FIG. 8b, the mask layer is selectively removed down to the substrate 10 to create new openings 30 between the GaAs crystalline material 40 regions. Referring to FIG. 8c, additional GaAs crystalline material 40 is deposited over the substrate 10 and the already present GaAs crystalline material 40 so that the crystalline material 40 coalesces to form contiguous crystalline material layer 50 of a suitable thickness for use as a base layer for the formation of PVDs 200. As discussed with respect to other embodiments, the GaAs contiguous crystalline material layer 50 may optionally be planarized, followed by optional regrowth, before the formation of PVD 200.

[0083] Similarly to the method illustrated in FIGS. 8a-8c, FIGS. 9a-9d illustrate an alternative method in which crystalline material 40 and the substrate 10 each may include a group IV material. Referring to FIG. 9a, a group IV material, e.g., Ge, is grown in openings 30 of a mask layer 35 over a Si substrate 10 using ART techniques. As shown in FIG. 9b, the mask layer 35 is then removed to create new openings 30 between the Ge regions. Referring to FIGS. 9c and 9d, either a III-V compound such as GaAs or a group IV material such as Ge, respectively, is grown over the existing crystalline material 40 and openings 30 to create a coalesced contiguous material layer 50 of GaAs or Ge. The GaAs layer provides a suitable base layer for PVDs 200. In the case of a coalesced Ge layer 50, after optional planarization, a III-V material such as GaAs (not shown) may be grown to provide a suitable base layer for PVDs. The growth of high quality Ge or GaAs layers such as the coalesced layers in FIGS. 8 and 9 provide virtual Ge or GaAs wafers atop a Si substrate, which may be useful in various applications in addition to PVD applications, such as light emitting devices or laser diodes.

[0084] Referring to FIG. 10, bonding may be used to create a virtual wafer suitable for applications such as PVDs. The first step is the growth of coalesced contiguous crystalline material layer 50 including, e.g., Ge or GaAs, in windows in a mask layer 35 disposed over a first substrate 10, such as by the ART techniques discussed above and illustrated in FIGS. 5 and 7. Then a top surface 1000 of contiguous crystalline material layer 50 is wafer bonded, after an optional planarization step, to a second substrate 1010, e.g., a Si or Si on insulator (SOI) or other compatible wafer platform. A virtual Ge or GaAs wafer 1020 is created atop the second Si or SOI substrate 1010 by removing the Si and SiO.sub.2 from the first Si wafer and then using CMP to planarize the exposed bottom surface 1030 of the Ge or GaAs layer. This virtual wafer 1020 may be further processed, e.g., with growth of an additional layer 1040 of e.g., a III-V compound such as GaAs, to create a base for PVDs 200, or the virtual wafer 1020 may be used in other applications that require or benefit from a relatively thin, larger size, high quality Ge or GaAs layer disposed atop suitable template.

[0085] Referring to FIG. 11, an array 1100 of PVDs may be built by use of a two-step heteroepitaxy process. Each PV cell may include the exemplary cell structure illustrated in FIG. 3 as device 300. Openings 30 are defined in a mask layer 35 disposed over on substrate 10 using ART techniques. The openings 30 may be configured as trenches. A layer of crystalline material 40, e.g., Ge, is grown at the bottom of the trenches to a height that allows defects to exit at the sides so that the top surface of the crystalline material 40 has a low level of defects. Then layers are sequentially grown above the Ge layer within the trenches to create PV devices 300.

[0086] Note that while FIG. 11 illustrates an array of elongated PVDs grown in trenches, ART techniques enable a wide variety of configurations for arrays of PVDs, such as arrays including PVDs formed as columns with circular cross-sections or as posts with square cross-sections. ART techniques also enable a wide variety of dimensions for the elements in PVD arrays. For example, a trench can be configured to be several millimeters long with a width on the order of one or two micrometers or smaller. Decreasing the width of an ART opening can decrease the height below which most defects are trapped, enabling the use of masks having thicknesses of about less than one micrometer, although in some embodiments a mask thickness in excess of one micrometer will be advantageous. Other embodiments can take advantage of sub-micrometer widths, such as a trench having a width in the range of 100 nanometers to 1 micrometer, or between 50 and 100 nanometers, or between 10 and 50 nanometers, or even smaller than 10 nanometers, or openings to create columns or posts with a maximum dimension (parallel to the substrate) of less than one micrometer, or less than 100 nanometers, or even less than 50 or 10 nanometers. Also, decreasing widths permits decreasing mask thicknesses.

[0087] In constructing the PV devices 300, an exemplary sequence of layers includes the growth of an n-type GaAs buffer layer above an n-type Ge layer in the trenches, followed by the growth of an n-type InGaP BSF layer, an n-type GaAs base layer, a p-type GaAs emitter layer, a p-type InGaP layer, and a p-type GaAs cap layer. For multi junction cells, an exemplary sequence of layers may include the growth of an n-type Ge layer above a p-type Ge layer to create a bottom cell, followed by the growth of an n-type InGaAs buffer layer, an n-type InGaP layer, and a p-type AlGaAs layer to create a tunnel junction. Subsequently, a p-type InGaP layer, a p-type InGaAs layer, an n-type InGaAs layer, and an n-type AlInP layer are grown to create a middle cell. An n-type InGaP layer and a p-type AlGaAs layer define another tunnel junction. Finally, a p-type AlInP layer, a p-type InGaP layer, an n-type InGaP layer, and an n-type AlInP layer are formed to create a top cell. In some embodiments, an active cell junction may be disposed above a top surface of the mask layer. In other embodiments, the active cell junction may be disposed below the top surface of the mask layer. In still other embodiments, the active cell junction may be disposed below the top surface of the substrate. The materials used to create cells and tunnel junctions, parameters such as doping levels and layer thicknesses, and materials for use as anti-reflective coatings and top contacts may be varied in accordance with methods known to those of skill in the art.

[0088] The length of PVDs built using the trenches may vary and be relatively long, for example extending virtually from edge to edge of a wafer. By using suitably narrow nanoscale trenches, the PVDs can provide a nanowire-type configuration of individual PVDs in an array that can be of a flexible size and shape. The PVD cells or elements within an array may be electrically interconnected with contacts 1110 formed from any of a variety of materials such as ITO, and in a variety of configurations as desired, for example in parallel as shown in the embodiment illustrated in FIG. 11. In alternative embodiments, some sub-arrays of PVD elements may be connected in parallel and other sub-arrays in series.

[0089] The height and width of PVDs may vary based on materials and design parameters. For the first exemplary sequence of layers for PV devices 300 discussed above, for example, the height may be selected from a range of approximately 0.5-3 micrometers and the width may be selected from a range of approximately 0.5-2 micrometers.

[0090] By configuring the width of PVDs built in the trenches to be wider than the width of the mask layer portions used to define trenches, a PVD array may cover more than half the area of a substrate upon which the array is formed. The trench and mask widths may be varied, and a wide variety of materials may be substituted to create the active regions of PVDs to create PVDs and PVD arrays with desired performance characteristics.

[0091] In the embodiment of FIG. 11, one option for the top contact 1110 for PVDs is to deposit an optically transparent and electrically conductive material layer, such as ITO. As an alternative to using ITO, another option for connecting PVDs is the use of metal contact wires to connect multiple PVDs in parallel. In both illustrated contact options, a bottom contact 1120 for the PVDs is provided on a bottom surface 1130 of the substrate 10. The substrate 10 is suitably doped such that an electrical path is formed from the bottom of the PV devices 300 through the crystalline material 40 and substrate 10. As illustrated in other embodiments, wafer thinning may be applied to the substrate 10 to reduce PV cell photocurrent resistance.

[0092] Alternative methods and configurations may be used to provide sub-micrometer PVD arrays. Referring to FIG. 12, ART-configured openings 30 configured as trenches are defined by a mask layer 35 over substrate 10. The openings 30 may define any of a number of patterns, such as a ribbing-type pattern 1200 or a finger-type pattern 1210. The mask layer 35 may be a compound mask having a first mask layer 1220 and a second mask layer 1230, with a chemical composition of the first layer being different from a chemical composition of the second layer. For example, the second mask layer may include SiO.sub.2 formed above the first mask layer including SiN.sub.x disposed above a Si substrate 10. Using the same techniques as discussed above with reference to FIG. 11, crystalline material 40 and PVD device 300 layers are grown in the trenches, and contacts 1110, e.g., metal contacts, are defined. In an embodiment, the second layer 1230 of the compound mask layer 35, i.e., SiO.sub.2, is selectively removed after formation of the PVDs 300 to expose the first layer 1220 of the compound mask layer, e.g., the SiN.sub.x layer that provides a reflective surface between the PVDs, so that photons 1240 that fall between the PVD nanowires will be reflected back and captured for conversion to electricity.

[0093] Those of skill in the art will appreciate that different materials may provide a reflective surface between the PVD elements. When creating the reflective surface, such as by deposition of a material layer, the surface can be faceted or otherwise configured to direct photons towards the PVDs so that a PVD nanotrench array that only covers about 50% of the surface of the substrate can still capture over 90% of the photons that strike the area defined by the perimeter of the array. PVD arrays may be configured to effectively capture the same percentage of photons as conventional PVDs that have no gaps within their outer perimeter.

[0094] The illustrated array may include a plurality of spaced-apart photonic devices disposed within a device perimeter on the top surface of the substrate defining a substrate surface area, with each photonic device including an active device junction between two semiconductor materials defining an active junction surface area, the combined active surface areas of the plurality of photonic devices being greater than the substrate surface area defined by the device perimeter. For example, the combined active surface areas of the plurality of photonic devices may be at least about 25% greater than the substrate surface area defined by the device perimeter. In some embodiments, the combined active surface areas of the plurality of photonic devices may be at least about 50%, 100%, 200%, or 400% greater than the substrate surface area defined by the device perimeter.

[0095] As mentioned briefly above, in one variation of the embodiment illustrated in FIG. 12, a finger-type mask pattern 1210 is used so that each nanowire element of the PVD array has a distinct perimeter completely separated from other elements. In another variation, a ribbing-type mask pattern 1200 is used so that the nanowires are connected to each other in a transverse direction. In the finger-type configuration, a top PVD contact 1110 is created by depositing a metal contact layer transversely across the top of the PVD array elements before removing the SiO.sub.2 layer to expose the underlying SiN.sub.x layer. In the ribbing-type configuration, a top PVD contact 1110 is created by depositing metal contact layers over the top of the PVD array in areas not covered by the mask, in this case in directions both parallel and transverse to the PVD array elements. Those of skill in the art shall readily recognize how to configure a suitable number of contact wires depending on the size and configuration of a PVD array.

[0096] Referring to FIG. 13, an alternative structure is formed by using a mask layer 35, including a second mask layer 1230 of SiO.sub.2 disposed above a first mask layer 1220 of SiN.sub.x to define trenches in a ribbing-type pattern 1200 using ART techniques. The first layer 1220 (SiN.sub.x) is sufficiently thick, e.g., about 300 nm, such that the majority of defects arising from lattice-mismatch of the crystalline material 40 grown in the trench, e.g., GaAs, exits at the sidewalls 1300 of the SiN.sub.x layer. In the illustrated embodiment, the second layer 1230 (SiO.sub.2) of the mask layer 35 is removed prior to the deposition all of the layers to create the PVD cell elements 300, resulting in PVD cells that have boundary layers with both vertical and horizontal portions. Top and bottom contacts 1110, 1120 are subsequently formed.

[0097] In the example of FIG. 13, a single junction cell element 300 has an n-GaAs buffer layer 1310 deposited on an n-type Si substrate 10 within the ART-configured trench. The majority of defects arising from lattice mismatch between the GaAs buffer layer 1310 and the Si substrate 10 exit at the sidewall 1300 created by the SiN.sub.x layer so that the top surface of the buffer layer is substantially free of defects. An n-InGaP BSF layer 1320 and n-GaAs base layer 1330 are then deposited over the buffer layer 1310 in the trench prior to removal of the SiO.sub.2 layer 1230 of the mask layer 35. After removal of the SiO.sub.2 layer, the base layer includes exposed sidewalls 1340. InGaP is preferably used for BSF layer 1320 because it has a wider band gap than GaAs, and has an enhanced lateral growth tendency in comparison to GaAs. BSF layer 1320 provides an electrical barrier layer for reducing undesired current back flow, reflects higher energy photons back for photon recycling, and improves initial facet orientation for GaAs grown on the InGaP.

[0098] A p-type GaAs emitter layer 1350 and a p.sup.+-GaAs cap layer 1360 are then deposited over the n-GaAs base layer 1330. By configuring the p-n junctions of the PVD cell element 300 to have both a top surface 1370 and lateral sidewall surfaces 1380, the p-n junction interface surface area can exceed the surface area of the Si substrate covered by the PVD array, for example, by 50%, 100%, or 200% or more, providing efficiency advantages over PVDs that have smaller p-n junction surface areas. While the embodiment of FIG. 13 illustrates a single-junction PVD cell, those of skill in the art will readily recognize how to construct multi junction cells, such as the configuration discussed above with reference to FIG. 11.

[0099] The electrical contacts for the PVD array of FIG. 9 are provided by, e.g., an n-type metal contact layer formed on the bottom of the n-type Si substrate and an array of p-type metal contacts provided atop the PVD cell elements. While a ribbing-type mask pattern 1200 is shown in FIG. 13, such that the p-metal contacts are provided atop the PVD cell elements in directions both parallel and transverse to the trenches, an alternative is to use a finger-type mask pattern 1210 as discussed above with reference to FIG. 12.

[0100] Referring to FIG. 14, in an embodiment of the invention, a crystal orientation of an underlying substrate is used to control the configuration of crystalline material formed thereover. For example, one may start with a (111) Si substrate 10. Here, a ribbing-type mask pattern 1200 is used with an SiO.sub.2 masking layer to define trenches. Those of skill will appreciate how to substitute or include other mask configurations and materials such as the finger-type configuration and SiN.sub.x mask material. By using techniques to control growth conditions to limit growth of sidewalls in the <110> direction, PVD cell elements 300 may be grown substantially vertically above the mask layer 35. It is known, for example, how to grow narrow pillars of a first semiconductor material above small mask openings on a wafer including the same material, e.g., how to grow GaAs above small mask openings on a GaAs wafer. See, e.g., Hamao et al., JJAP 36, L236 (1997) and Noborisaka et al., APL 86, 213102 (2005), incorporated herein by reference in their entireties. For example, when using MOCVD with a precursor of AsH.sub.3, the growth rates of the (111) surface and (110) surface are highly dependent on substrate temperature (T.sub.s) and partial pressure of the precursor (P.sub.AsH3) during MOCVD epitaxy. See e.g., S. Ando et al., JCG 145, 320 (1994), incorporated herein by reference in its entirety, and Hamao, et al. At higher T.sub.s and lower P.sub.AsH3, growth is faster on the (111) plane, so the crystalline material 40 may be formed with (110) sidewall facets. In order to promote growth on (110) planes to form a second semiconductor layer, such as second semiconductor layer 1410 discussed below, a reversed set of growth parameters may be used, with a lower substrate temperature T.sub.s and a relatively higher P.sub.AsH3.

[0101] By adapting such growth techniques for hetero-epitaxial growth of III-V materials on a (111) Si substrate, it is possible to grow materials substantially vertically and trap dislocations on the sidewalls during vertical growth. For example, aligning the openings or trenches 30 along a <110> direction of the (111) substrate takes advantage of the slow growth on the (110) face of a sidewall 1400 of the epitaxially grown crystalline material 40. This asymmetric growth technique may be applied to structures other than pillars, such as fins or nanowires that have one narrow dimension and one long dimension.

[0102] The mask layer 35 may define openings 30, e.g., configured as trenches, through which the first crystalline material 40 is formed on the substrate 10, the opening having a sidewall extending a predefined height from a top surface of the mask layer to a top surface of the substrate, the opening defining a width and a length adjacent the top surface of the substrate. The ratio of the height to the width may be greater than 1. In other embodiments, the ratio of the height to the width may be less than 1.

[0103] After controlled vertical growth of one type of PVD cell layer, for example, a first semiconductor crystalline material 40, such as an n-type GaAs base layer, growth of subsequent cladding layers, for example, starting with a second semiconductor layer 1410 of, e.g., a p-type GaAs emitter layer, can be promoted on the sidewalls of, e.g., the base layer, in the <110> direction to define an active device junction region. Contacts 1110 may be formed over the PVD cell structures 300.

[0104] Techniques such as this can be used to create PVD cells with p-n junction surface areas that greatly exceed the surface substrate surface area covered by the PVD array, for example, by more than 100% or 200%. The PVD cell structure 300, i.e., photonic device, formed by this method includes an active junction 1420 having a surface that extends in a direction substantially away from the top surface 15 of the substrate 10, e.g., in a direction substantially perpendicular to the substrate top surface. The active junction may include a sidewall surface 1420a coupled to a top surface 1420b, the sidewall surface extending substantially away from the top surface 15 of the substrate 10.

[0105] A portion of the active junction may be adjacent the top surface of the mask layer, and the mask layer may electrically isolate the active junction from the substrate. The mask layer may also isolate a third semiconductor layer 1430 disposed on the second semiconductor layer 1420 from the substrate 10. The top surface of the mask layer may be substantially optically reflective.

[0106] The active cell junction may be disposed below a top surface of the substrate. The active cell junction may have a shape corresponding to a shape defined by the intersection of the opening in the mask layer and the top surface of the substrate. The active cell junction may include a doped layer proximal to the top surface of the substrate, or a doped layer proximal a bottom surface to the substrate.

[0107] The photonic device may include, e.g., a photovoltaic device, a plurality of multi junction photovoltaic devices, a light-emitting diode (LED), or a plurality of LEDs connected in parallel.

[0108] As illustrated in FIGS. 11-14, a device may include a first photonic device structure disposed above a first region of a substrate, the first photonic device structure including a first top surface and a first uncovered sidewall surface, and a second photonic device structure disposed above a second region of the substrate and spaced apart from the first structure, the second photonic device structure including a second top surface and a second uncovered sidewall surface. A conductive layer may extend from the first top surface of the first photonic device structure to the second top surface of the second photonic device structure above the first and second uncovered sidewall surfaces of the first and second structures to electrically couple the first and second top surfaces. The conductive layer may include a material such as, for example, Al, Ag, Ti, Sn, Cr, and/or Si.

[0109] FIGS. 15-17 illustrate features that may be included in various embodiments such as the embodiments of FIGS. 4-7 and 11-14. Referring to FIG. 15, localized n-type Si regions 1500 in a p-Si substrate 10 are formed by thermal annealing after growth of the III-V crystalline material 40 for the PVD cell 200 buffer layer. For example, GaP, GaSb and properly optimized GaAs materials are highly diffusive to Si. They are suitable wetting layers to over-compensate a p-type Si dopant and form p-n junctions at the bottom of trenched areas, e.g., the junctions between the localized n-type Si regions and the p-type substrate. Thus, additional localized p-n junction arrays are made on the Si substrate, which further enhances overall PV cell efficiency without altering the previously described structures. In such embodiments, an active cell junction is disposed below the top surface of the substrate. The shape of the active cell junction may correspond to a shape defined by an intersection of the opening in the mask layer 35 and the top surface 15 of the substrate 10. In some embodiments, p-type Si regions may be formed in an n-Si substrate.

[0110] The embodiment illustrated in FIG. 16 includes the formation of a p-n junction 1600 by epitaxially growing a thin film 1610 of n-type Si over a p-type Si substrate 10 before forming mask layer 35. Alternatively, one may grow a film of p-type Si over an n-type Si substrate. Here, an active cell junction, i.e., p-n junction 1600, is disposed below the top surface of the substrate upon which PVDs 200 shall be fabricated, and includes a doped layer, i.e., thin film 1610, proximal to the top surface of the substrate.

[0111] Referring to FIG. 17, in another embodiment, a p-n junction 1700 is formed near the bottom surface 1130 of the substrate 10 by diffusing an n-type dopant into a p-type Si substrate to form a doped layer 1710, prior to the formation of mask layer 35. Similarly to FIG. 16, an alternative is to diffuse p-type dopants into an n-type Si substrate. In this embodiment, an active cell junction is disposed below the top surface of the substrate and includes a doped layer 1710 proximal to the bottom surface of the substrate 10.

[0112] Referring to FIGS. 18 and 19, embodiments of the invention include ART-based dual junction cells. In each of the exemplary dual junction cells, the design of the top cell is de-coupled from the design of the bottom cell so that one may customize the design parameters of each cell without concern for lattice matching. Moreover, the use of ART allows a combination of a Si-based lower cell with a lattice-mismatched III-V-based upper cell.

[0113] In addition, the 2-D/3-D structure allows for a fully depleted core/center. For example, in the auto doped structure of FIG. 19, the n-InGaP core 1940 may be fully depleted when covered with a p+ InGaP layer 1935, resulting in improved performance due to higher carrier velocities.

[0114] In FIGS. 18 and 19 a bottom region of the crystalline material 40 disposed in the ART opening 30 is heavily doped, which for PVD applications provides an advantage of mitigating potentially negative impact on performance that may arise from recombination of electrons and holes facilitated by the presence of defects. To avoid having depletion zones that encompass the region of trapped defects, appropriate doping levels are preferably used to either keep the depletion regions outside the defect regions or else to reduce the size of the depletion zones in the area of defect regions. In the exemplary structures of FIGS. 18 and 19, the tunnel junctions in or near the regions of trapped defects are heavily doped and create very small depletion zones.

[0115] More specifically, referring to FIG. 18, in an embodiment, a dual junction cell 1800 includes an n+/p III-V top cell 1805 with a bandgap of 1.7 eV disposed over an n+/p Si bottom cell 1810 with a bandgap of 1.1 eV. A summary of the components of the dual junction cell 1800, from top to bottom, is as follows: [0116] 1810top contact [0117] 1815, 1820contact layersGaAs doped with Si facilitating a low resistance contact from the semiconductor GaAs layer to the top contact layer [0118] 1825/1840transition layers [0119] 1830/1835top cell 1805 [0120] 1845/1850tunnel junction [0121] 1855/1860bottom cell 1810 [0122] 1865contact layer [0123] 1830bottom contact [0124] 1875/1880two layers left from a 3-layer mask/dielectric (top SiOx layer etched away after layer 6 InGaP is grown).
More particularly, the dual junction cell includes, from the top down, the following layers, with an exemplary structure including the indicated particular materials and thicknesses: [0125] top contact grid 1810, e.g., an Al grid; [0126] contact layer 1815 formed by ohmic contact doping, e.g., a Si doping spike; [0127] contact layer 1820 including an n++ ohmic layer, having a thickness selected from a range of 75-1000 nm, e.g., a 500 nm layer of GaAs, n-doped with Se to a level of 610.sup.18/cm.sup.3; [0128] window layer defining a transition layer 1825, having a thickness selected from a range of 20-35 nm, n+ doped and lattice matched to cell layer 5, e.g., a 25 nm layer of AlInP, n-doped with Si to a level of 410.sup.17/cm.sup.3; [0129] n+ polarity layer 1830 defining a first layer of the top cell 1805, composition designed to provide efficiency, with a band gap E.sub.g of 1.7 eV and having a thickness selected from a range of 75-150 nm, e.g., a 100 nm thick layer of GaInP, n-doped with Se to a level of 210.sup.18/cm.sup.3; [0130] p polarity layer 1835, composition designed to provide efficiency, with a band gap E.sub.g of 1.7 eV and having a thickness selected from a range of 500-1000 nm, e.g., a 750 nm layer of GaInP with a bandgap E.sub.g of 1.7 eV, p-doped with Zn to a level of 1.510.sup.17/cm.sup.3; [0131] n+ back surface field layer 1840, lattice matched to cell layer 1835, having a thickness selected form a range of 30-100 nm, e.g., a 50 nm thick layer of GaInP with a bandgap E.sub.g of 1.7 eV, p-doped with Zn to a level of 310.sup.18/cm.sup.3; [0132] p++ layer 1845 lattice matched to n+ back surface field layer 1840, having E.sub.g=1.7 eV and having a thickness selected from a range of 100-150 nm, e.g., a 100 nm thick layer of GaAs, p-doped with C to a level of 810.sup.19/cm.sup.3; [0133] n++ layer 1850 lattice matched to layer 1845, having E.sub.g=1.7 eV, having a thickness selected from a range of 100-150 nm, e.g., a 100 nm thick layer of GaAs, n-doped with Se to a level of 110.sup.19/cm.sup.3; [0134] n+ Si layer 1855 with an E.sub.g of 1.1 eV doped with, e.g., As; [0135] p Si layer 1860 with an E.sub.g of 1.1 eV doped with, e.g., B; [0136] diffused Al:Si layer 1865; [0137] Al back contact layer 1870; [0138] SiN.sub.x etch stop layer 1875 having a thickness of, e.g., 100 nm; and [0139] SiO.sub.x layer 1880 having a thickness of, e.g., 250 nm.

[0140] Referring to FIG. 19, in another embodiment, a dual junction cell is autodoped by Si and includes a p+/n III-V top cell 1905 with a bandgap of 1.7 eV disposed over a p+/n Si bottom cell 1910 with a bandgap of 1.1 eV. An advantage of the illustrated auto-doped structure is that using a heavily doped III-V material in the ART region allows one to benefit from Si diffusion in that Si diffusion effectively provides n-type doping Alternatively, if the heavy doping at least mitigates or eliminates potential problems caused by diffusion of Si into the III-V material during processing. A summary of the components of the dual junction cell is as follows:

[0141] More particularly, the dual junction cell of FIG. 19 includes, from the top down, the following layers, with an exemplary structure including the indicated particular materials and thicknesses: [0142] top contact grid 1915, e.g., an Al grid; [0143] ohmic contact doping layer 1920; [0144] p++ ohmic contact layer 1925 having a thickness of selected from a range of 75-1000 nm, e.g., a 100 nm thick layer of p++ GaAs; [0145] a p+ window layer 1930 lattice matched to cell layer 5 and having a thickness selected from a range of 20-35 nm, e.g., a layer of p+ InAlGaP having a thickness of 30 nm; [0146] a p+ polarity layer 1935 having a band gap E.sub.g of 1.7 eV and a thickness selected from a range of 75-150 nm, with a composition tailored for efficiency, e.g., a layer of p+ InGaP having a thickness of 50 nm; [0147] an n polarity layer 1940 having a band gap E.sub.g of 1.7 eV and a thickness selected from a range of 500-1000 nm, with a composition tailored for efficiency, e.g., a layer of n InGaP having a thickness of 550 nm (layers 1935, 1940 forming top cell 1905); [0148] a back surface field layer 1945 having a thickness selected from a range of 30-100 nm and lattice matched to cell layer 6, e.g., a layer of n+ InAlGaP having a thickness of 30 nm; [0149] an n++ layer 1950 lattice matched to back surface field layer 1945, having a band gap of E.sub.g=1.7 eV and a thickness selected form a range of 250-300 nm, e.g., a layer of n++ GaAs having a thickness of 300 nm; [0150] a p++ doped Si layer 1955 having a thickness selected from a range of 20-30 nm, e.g., 20 nm; [0151] a p+ Si layer 1960 having a band gap E.sub.g of 1.1 eV; [0152] an n Si layer 1965 having a band gap E.sub.g of 1.1 eV; [0153] a diffused Al: Si layer 1970; [0154] an Al back contact layer 1975; [0155] an SiN.sub.x etch stop layer 1980 having a thickness of 100 nm; and [0156] an SiOx layer 1985 having a thickness of 250 nm.

[0157] Referring to FIG. 20, a process flow for forming a PVD by ART is summarized. In a particular embodiment, a starting material is a p+ Si wafer. Arsenic is diffused into the wafer to define an n-type region. A thermal oxide having a thickness of 250 nm is grown over the wafer. PECVD is used to define a mask layer by depositing a 100 nm thick layer of SiN.sub.x and 750 nm of SiO.sub.x. Photolithographic and reactive ion etch steps are performed to define windows in the mask layer. The photoresist is removed by a wet strip and dry ash, and the wafer is cleaned. A pre-epitaxial clean is performed, followed by a first III-V epitaxial step to deposit the PVD layers up through the core layer, e.g., layers 1835, 1840, 1845, and 1850 of FIG. 18. A wet etch with HF is performed to remove a portion of the mask layer, i.e., the upper SiO.sub.x portion. A second III-V epitaxial step is performed to deposit the remaining III-V layers over the core layer. A back side Al diffusion defines a back side contact. A front side contact layer is deposited, and a grid is defined by lithography and etch steps. The photoresist is stripped and the wafer cleaned. The wafer is diced into discrete devices and tested. The devices are tested and supplied to a module manufacturer.

[0158] Many of the embodiments discussed above describe providing PVDs over monocrystalline Si substrates. Those of skill in the art understand how to substitute other substrate materials. For example, poly-crystalline or amorphous Si substrates may be used as more cost-effective alternatives with suitable efficiency levels for many applications.

[0159] Aspects of the embodiments discussed above also provide utility for applications other than PVDs. For example, other device applications such as photonics, e.g., LEDs, can benefit from the ability to create vertically grown hetero-epitaxial materials using Si substrates. Inventive aspects of the foregoing embodiments include combinations and variations to implement photovoltaic and other devices comprising a variety of elements.

[0160] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.