METHOD AND APPARATUS FOR CONVERSION OF VALUE OF ANALOG SIGNAL TO COMPRESSED DIGITAL WORD

Abstract

Method for conversion of a value of an analog signal to a compressed digital word uses conversion of the analog signal to a linear digital word according to a successive approximation scheme. The process of conversion of the analog signal to the linear digital word is terminated by the compression module when all bits of the compression word have been already evaluated. Apparatus for conversion of a value of an analog signal to a compressed digital word a linear successive approximation analog-to-digital converter. The output of the linear digital word of this converter is connected to the input of the linear digital word of the compression module comprising a section number register, while complete conversion signal output of the compression module is connected to a complete conversion signal input of the linear analog-to-digital converter, and a bit ready signal output of the linear analog-to-digital converter is connected to a bit ready signal input of the compression module.

Claims

1. A method for conversion of a value of an analog signal to a compressed digital word using a conversion of the analog signal to a linear digital word according to a successive approximation scheme, while a number of bits of the linear digital word is not lower than m, and at the same time, the number of bits of the linear digital word is higher than a number of bits of a compressed digital word, and the number of bits of the compressed digital word is not lower than n, whereas the bits of the linear digital word are already evaluated by the use of a linear analog-to-digital converter and provided to a linear digital input, wherein the conversion of a value of the analog signal to the linear digital word (LW) is terminated by the use of a compression module (CPM) when all bits of the compression word (CW) are already evaluated, while a compression starts when the compression module (CPM) detects an active state on a compression trigger input (TrgCP), and then a number equal to a difference between numbers m and v is written to a section number register (RegS) in the compression module (CPM), while v is an arbitrarily chosen natural number smaller than n, and after detection, on the basis of a bit ready signal (BitRdy), that a new output bit in the linear digital word (LW) has been evaluated by the linear analog-to-digital converter (SA-ADC), a content of the section number register (RegS) is decreased by one if a state of the new output bit in the linear digital word (LW) has been evaluated to zero, while the content of the section number register (RegS) is not decreased if a state of the new output bit in the linear digital word (LW) has been evaluated to one, or if the content of the section number register (RegS) has been already reduced to zero, and then, in both cases, the evaluation of next v bits of the linear digital word (LW) by the linear analog-to-digital converter (SA-ADC) is awaited, and a number of v occurrences of a bit ready signal (BitRdy) is counted, and afterwards, a complete conversion signal (End) is generated by the compression module (CPM), which terminates the conversion of the analog signal to the linear digital word (LW), and introduces the linear analog-to-digital converter (SA-ADC) to a stand by state, while the states of v bits of the linear digital word (LW) evaluated recently are assigned by the compression module CPM respectively to the least significant v bites of the compressed word (CW), and the content of the section number register (RegS) is written by the compression module CPM to the more significant bites of the compressed word (CW).

2. The method according to claim 1, wherein the analog signal is unipolar, the compression word (CW) contains a number of n=s+v bits, and a process of decreasing of the content of the section number register (RegS) is started as soon as the most significant bit in the linear digital word (LW), having a number of m bits, is evaluated by the linear analog-to-digital converter (SA-ADC).

3. The method according to claim 1, wherein the analog signal is bipolar, the compression word (CW) contains a number of n+1=s+v+1 bits, and a process of decreasing of the content of the section number register (RegS) is started as soon as a bit following the most significant bit in the linear digital word (LW), having a number of m+1 bits, is evaluated by the linear analog-to-digital converter (SA-ADC), while a state of the most significant bit in the linear digital word (LW) representing a sign of an analog signal value (Sg) according to a sign-magnitude format is by the use of the compression module (CPM) assigned to the most significant bit of the compressed word (CW) having the number of m+1 bits.

4. An apparatus for conversion of a value of an analog signal to a compressed digital word using a conversion of a value of an analog signal to a linear digital word according to a successive approximation scheme whose linear digital word output having a number of bits not lower than m is connected to a linear digital word input of a compression module comprising a compressed digital output having a number of bits not lower than n, while the number of bits of the linear digital word input is not higher than the number of bits of the compressed digital word, wherein the compression module (CPM) comprises a section number register (RegS), while a complete conversion signal output (End) of the compression module (CPM) is connected to a complete conversion signal input (End) of the linear analog-to-digital converter (SA-ADC), and a bit ready signal output (BitRdy) of the linear analog-to-digital converter (SA-ADC) is connected to a bit ready signal input (BitRdy) of the compression module (CPM).

5. The apparatus according to claim 4, wherein a compression trigger input (TrgCP) of the compression module (CPM) is connected to a conversion trigger input (TrgADC) of the linear analog-to-digital converter (SA-ADC).

6. The apparatus according to claim 4, wherein the compression trigger input (TrgCP) of the compression module (CPM) is connected to an analog input (InADC) of the linear analog-to-digital converter (SA-ADC).

7. The apparatus according to claim 5, wherein the linear analog-to-digital converter (SA-ADC) is a synchronous device, and a bit ready signal output (BitRdy) of the linear analog-to-digital converter (SA-ADC) comprises a single line transmitting a signal that provides timing for the linear analog-to-digital converter (SA-ADC) operation.

8. The apparatus according to claim 5, wherein the linear analog-to-digital converter (SA-ADC) is a known asynchronous device comprising two comparators, and a bit ready signal output (BitRdy) of the linear analog-to-digital converter (SA-ADC) contains two lines that transmit output signals of both comparators.

9. The apparatus according to claim 7, wherein the linear analog-to-digital converter (SA-ADC) is a converter of a unipolar input signal comprising a linear output (LW) having a number of m bits, while the compression module (CPM) contains an output of the compressed word (CW) having a number of n bits.

10. The apparatus according to claim 7, wherein the linear analog-to-digital converter (SA-ADC) is a converter of a bipolar input signal comprising a linear output (LW) having a number of m+1 bits representing a sign-magnitude format, while the compression module (CPM) contains an output of the compressed word (CW) having a number of n+1 bits.

Description

[0023] The solution according to the invention is presented in the following figures:

[0024] FIG. 1 illustrates the block diagram of the apparatus, in which the compression trigger input TrgCP of the compression module CPM is connected to the conversion trigger input TrgADC of the synchronous linear analog-to-digital converter SA-ADC.

[0025] FIG. 2 illustrates the block diagram of the apparatus, in which the linear analog-to-digital converter SA-ADC is a known asynchronous device, and a bit ready signal output BitRdy contains two lines.

[0026] FIG. 3 illustrates a format of the linear digital word LW and the compressed digital word CW for conversion of unipolar signal.

[0027] FIG. 4 illustrates a format of the linear digital word LW according to a sign-magnitude representation and the compressed digital word CW for conversion of bipolar signal.

[0028] Method for conversion of a value of an analog signal to a compressed digital word, according to the invention, adopts a conversion of a unipolar analog signal to a linear digital word using successive approximation scheme. Bits of the linear digital word LW, having a number of m=11 bits are evaluated successively using the linear analog-to-digital converter SA-ADC, and are provided to the linear digital input LW of a compression module CPM.

[0029] The conversion of a value of the analog signal to the linear digital word LW is terminated by the use of the compression module CPM as soon as all the bits of the compressed digital word CW, having a number of bits equal to 7, are evaluated. The compression process is started when an active state on a compression trigger input TrgCP is detected by the compression module CPM. Then, a number 7 equal to a difference between the numbers m=11 and v=4 is written to a section number register (RegS) in the compression module CPM, while v=4 is chosen arbitrarily. After detection, on the basis of a bit ready signal BitRdy, that a new output bit in the linear digital word LW has been evaluated by a linear analog-to-digital converter SA-ADC, a content of the section number register RegS is decreased by one if a state of the new output bit has been evaluated to zero. The reduction of the content of the section number register RegS is started as soon as the most significant bit in the linear digital word LW is evaluated on the output the linear analog-to-digital converter SA-ADC. The content of the section number register RegS is not reduced if a state of the new output bit in the linear digital word LW has been evaluated to one, or if the content of the section number register RegS has been already reduced to zero. Then, in both cases, the evaluation of the next v bits of the linear digital word LW by the linear analog-to-digital converter SA-ADC is awaited, while a number v is equal to 4, and a number of occurrences of bit ready signal BitRdy up to 4 has been counted. Afterwards, a complete conversion signal End is generated by the compression module CPM, which terminates the conversion of the analog signal value to the linear digital word LW and introduces the linear analog-to-digital converter SA-ADC to a stand by state. The states of v=4 bits of the linear digital word LW evaluated recently are assigned respectively to the least significant v=4 bites of the compressed digital word CW. The content of the section number register RegS is written to a number of s of more significant bites of the compressed digital word CW, while s is equal to 3.

[0030] In another variant of the method for conversion of a value of the analog signal to the compressed digital word, according to the invention, adopts a conversion of a bipolar analog signal to the linear digital word using successive approximation scheme. A number of m+1 bits of the linear digital word LW equals 12, and a number of n+1 bits of the compression word CW equals 8.

[0031] This variant of the method differs from the previous variant in that a process of reduction of the content of the section number register RegS is started as soon as a bit following the most significant bit in the linear digital word LW has been evaluated by the linear analog-to-digital converter SA-ADC. A state of the most significant bit in the linear digital word LW representing a sign of an analog signal value Sg according to a sign-magnitude format is by the use of the compression module CPM assigned to the most significant bit of the compressed digital word CW (FIG. 4).

[0032] The apparatus for conversion of a value of the analog signal to the compressed digital word in the first embodiment, according to the invention, comprises the 11-bit synchronous unipolar linear successive approximation analog-to-digital converter SA-ADC (FIG. 1). A linear digital word LW output of the linear analog-to-digital converter SA-ADC, having a number of bits equal to 11, is connected to a linear digital word LW input of a compression module CPM comprising a section number register RegS and a compressed digital word CW output, having a number of bits equal to 7, a and complete conversion signal output End, connected to a complete conversion signal input End of the linear analog-to-digital converter SA-ADC. A bit ready signal output BitRdy of the linear analog-to-digital converter SA-ADC comprising a single line transmitting a signal that provides timing for the linear analog-to-digital converter SA-ADC operation is connected to a bit ready signal input BitRdy of the compression module CPM. A compression trigger input TrgCP of the compression module CPM is connected to a conversion trigger input TrgADC of the linear analog-to-digital converter SA-ADC.

[0033] In the second embodiment, the apparatus comprises a known 11-bit synchronous unipolar linear successive approximation analog-to-digital converter SA-ADC comprising a set of capacitors A connected to a control module CM by the use of lines transmitting control signals Ctr (FIG. 2). A first comparator K1 and a second comparator K2 are connected to the set of capacitors A. Outputs of both comparators are connected respectively to a first input In1 and to a second input In2 of the control module CM. An output of the linear digital word LW of the control module CM, having a number of bits m equal to 11, is connected to an input of the linear digital word of the compression module CPM comprising a section number register RegS, and an output of the compressed digital word CW having a number of bits n equal to 7, and a complete conversion signal output End of the control module CM. A bit ready signal output BitRdy of the linear analog-to-digital converter SA-ADC, comprising two lines transmitting output signals both of the first comparator K1 and of the second comparator K2, is connected to a bit ready signal input BitRdy of the compression module CPM. A compression trigger input TrgCP of the compression module CPM is connected to an analog input InADC of the control module CM, which is the input for conversion of time intervals.

[0034] In the third embodiment, the apparatus differs from the first embodiment in that the apparatus comprises a 12-bit synchronous bipolar linear analog-to-digital converter SA-ADC, whose output of the linear digital word LW, having a number of bits m+1=12 is connected to the input of the linear digital word of the compression module CPM (FIG. 1). The compression module CPM comprises the output of the compressed digital word CW having a number of bits n+1=8.

[0035] The conversion of a value of the analog signal to the compressed digital word In the first embodiment is realized as follows (FIG. 1). As soon as an active state on a compression trigger input TrgCP is detected by the compression module CPM, a number m-v=7 is written to a section number register RegS in the compression module CPM. At the same time, an active state of the conversion trigger input TrgADC by the linear analog-to-digital converter SA-ADC, the conversion of a unipolar value of an analog signal provided to the analog input InADC to the linear digital word LW, having a number of bits equal to 11, according to a known successive approximation scheme, is started. The states of bits of the linear digital word LW are successively evaluated in a known way by the linear analog-to-digital converter SA-ADC, and at the same time provided to the input of the linear digital word of the compression module CPM.

[0036] The linear analog-to-digital converter SA-ADC by the use of the bit ready signal BitRdy signalizes to the compression module CPM that a new output bit in the linear digital word LW has been evaluated. As soon as the compression module CPM, on the basis of the bit ready signal BitRdy, detects that a new output bit in the linear digital word LW by the linear analog-to-digital converter SA-ADC has been evaluated, the content of the section number register RegS is decreased by one if a state of a new output bit in the linear digital word LW has been evaluated to zero, and the cycle of evaluation and the analysis of next bits are repeated. The compression module CPM terminates a process of decreasing the content of the section number register RegS if a state of a new output bit in the linear digital word LW has been evaluated to one, or if the content of the section number register actually RegS has been already reduced to zero.

[0037] Then, in both cases, the evaluation of the next v bits of the linear digital word LW by the linear analog-to-digital converter SA-ADC is awaited, and a number of v occurrences of the bit ready signal BitRdy is counted, while v equals 4. Afterwards, a complete conversion signal End is generated by the compression module CPM, which terminates the conversion of the analog signal to the linear digital word LW, and introduces the linear analog-to-digital converter SA-ADC to a stand by state. The states of v bits of the linear digital word LW evaluated recently are assigned by the compression module CPM respectively to the least significant v bites of the compressed word CW, while v equals 4 (FIG. 3). The content of the section number register RegS is written by the compression module CPM to the more significant s bites of the compressed word CW, while s equals 3 (FIG. 3).

[0038] The conversion of a value of an analog signal to a compressed digital word in the second embodiment (FIG. 2) is realized as follows. As soon as an active state on a compression trigger input TrgCP is detected by the compression module CPM, a number equal to 7 which is a difference between numbers m and v is written to a section number register RegS in the compression module CPM. At the same time, when a beginning of a time interval which is signalled at an analog input InADC, the linear analog-to-digital converter SA-ADC starts the conversion of the time interval provided to the analog input InADC to the linear digital word LW, having a number of bits equal to 11, according to a known successive approximation scheme. The values of bits of the linear digital word LW are successively evaluated in a known way by the linear analog-to-digital converter SA-ADC, and at the same time provided to the input of the linear digital word of the compression module CPM.

[0039] The linear analog-to-digital converter SA-ADC terminates the evaluation of the output bits when a short active state is generated on the output of the first comparator K1, or on the output of the second comparator K2. The states of the outputs of both comparators are transmitted by the use of two lines of the bit ready signal output BitRdy of the compression module CPM.

[0040] As soon as the compression module CPM, on the basis of the bit ready signal BitRdy, detects that a new output bit in the linear digital word LW by the linear analog-to-digital converter SA-ADC has been evaluated, the content of the section number register RegS is decreased by one if a state of the new output bit in the linear digital word LW has been evaluated to zero, and the cycle of evaluation and the analysis of next bits is repeated. The compression module CPM terminates a process of decreasing the content of the section number register RegS if a state of a new output bit in the linear digital word LW has been evaluated to one, or if the content of the section number register actually RegS has been already reduced to zero.

[0041] Then, in both cases, the conversion of the value of the analog signal to the compressed digital word is continued in the same way as in the first embodiment.

[0042] The conversion of a value of an analog signal to a compressed digital word in the third embodiment differs from the conversion in the first embodiment in that the compression module CPM starts the process of decreasing of the content of the section number register RegS as soon as a bit following the most significant bit in the linear digital word LW. The state of the most significant bit in the linear digital word LW representing a sign of an analog signal value Sg according to a sign-magnitude format is by the use of the compression module CPM assigned to the most significant bit of the compressed word CW (FIG. 4).

Acronyms

[0043] SA-ADC linear analog-to-digital converter [0044] CPM compression module [0045] InADC analog input [0046] RegS section number register [0047] LW linear digital word [0048] CW compressed digital word [0049] End complete conversion signal [0050] BitRdy bit ready signal [0051] TrgADC conversion trigger input [0052] TrgCP compression trigger input [0053] Sg sign of an analog signal value [0054] A set of capacitors [0055] CM control module [0056] K1 first comparator [0057] K2 second comparator [0058] In1 first input of control module [0059] In2 second input of control module